KR19990010376A - Contact hole formation method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a contact hole of a semiconductor device having a different process hole formation method using a self aligned contact (SAC) process, which increases the process margin and improves the reliability of the device. Forming cell transistors including a gate electrode, a cap insulating layer surrounding the gate electrode, and a gate sidewall on the semiconductor substrate having a gate electrode, and forming an interlayer insulating layer using an oxidizing material on an entire surface of the semiconductor substrate on which the cell transistors are formed; Forming a first nitride film layer and a photoresist layer on the interlayer insulating layer and selectively patterning the photoresist layer; and using the patterned photoresist layer as a mask by dry etching to form the first nitride film layer and the interlayer. Selectively etching the insulating layer to leave the interlayer insulating layer at a lower thickness in the first contact Forming a hole, forming a second nitride film layer on the entire surface including the contact hole, and etching back to form a nitride sidewall on an inner side surface of the primary contact hole, and forming the first nitride film layer and the nitride sidewall And forming a secondary contact hole through which the interlayer insulating layer exposed by the SAC process by wet etching is completely removed by wet etching as a mask to expose the impurity diffusion regions on one side of the cell transistors.

Description

Contact hole formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a contact hole in a semiconductor device having a different process contact formation method using a SAC (Self Aligned Contact) process to increase the process margin and increase the reliability of the device.

In the process of forming a metal wiring in a device such as a DRAM, the metal wiring is formed as a cap structure of a (conductive material layer / nitride film), and sidewalls are formed by applying / etching a nitride layer to form a contact hole. Sidewalls are used as an etch stopper. Such a process is called a SAC process.

Hereinafter, a process for forming a contact hole in a semiconductor device of the prior art will be described with reference to the accompanying drawings.

1A and 1B are cross-sectional views of a prior art self-aligned contact technique.

In the method of forming a contact hole using the SAC of the prior art, first, as shown in FIG. 1A, a conductive material layer is formed on the semiconductor substrate 1 on which the active region is defined by the device isolation layer 2. And forming a nitride film layer on the conductive material layer.

Subsequently, the nitride layer and the conductive material layer are selectively etched to form a gate electrode layer 3 and a cap insulating layer 4.

Then, a nitride film layer is formed on the cap insulating layer 4 and the gate electrode layer 3 and etched back to form gate sidewalls 5 on the side surfaces of the cap insulating layer 4 and the gate electrode layer 3. do.

Next, an interlayer insulating layer 6 for planarization using BPSG or USG is formed on the entire surface of the semiconductor substrate 1 including the gate sidewall 5, the gate electrode layer 3, and the cap insulating layer 4. .

Then, a mask pattern layer 7 using photoresist or the like is formed on the interlayer insulating layer 6, and as shown in FIG. 1B, the contact hole 8 is formed by using the SAC process.

In the contact hole forming process using the SAC of the semiconductor device of the prior art, the nitride layer is used as an etch stop layer on the upper and side surfaces of the conductive material layer used as the metal wiring. At this time, the thickness of the nitride film used as the cap layer is thickened to prevent the short circuit between the wirings to increase the etching selectivity.

As such, an increase in the thickness of the nitride layer used as the cap layer of the conductive material layer used as the metal wiring leads to an increase in the processing time, and an increase in the thickness of the nitride film in the corner portion of the wiring in the SAC process is limited due to the reduction of the design rule. Process margin is small.

In addition, the etch selectivity of the oxidizing material layer and the nitride film layer used as the interlayer insulating layer must be 20: 1 or more, and it is disadvantageous in terms of economic process due to the difficulty of equipment selection.

The present invention is to solve the problem of the contact hole forming process using the SAC of the prior art semiconductor device, by increasing the process margin by increasing the contact hole formation method using the SAC process of the semiconductor device It is an object of the present invention to provide a method for forming a contact hole.

1A and 1B are process cross-sectional views illustrating a prior art self-aligned contact technique.

2A-2D are process cross-sectional views illustrating a self aligned contact technique in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

20. Semiconductor substrate 21. Device isolation layer

22. Gate electrode 23. Cap insulation layer

24. Gate sidewall 25. Interlayer insulation layer

26. First nitride film layer 27. Photoresist layer

28. Contact hole 29. Second nitride layer

29a. Nitrided sidewalls

The contact hole formation method of the semiconductor device of the present invention, which has a large process margin and high device reliability by using a different method of forming a contact hole using a self aligned contact (SAC) process, has a semiconductor substrate having an active region defined by an element isolation layer. Forming a cell transistor including a gate electrode, a cap insulating layer surrounding the gate electrode, and a gate sidewall on the substrate; forming an interlayer insulating layer using an oxidizing material on an entire surface of the semiconductor substrate on which the cell transistors are formed; Forming a first nitride film layer and a photoresist layer on the insulating layer and selectively patterning the photoresist layer; and using the patterned photoresist layer as a mask, the first nitride film layer and the interlayer insulating layer are formed by a dry etching process. Selectively etching to form a primary contact hole in the lower portion of the interlayer insulating layer having a predetermined thickness; Forming a second nitride layer on the entire surface including the contact hole and etching back to form a nitride sidewall on an inner side surface of the primary contact hole, and using the first nitride layer and the nitride sidewall as a mask And forming a secondary contact hole through which the interlayer insulating layer exposed by the process is completely removed by wet etching to expose one side of the impurity diffusion region of the cell transistors.

Hereinafter, the contact hole forming process of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

2A-2D are process cross-sectional views illustrating a self-aligned contact technique according to the present invention.

Contact hole forming process using the SAC process of the present invention, first, as shown in Figure 2a,

A gate electrode 22 and a cap insulation layer 23 are formed by depositing and selectively patterning a conductive material layer and an insulating material layer on the semiconductor substrate 20 having an active region defined by the device isolation layer 21. . In this case, the insulating material layer is deposited to a thickness of more than 300Å.

Polysilicon is used as the conductive material for forming the gate electrode 22 and a nitride film is used as the cap insulating layer 23.

Subsequently, a nitride layer is further deposited and etched back on the entire surface of the semiconductor substrate 20 including the patterned gate electrode 22 and the cap insulating layer 23 to form the gate sidewall 24. At this time, although not shown in the figure, an impurity implantation process is performed before and after the gate sidewall 24 is formed to form impurity diffusion regions in both semiconductor substrates 20 of the gate electrode 22 to complete the cell transistors. In addition, the thickness of the insulating layer for forming the gate sidewall 24 may be deposited to a thickness such that the gap between the gate electrodes 22 is secured up to 0.05 μm, and the material layer may be replaced with anything other than an oxidizing material.

And an oxidizing material on the entire surface of the semiconductor substrate on which the cell transistors are formed, for example, USG (Undoped Silicate Glass), BPSG (Boron Phosphorus Silicate Glass), HLD (High temperature Low pressure Deposition) oxide, thermal oxide, TEOS (TetraEthylOrthoSilicate) The interlayer insulating layer 25 is formed to a thickness of about 500 kPa to about 20,000 kPa.

Next, a contact hole for forming a first nitride layer 26 on the interlayer insulating layer 25, a photoresist layer 27 on the first nitride layer 26, and forming a storage node of a capacitor The photoresist layer 27 is selectively patterned to form a film.

As shown in FIG. 2B, the first hole layer 26 and the interlayer insulating layer 25 are selectively etched by dry etching using the patterned photoresist layer 27 as a mask to form the contact hole 28. Form. In this case, the interlayer insulating layer 25 is not etched completely but is etched to have a thickness thicker than the upper height of the cell transistors. In other words, the interlayer insulating layer 25 is left at a predetermined height below the contact hole, not the complete contact hole.

Subsequently, a second nitride layer 29 is formed on the entire surface including the contact hole 28.

As shown in FIG. 2C, the second nitride layer 29 is etched back to form a nitride sidewall 29a on an inner side surface of the contact hole 28.

Subsequently, as shown in FIG. 2D, the interlayer insulating layer (remained at the time of forming the contact hole 28) 25 exposed by the SAC process using the first nitride layer 26 and the nitride sidewall 29a as a mask is HF. It is completely removed by wet etching using a light and the like to form a contact hole in which one impurity diffusion region of the cell transistors is exposed.

The chemical used in the wet etching process can be used as long as it can selectively etch the oxidizing material layer.

The contact hole forming process of the semiconductor device of the present invention is a hole forming process for removing a part of the interlayer insulating layer 25 primarily and using the nitride sidewall 29a and the gate sidewall 24 formed on the side of the hole. The contact hole is formed by the SAC process using wet etching.

The contact hole forming process of the semiconductor device of the present invention does not require a high selectivity between the insulating layer and the interlayer insulating layer surrounding the gate electrode when forming the contact hole using the SAC process, thereby increasing the process margin.

In addition, after forming the contact hole forming process of first etching the interlayer insulating layer and forming sidewalls on the side thereof, exposing the impurity diffusion region, there is an effect of increasing the alignment margin during the photolithography process.

In addition, there is no fear of loss of the cap insulation layer and the gate sidewall surrounding the gate electrode by forming the final contact hole by using a wet etching having a high selectivity.

Claims (7)

Forming a cell transistor including a gate electrode, a cap insulating layer surrounding the gate electrode, and a gate sidewall on the semiconductor substrate having an active region defined by the device isolation layer, and an oxidizing material on the entire surface of the semiconductor substrate on which the cell transistors are formed. Forming an interlayer insulating layer, forming a first nitride film layer and a photoresist layer on the interlayer insulating layer, and selectively patterning the photoresist layer, and drying the patterned photoresist layer as a mask. Selectively etching the first nitride film layer and the interlayer insulating layer by an etching process to form a first contact hole in which the interlayer insulating layer remains at a predetermined thickness, and a second nitride film layer on the entire surface including the contact hole Forming and etching back to form a nitride sidewall on an inner side surface of the primary contact hole; And forming a secondary contact hole through which the impurity diffusion region on one side of the cell transistors is exposed by completely removing the interlayer insulating layer exposed by the SAC process by using the oxide layer and the nitride sidewall as a mask by wet etching. Method for forming contact holes in semiconductor device. The method of claim 1, wherein the cap insulating layer is deposited to a thickness of 300 GPa or more using a nitride film. The method of claim 1, wherein the gate electrode is formed of polysilicon. The method of claim 1, wherein in the first contact hole forming process, the interlayer insulating layer is etched to remain thicker than the upper height of the cell transistors. The method of claim 1, wherein the wet etching process for forming the secondary contact hole is performed using HF. The method of claim 1, wherein the thickness of the insulating layer for forming the gate sidewall is deposited to a thickness such that a gap between the gate electrodes is secured to 0.05 μm. The method for forming a contact hole in a semiconductor device according to claim 1, wherein the interlayer insulating layer is formed to a thickness of about 500 kPa to about 20,000 kPa using a material such as USG, BPSG, HLD oxide film, thermal oxide film, or TEOS.