KR19990009680A - Diagnosis / Control System Using I2C Bus with Multi-layered Accessibility for Multiple Master Devices - Google Patents

Abstract

The present invention relates to a diagnosis / control system using a multi-layered I2C bus that can access a plurality of master devices, comprising: a plurality of I2C bus master devices connected to a plurality of main I2C buses; An I2C bus multiplexer module that allows the separation of secondary I2C buses and connects as many I2C bus slave devices as needed on this secondary I2C bus, and one secondary I2C at any one time by each of the plurality of I2C bus master devices. A diagnostic / control system using a multi-layered I2C bus comprising an I2C bus slave device to which one I2C bus slave device on a bus is accessed,

The I2C bus multiplexer module includes: a remote 8-bit I / O expander for an I2C bus coupled to the main I2C bus to convert serial data of the I2C bus into parallel data; A register for determining an I2C bus slave address of this remote 8-bit I / O expander; A resistor for delivering a high current to the main I2C bus; An octal transparent D-type latch that receives eight output pins of the remote 8-bit I / O expander for the I2C bus as inputs and uses the SDA signal of the main I2C bus as a latch enable signal; A pull-down register that always enables the output of the type latch; The SCL and SDA signals of the main I2C bus are used by using 3 bits of the output of the octal transparent D-type latch as a selection input signal and 1 bit of the output of the octal transparent D-type latch as the output enable signal. An 8-bit multiplexer quick switch that multiplexes to eight main I2C buses each; An inverter for driving an output enable signal of the 8-bit multiplexer quick switch by inverting one output signal of the output signal of the remote 8-bit I / O expander to distinguish between an upper group and a lower group of the secondary I2C bus; Each consists of a resistive network for pullups that delivers high current to 16 secondary I2C buses.

Description

Diagnosis / Control System Using I2C Bus with Multi-layered Accessibility for Multiple Master Devices

The present invention relates to a diagnostic / control system using a multi-layer I2C bus accessible to a plurality of master devices, and in particular, multiple master devices present on one primary I2C bus may have slave devices on multiple secondary I2C buses with the same qualification. The present invention relates to a diagnostic / control system using a multi-layered I2C bus that is accessible to a number of master devices that can achieve stability and diversify system diagnostics and control.

1 is a block diagram showing the configuration of a conventional multi-layer I2C bus control apparatus.

As shown, a plurality of I2C bus master devices (MD0 through MDN) connected to a primary I2C bus, an I2C bus multiplexer connected to the primary I2C bus and connected to a plurality of secondary I2C buses (SB0 to SBN) and the plurality of secondary I2Cs. And a plurality of I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN) respectively connected to the buses SB0 to SBN.

The conventional multi-layer I2C bus controller is configured to replace the main I2C bus to overcome the limitation of the number of I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN) that can be connected to the I2C bus. I2C bus multiplexer is used to separate into multiple secondary I2C buses (S0 to SN), and as many I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, ... as required on multiple secondary I2C buses (SB0 to SBN). , SDN0 to SDNN).

Wherein the I2C bus multiplexer is controlled by a master (defined as I2C bus master device 0; master 0) responsible for accessing the I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN). At any moment, only one secondary I2C bus of the secondary I2C buses SB0 to SBN is connected to the primary I2C bus.

Accordingly, the master 0 wants the I2C bus multiplexer to access the I2C bus multiplexer before accessing the I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN that lie on the secondary I2C buses SB0 to SBN. After setting the buses SB0 to SBN, the corresponding I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN may be accessed.

In FIG. 1, the main I2C bus is composed of an SCL signal and an SDA signal.

2 is a detailed circuit diagram of an I2C bus multiplexer of a conventional multilayer I2C bus control apparatus.

As shown, an 8-bit remote I / O expander U1 for an I2C bus is controlled (read / write) by the master 0 as an I2C bus slave device connected to the main I2C bus.

Signal lines I2C15_XXX to I2C0_XXX of the secondary I2C buses SB0 to SBN operate as independent I2C buses, respectively.

In order for the master 0 to communicate with any I2C bus slave device (SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN) on any secondary I2C bus (SB0 to SBN), the first communication with U1 is performed. The output terminals P3 to P0 must be set to values that match the desired secondary I2C bus (SB0 to SBN) numbers.

For example, if the output terminals P3 to P0 of U1 are set to (P3, P2, P1, P0) = (1,1,0,0) to communicate with the secondary I2C buses SB0 to SBN No. 12, Select I2C bus multiplexers U2, U3, U4, U5, the input input terminals S2, S1, S0 become (S2, S1, S0) = (1, 0, 0), and the I2C bus multiplexers U2, U3 Each of the output terminals B4 of U4 and U5 is connected to each of the input terminals A of the devices U2, U3, U4 and U5.

In addition, since the I2C bus multiplexers U2, U3, U4, and U5 have low active output enable terminals, the output P3 of the U1 having a value of '1' is the value of the OE input terminal through the inverter U6. The output of the I2C bus multiplexer U2 U3 with '0' is enabled, and the output of the I2C bus multiplexers U4 and U5 is disabled because the OE input has a value of '1'.

As a result, the SCL signal of the main I2C bus is connected to I2C12_SCL and the SDA signal is connected to I2C12_SDA so that No. 12 of the main I2C bus and the secondary I2C buses SB0 to SBN are connected.

After the connection of the primary I2C bus and the secondary I2C buses SB0 to SBN is set as described above, the master 0 is an I2C bus slave device SD00 to SD0N on the 12th side of the secondary I2C buses SB0 to SBN. SD10 to SD1N, ..., SDN0 to SDNN).

The master 0 should properly set the 8-bit remote I / O expander U1 for the I2C bus to a desired number whenever there is a change in the secondary I2C buses SB0 to SBN.

Fig. 3 is a waveform diagram of changing a secondary I2C bus of a conventional multilayer I2C bus control apparatus.

FIG. 3 shows that other master devices located on the primary I2C bus except the master 0 granted access to the secondary I2C buses SB0 to SBN cannot access the secondary I2C buses SB0 to SBN. I can see clearly.

In order for the I2C multiplexer circuit shown in FIG. 2 to operate normally, the master 0 must execute the 'start' and 'stop' commands on the I2C bus protocol as shown in FIG. 3 when setting the U1.

If the 'Repeat Start' command is issued without generating the 'Stop' command, the I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ..., SDN0 to the secondary I2C bus SB0 to SBN are generated. SDNN) results in a result as shown in FIG.

Accordingly, an I2C bus protocol violation occurs with respect to the I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN on the secondary I2C bus SB0 to SBN. SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN) do not respond.

That is, in FIG. 4, after the 'start' command of T1, the 'repeat start' command is generated at T2 without the process of transmitting 8 data bits and ACK, and thus, the I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ... , SDN0 to SDNN) become unresponsive to subsequent accesses.

Therefore, in the related art, after setting U1 of FIG. 2, a 'stop' command must be driven. In this case, a problem occurs when one or more master devices attempt to access the secondary I2C buses SB0 to SBN.

The I2C bus performs arbitration between the master devices at the beginning of every access cycle so that the master device, which is licensed for the I2C bus, can access the I2C bus.

Therefore, if master 0 sets the secondary I2C buses (SB0 to SBN) to 12 through I2C bus arbitration, it drives a 'stop' command (ends the I2C bus).

Then, when attempting the arbitration again to access the I2C bus slave device (SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN) on the secondary I2C bus (SB0 to SBN) No. 12, another master If a device attempted to write to the U1 to set the secondary I2C buses SB0 through SBN to five and the other master device eventually won the arbitration, the I2C bus multiplexer could be assigned to the secondary I2C bus SB0. To SBN) 5.

Therefore, even if the master device 0 subsequently acquires the I2C bus right again, the master device 0 is connected to the I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN on the secondary I2C bus SB0 to SBN No. 12. Access will be disabled.

In conclusion, in the conventional I2C bus structure, access to the I2C bus slave devices SD00 to SD0N, SD10 to SD1N, ..., SDN0 to SDNN on the secondary I2C buses SB0 to SBN by various master devices is prevented. It is not possible and only access by a single master device is allowed.

This makes it difficult to diversify agents that can perform system diagnostics and control to provide duplicate paths (for example, local in-band and remote out-of-band). Constraints in system diagnostics and control functions.

Accordingly, the present invention provides a high value-added function to the system by diversifying the master device for performing system diagnosis and control in a system using the I2C bus for the purpose of system diagnosis and control in order to achieve the above object. It is an object of the present invention to provide a diagnosis / control system using a multi-layered I2C bus that is accessible to multiple master devices to enable multiple master devices to access multiple secondary I2C buses to provide stability.

1 is a block diagram showing a conventional multi-layer I2C bus control device.

FIG. 2 is a detailed circuit diagram of the portion of the I2C bus multiplexer of FIG. 1; FIG.

FIG. 3 is a waveform diagram at the time of changing the secondary I2C bus of FIG. 1; FIG.

4 is a waveform diagram of driving a repeat start command T2 without a start command in FIG.

5 is an embodiment of a diagnosis / control system using a diagnosis / control system using a multi-layered I2C bus capable of accessing a plurality of master devices according to the present invention.

FIG. 6 is a detailed circuit diagram of the portion of the I2C bus multiplexer of FIG. 5; FIG.

FIG. 7 is a waveform diagram at the time of changing the secondary I2C bus of FIG. 5; FIG.

Explanation of symbols on the main parts of the drawings

U1: 8-bit remote I / O expander for I2C bus

U2 to U5: 8-bit multiplexer quick switch

U6: Inverter

U7: Octal Transparent D-Type Latch

R1 to R3: pullup registers

R4: pull down register

RN1 to RN4: resistive network for pullup

In order to achieve the above object, the present invention provides a plurality of I2C bus master devices each connected to a plurality of primary I2C buses, separating the plurality of primary I2C buses into a plurality of secondary I2C buses, and as needed on this secondary I2C bus. An I2C bus multiplexer module that enables the connection of an I2C bus slave device of the I2C bus and an I2C bus on which one I2C bus slave device on one secondary I2C bus is accessed at any one time by each of the plurality of I2C bus master devices. A diagnostic / control system using a multi-layered I2C bus accessible to a plurality of master devices including a slave device,

The I2C bus multiplexer module includes: a remote 8-bit I / O expander (U1) for an I2C bus coupled to the main I2C bus to convert serial data of the I2C bus into parallel data; A register R1 for determining an I2C bus slave address of the remote 8-bit I / O expander U1; Resistors R2 and R3 for sourcing high current to the main I2C bus; An octal transparent D-type latch (U7) which receives eight output pins of the remote 8-bit I / O expander (U1) for the I2C bus as inputs and uses the SDA signal of the main I2C bus as a latch enable signal; A pull-down resistor R4 which always enables the output of this octal transparent D-type latch U7; 3 bits (B2 to B0) of the output of the octal transparent D-type latch U7 are used as the selection input signal, and one bit (B3) of the output of the octal transparent D-type latch U7 is enabled. An 8-bit multiplexer quick switch (U2 to U5) for multiplexing the SCL and SDA signals of the main I2C bus into eight main I2C buses, respectively, as signals; Inverting one output signal P3 of the output signals of the remote 8-bit I / O expander U1 for the I2C bus to distinguish between the upper group I2C15_XXX I2C8_XXX and the lower group I2C7_XXX I2C0_XXX of the secondary I2C bus. An inverter U6 for driving output enable signals of the 8-bit multiplexer quick switches U2 and U3; It comprises a pull-up resistive network (RN1 through RN4) that delivers a high current to each of 16 secondary I2C buses.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6 is a detailed circuit diagram of an I2C bus multiplexer portion of a system diagnosis / control apparatus using a multi-layered I2C bus capable of accessing a plurality of master devices according to the present invention.

As shown, an 8-bit latch, Octal Transparent D-Type Latch (U7), is added between the 8-bit remote I / O expander (U1) for the I2C bus and the I2C bus multiplexers (U2 to U5). The latch enable pin (LE) of the type latch (U7) is connected to the SDA signal line of the main I2C bus.

Here, the 8-bit remote I / O expander U1 for the I2C bus is an I2C bus slave device connected to the main I2C bus and is under the control (read / write) of any I2C bus master device on the main I2C bus.

The secondary I2C buses I2C15_XXX to I2C0_XXX operate as independent I2C buses. In order for any I2C bus master device on the primary I2C bus to communicate with any I2C bus slave device on any of the primary I2C buses, it first communicates with an 8-bit remote I / O expander (U1) for the I2C bus to provide this I2C. The output terminals P3 to P0 of the 8-bit remote I / O expander U1 for the bus should be set to a value corresponding to the number of the desired secondary I2C bus I2C15_XXX I2C0_XXX.

For example, an output terminal of the 8-bit remote I / O expander U1 for the I2C bus (P3, P2, P1, P0) for communicating with the secondary I2C bus of the secondary I2C buses (I2C15_XXX to I2C0_XXX). = (1,1,0,0)

The outputs P3 to P0 of the 8-bit remote I / O expander U1 for the I2C bus are expandable to P7 to P0 and octal transparent D-type latches U7 under the control of the SDA signal of the main I2C bus. Is latched by.

Since the output enable of the octal transparent D-type latch U7 is always low by the pull-down resistor R4, the latched data is driven by the output ports B3 to B0, which are directly expandable to B7 to B0. The output ports B2 to B0 of the octal transparent D-type latch U7 have a selection input terminal S2, S1, S0 of the 8-bit multiplexer quick switch (U2, U3, U4, U5) (1, 0, 0), the output terminal B4 of each device is connected to each input terminal A. FIG.

Since the 8-bit multiplexer quick switch U2, U3, U4, U5 has a low active output enable terminal, the output P3 of the octal transparent D-type latch U7 having the value '1' is an inverter ( Through U6), the output of the 8-bit multiplexer quick switch U2, U3 whose OE (output enable) input terminal has the value '0' is enabled.

In the 8-bit multiplexer quick switches U4 and U5, the output is disabled because the OE (output enable) input terminal has a value of '1'.

A detailed waveform diagram relating to the octal transparent D-type latch U7 is shown in FIG. 7.

As shown, the output terminals P3 to P0 of the 8-bit remote I / O expander U1 for the I2C bus change at the time of T1 after the rising edge of the SCL at the time of ACK driving after the last bit of write data. do.

However, since the SDA signal is 'low', the output of the octal transparent D-type latch U7 does not change.

When the SDA signal becomes 'high' at the 'T2' time point, the LE input of the octal transparent D-type latch U7 is activated, so that the output value of the octal transparent D-type latch U7 is changed from 'T1'. The output value of the 8-bit remote I / O expander U1 for the I2C bus is the same.

In FIG. 7, after the 'T2', the I2C12_SCL signal falls low for a while, but does not affect the I2C bus slave device on the secondary I2C bus 12 in the I2C bus protocol.

After 'T2', the SCL signal of the main I2C bus is connected to the I2C12_SCL signal, and the SDA signal is connected to the I2C12_SDA signal, thereby eventually connecting the main I2C bus and the secondary I2C bus 12.

After the connection of the I2C bus is set in this way, the master device may communicate with the I2C bus slave device on the secondary I2C bus 12.

As shown in FIG. 7, the master device sets the 8-bit remote I / O expander U1 for the I2C bus and then releases the bus. The I2C bus slave device can be accessed.

In this way, by preventing the interference of other master devices between the I2C bus multiplexer setting and the I2C bus slave device access operation on secondary I2C bus No. 12, the conventional I2C bus access by the plurality of master devices in the conventional invention. The problem can be solved.

The bus states of the secondary I2C bus before and after the I2C bus multiplexer change are as follows.

In FIG. 7, since the cycle of the secondary I2C bus 5 before the change of the I2C bus multiplexer is stopped without a 'stop' command at 'T2', there is no problem in operating in the 'repeat start' state at the next access.

In addition, after changing the I2C bus multiplexer, bus No. 12 of the secondary I2C bus is driven as 'low' for a while after 'T2' as described above, but has no meaning in the I2C bus protocol. A phase I2C bus slave device will ignore it.

At 'T3' the 'Start Repeat' command is driven on the I2C bus and the corresponding I2C bus slave device responds.

The master devices capable of accessing the secondary I2C bus should properly set the 8-bit remote I / O expander U1 for the I2C bus to the desired number whenever the secondary I2C bus access is required.

It must be considered here that each master device releases the I2C bus between the access for setting the 8-bit remote I2C I / O expander (U1) for the I2C bus of FIG. 5 and the I2C bus slave device access on the secondary I2C bus. You should choose to rerun the 'Start Repeat' command without the word 'Stop'.

5 is an example of a control and diagnostic system constructed utilizing the present invention.

As shown, the 'uSMC' is a master device connected to the local console and responsible for in-band system diagnostics and control, while the 'add-in card for remote system diagnostics and control' is connected to the remote console via a modem or LAN. Agent to enable out-of-band system diagnostics and control.

Here, the 'uSMC' and the add-in card can access the slave device on the secondary I2C bus with the same qualification.

The in-band system diagnosis and control is impossible to operate the system when the main processor (host) is not operating because the main processor (host) of the system is the subject of diagnosis and control.

In addition, out-of-band system diagnosis and control is a method of diagnosing and controlling the system regardless of the main processor of the system through a method such as a modem or a LAN at a remote console.

As described above, according to the present invention, in the diagnosis and control system using the I2C bus, a plurality of master devices have the same qualification by appropriately operating an I2C multiplexer and a circuit for controlling the I2C multiplexer which branches one main I2C bus into up to 256 secondary I2C buses. As a result, it is possible to connect to multiple secondary I2C buses, and as a result, by diversifying the master device performing system diagnosis and control, it is possible to add high-value functions to the system and to provide convenience and stability of use.

Claims (5)

Multiple I2C bus master devices, each connected to one primary I2C bus, and an I2C bus that allows the primary I2C bus to be separated into multiple secondary I2C buses and connect as many I2C bus slave devices as needed on this secondary I2C bus. A plurality of master devices accessible multilayers comprising a multiplexer module and an I2C bus slave device to which one I2C bus slave device on one secondary I2C bus is accessed at any one time by each of the plurality of I2C bus master devices. In the diagnosis / control system using the I2C bus of the structure, The I2C bus multiplexer module includes: a remote 8-bit I / O expander (U1) for an I2C bus coupled to the main I2C bus to convert serial data of the I2C bus into parallel data; A register (R1) for determining an I2C bus slave address of said remote 8-bit I / O expander (U1); Resistors (R2 and R3) for delivering a high current to the main I2C bus; An octal transparent D-type latch (U7) which receives eight output pins of the remote 8-bit I / O expander (U1) for the I2C bus as inputs and uses the SDA signal of the main I2C bus as a latch enable signal; A pull down resistor (R4) that always enables the output of the octal transparent D-type latch (U7); 3 bits (B2 to B0) of the output of the octal transparent D-type latch U7 are used as the selection input signal, and one bit (B3) of the output of the octal transparent D-type latch U7 is enabled. An 8-bit multiplexer quick switch (U2 to U5) for multiplexing the SCL and SDA signals of the main I2C bus into eight main I2C buses, respectively, as signals; Inverting one output signal P3 among the output signals of the remote 8-bit I / O expander U1 for the I2C bus to distinguish between the upper group I2C15_XXX to I2C8_XXX and the lower group I2C7_XXX to I2C0_XXX of the secondary I2C bus. An inverter U6 for driving output enable signals of the 8-bit multiplexer quick switches U2 and U3; It characterized in that it comprises a pull-up resistive network (RN1 to RN4) for delivering a high current to each of 16 secondary I2C bus, Diagnostic / control system using multi-layer I2C bus with multiple master device access. The method of claim 1, wherein the octal transparent D-type latch U7 is A part or all of an output terminal signal of the remote 8-bit I / O expander U1 for the I2C bus is input, and an SDA signal on the main I2C bus or a signal using the same is used as a latch enable signal. A circuit which is always enabled by a pull down register R4, characterized in that the output of the remote 8-bit I / O expander U1 for the I2C bus is driven at an appropriate time point, Diagnostic / control system using multi-layer I2C bus with multiple master device access. The method of claim 2, wherein the octal transparent D-type latch U7 It is located between the remote 8-bit I / O expander (U1) for the I2C bus and the 8-bit multiplexer quick switch (U2 to U5), characterized in that the latch enable signal is connected to the SDA signal of the main I2C bus , Diagnostic / control system using multi-layer I2C bus with multiple master device access. The method of claim 1, wherein the 8-bit multiplexer quick switch (U2 to U5), Partial signals of the output port driven by the octal transparent D-type latch U7 are used as a selection input signal, and outputs are controlled according to output input terminal values as signals generated by the inverter U6. doing, Diagnostic / control system using multi-layer I2C bus with multiple master device access. Multiple I2C bus master devices connected to one primary I2C bus, an I2C bus multiplexer that separates the primary I2C bus into multiple secondary I2C buses and allows as many I2C bus slave devices as needed on this secondary I2C bus. A module and an I2C bus slave device to which one I2C bus slave device on one secondary I2C bus is accessed at any one time by each of the plurality of I2C bus master devices, The I2C bus multiplexer module includes: a remote 8-bit I / O expander (U1) for an I2C bus coupled to the main I2C bus to convert serial data of the I2C bus into parallel data; A register (R1) for determining an I2C bus slave address of said remote 8-bit I / O expander (U1); Resistors (R2 and R3) for delivering a high current to the main I2C bus; An octal transparent D-type latch (U7) using the SDA signal of the main I2C bus as a latch enable signal; A pull down resistor (R4) that always enables the output of the octal transparent D-type latch (U7); 8-bit multiplexer quick switches (U2 to U5) for multiplexing the SCL and SDA signals of the main I2C bus to eight main I2C buses, respectively; An inverter (U6) for inverting one output signal (P3) of the output signal of the remote 8-bit I / O expander (U1) for the I2C bus to drive the output enable signal of the 8-bit multiplexer quick switch (U2, U3). Wow; A diagnostic / control system using a multi-layered I2C bus accessible to multiple master devices, including a resistive network (RN1 to RN4) for pull-up, each delivering high current to 16 secondary I2C buses, Each of the plurality of I2C bus master devices, Without an I2C bus stop command between access of the remote 8-bit I / O expander U1 to control the 8-bit multiplexer quick switches U2 through U5 and access of a plurality of I2C bus slave devices on the plurality of secondary I2C buses. By using only I2C bus repeat start instructions to prevent interference of multiple I2C bus master devices between the 8-bit multiplexer quick switch (U2 through U5) settings and access of multiple I2C bus slave devices on the multiple secondary I2C buses. Characterized in that, Diagnostic / control system using multi-layer I2C bus with multiple master device access.