JPH0290256A - Memory bus switching system - Google Patents

Abstract

PURPOSE:To remove complexity and dangerousness to be generated by a mechanical system or the like by automatically deciding the specification of a connected memory board, collectively switching an interface and selectively setting up a control signal. CONSTITUTION:The memory board 12 having an exclusive interface is provided with a flip flop 21 for holding an one-bit status signal at an 'L' level on a memory bus from a point of time immediately after resetting up to the start of access and a selector circuit 18 for selecting either one of a reference memory bus control circuit 15 and an exclusive memory bus control circuit 16 on a CPU board 11. The interface attribute of the connected memory board is decided by a CPU and a control signal for the interface is automatically switched to select and set up the control signal. Consequently, complexity and dangerousness like a mechanical setting case can be removed.

Description

[Detailed Description of the Invention] A. Industrial Field of Application The present invention is a control system or the like in which a central processing unit (hereinafter referred to as a CPU) and a memory are each integrated into a board.
The present invention relates to a switching method for switching input and output of a CPU in accordance with the memory bus method when there are two types of memory buses that directly connect them, a standard type and a dedicated type.

B1 Summary of the Invention The present invention provides a CPU that is compatible with a standard or dedicated system of a memory bus that directly connects a CPU such as a control system and a memory.
In the memory bus switching method for switching input and output of U, on a memory board with a dedicated method interface, there is a flip-flop that holds a 1-bit status signal on the memory bus at L'' level from reset to start of access, and its Equipped with a selector circuit that selects one of two control circuits on the CPU board based on a status signal, the CPU determines the interface attributes of the connected memory board and automatically switches the interface control signal. Automatically determines the specifications of the connected memory board,
It is possible to switch interfaces all at once and set control signals selectively, and provides a technology that eliminates the trouble and danger that computer users face each time they build a system in the case of mechanical settings. It is something.

C3 Conventional technology Control microcomputers used in control systems and equipment are usually created using printed wiring boards, and these are connected to groups of boards with predetermined shapes and dimensions using signal wire bundles called buses. It is often created by concatenating.

FIG. 5 is a diagram showing the hardware configuration of a general control microcomputer. In the figure, 1 is a CPU, 2 is a memory, 31 is 1f10 (input/output unit), and 4 is a system bus for control. In this hardware, CPU1
．． Memory 2. The l103 is designed to transfer signals only with the system bus 4, but in recent years, as shown in FIG. The number is increasing. this is,
The purpose of the system bus 4 is to connect various types of memories and Ilo within the same system, and since it can only operate at low speed, the memory bus 5 is intended to realize high-speed memory access.

The system bus and memory bus in such control systems are currently being standardized by several international standards such as IEC and IEEE, and many manufacturers provide products with the same standards. Each board product is compatible and can be used in any combination.

However, the standardized memory bus is contrary to the aim of increasing speed, and is extremely slow in terms of CPU operation, to the extent that it cannot fully utilize the capabilities of the microprocessor on the CPU board. In order to maximize the capabilities of a microprocessor and achieve faster memory access, it is necessary to install dedicated signal lines that conform to the microprocessor's control method, but it is necessary to install dedicated signal lines on the memory bus. If such a board is provided, the standardity of the bus will be lost, and compatibility will be lost if other boards are manufactured by other manufacturers.

Therefore, as a compromise, some conventional CPU boards
By making it possible to switch some of the signal groups defined in the standard memory bus using setting pins, and by inserting and removing the setting pins for each applicable system, it can be used as a memory bus with the desired specifications. There are some.

FIG. 7 is a configuration diagram of such a conventional example, showing the connection part between the CPU board and the memory bus, and 71 in the figure indicates the CPU board,
72 is a memory board, and 73 is a memory bus. CPU
The board 71 includes a microprocessor 74 . Standard memory bus control circuit 75° Dedicated memory bus control circuit 76, control register 77, and setting pin group 78 for memory bus switching are installed.
are setting pins ■, ■, ■, which connect the standard memory bus control circuit 75 and the output signal line group, and setting pins ■, ■, ■, which connect the dedicated memory bus control circuit 76 and the output signal line group.
If the memory board has a standard memory bus interface, set the setting pins ■, ■, ■..., and the memory board has a dedicated memory bus interface. If it has a face, set the setting pins ■, ■, ■, etc.

D1 Problems to be Solved by the Invention As mentioned above, there are two types of memory buses provided in control microcomputers to speed up memory access: standard buses and dedicated buses, and it is possible to control both of them. When equipped with a CPU, it is necessary to set which memory bus interface to select.However, as in the conventional example, mechanical methods such as inserting and removing setting pins may require dozens of steps in some cases. Therefore, it takes time to configure the settings, and the user must constantly keep track of these settings.
It may also cause the control system to malfunction.

The present invention was created in view of these problems, and
Automatically determines the specifications of the connected memory board,
Memory bus switching allows interfaces to be switched all at once and control signals to be selectively set, eliminating the hassle and danger that computer users face each time they build a system when using mechanical settings. The purpose is to provide a method.

81 Means for Solving the Problems Means for solving the above problems in the present invention are CP
In the memory bus switching method of a control system that is equipped with two control circuits corresponding to two types of interfaces, standard method and dedicated method, of the memory bus arranged between U and memory, A flip-flop keeps the 1-bit status signal on the memory bus at L'' level from immediately after reset until the start of access, and the status signal causes the C
Equipped with a selector circuit that selects one of two control circuits on the PU board, the CPU determines the interface attributes of the connected memory board, and uses a memory bus switching method that automatically switches the interface control signal. shall be.

When the F1-operating CPU and memory are each integrated into a board, and there are two types of memory buses that access them at high speed: a standardized standard method and a high-speed dedicated method, each method is different. It is natural that a memory board having an interface corresponding to each system is connected to each memory bus, but the CPU board also requires an input/output control circuit corresponding to each system.

The present invention attempts to create compatibility by automatically switching between two types of control circuits by a CPU, and uses one bit of a signal line on a memory bus as a status signal.

To generate a status signal on the memory bus,
A flip-flop is provided on a memory board that has an interface for a dedicated memory bus, and one bit on the memory bus is held at the "L" level from immediately after reset until the start of access.

On the other hand, a selector circuit is provided on the CPU board, and by selecting one of the two control circuits based on the read status signal, the CPU determines the interface attributes of the connected memory board and performs interface control. Automatically switches the signal to correspond to the type of memory bus.

Theoretically, the status signal may correspond to either the "L" level or the H level for a dedicated method, but if the "L" level is used as the status signal when there is no signal on the standard method memory bus, it will be difficult to identify the status signal. Therefore, it is better to use the 'L' level as the status signal when there is no signal on the dedicated memory bus.

For the same reason, the signal line that generates the status signal is inappropriate if the low level input to the signal line causes malfunction.The timing of generating and reading the status signal is determined by the output buffer and Limited by input buffer.

G. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, showing a state in which a memory board having an interface compatible with a dedicated memory bus and a CPU board according to the present invention are combined. In the figure, 11 is a CPLJ board, 12 is a memory board, 13 is a memory bus, and the CPU board 11 is
Microprocessor 14 and standard memory bus control circuit 1
5, a dedicated memory bus control circuit 16, a control register 17, a selector circuit 18 for selecting either the signal of the control circuit 15 or 16, an input cover, and a filter 19.
It is equipped with. The memory board 12 has an interface compatible with a dedicated memory bus 13, and is equipped with an output sofa 20 and a flip-flop 21. In the embodiment shown in FIG. 1, the input buffer 19 and output buffer 20 are included in the address signal group, but any signal line may be used as long as it has the interface conditions as shown in FIG. .

However, it is inappropriate if the "L" level input of the signal line causes malfunction.

Now, under the interface conditions shown in FIG. 2, if the OE double signal of the output buffer 20 is at the "negate" (invalid) level immediately after being reset to the initial state, the output of the output buffer 20 is in the oven state. (high impedance), and this line is set to the "H" level by the pull-up resistor Rp before the input buffer 19. Therefore, the flip-flop 21 outputs the "assert" (invalidate) level of the output buffer 20 immediately after being reset, and is cleared when the control signal A to the memory board 12 is activated, thereby negating the output buffer 20. After the system is reset and before the memory control signal is output, the output buffer 20 is in an enabled state, its input is at the GND level, and the status signal is at the "L" level.

The microprocessor 14 on the CPU board 11 executes the manual control register 17 by commands to the control register 17.
9 to read the state of the status signal. In this case, the value is “■7” level, so
The memory board 12 connected to the memory bus 13 is
Recognized as having a dedicated memory bus interface.

FIG. 3 is a configuration diagram showing another state of the above embodiment, showing a state in which a memory board having an interface compatible with a standard memory bus and a CPU board according to the present invention are combined; A CPU board, 22 a memory board, and 23 a memory bus. The CPU board 11 is the same as that shown in FIG. 1, and each circuit mounted thereon with the same number is the same. On the other hand, the memory board 22 has an interface compatible with the standard memory bus 23, and no special circuit is added.

In this case, the microprocessor 1 on the CPU board 11
4 issues a command to the control register 17 and reads the state of the status signal from the input buffer 19. Since the value is at the "H" level, the memory board 22 is recognized as having a standard memory bus interface.

In this way, in the device implementing the present invention, the memory board connected to the memory bus is dedicated.

It is possible to automatically determine which standard memory bus interface the device has.

FIG. 4 is a flowchart showing an example of memory bus switching processing according to the present invention. As shown in the figure, after making the above judgment, the microprocessor 14 issues a command to the control register 17 according to the judgment, and the selector circuit I8 controls the selection signal to control the standard memory bus control circuit 15. Alternatively, by simply connecting the corresponding signal from the dedicated memory bus control circuit 16 to the memory bus, normal memory access can be performed from then on.

In this way, a control microcomputer has two types of memory buses, a standard bus and a dedicated bus, which are provided to speed up memory access, and when equipped with a CPU that can control both, which memory bus interface The setting to select the control signal is very troublesome for the person in charge, but in the present invention, the specifications of the connected memory board are automatically determined by simple program control after the system is reset, and the control signal is selected and set. This eliminates the hassle and high risk that computer users face each time they build a system when mechanical settings are used.

As explained in detail about the H6 invention, according to the present invention, it is possible to automatically determine the specifications of the connected memory boards, switch the interfaces all at once, and selectively set the control signals. It is possible to provide a memory bus switching method that eliminates the trouble and danger that computer users face each time they build a system in the case of mechanical settings.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a partial circuit diagram of the embodiment, Fig. 3 is a block diagram of the embodiment of the present invention in another state, and Fig. 4 is a block diagram of an embodiment of the present invention. A flowchart of the processing of the embodiment, FIGS. 5 and 6 are block diagrams of a general control microcomputer, and FIG. 7 is a block diagram of a conventional example. 11.71...CPU board, 12,22.72...
・Memory board, 13, 23.73...Memory bus,
14.74...Microprocessor, 15.75...
・Standard memory bus control circuit, 16.76... Dedicated memory bus control circuit, 17, 77... Control register, 18... Selector circuit, 19 Input buffer, 2
0... Output buffer, 78... Setting pin group for memory bus switching. Figure 1 Flow chart of processing of the embodiment Figure 4 Figure 5 Configuration diagram of a control system equipped with a memory bus Figure 6

Claims (1)

[Claims] (1) In the memory bus switching method of a control system that is equipped with two control circuits corresponding to two types of interfaces, a standard method and a dedicated method, of the memory bus arranged between the central processing unit and the memory, the dedicated method A flip-flop that holds a 1-bit status signal on the memory bus at "L" level from immediately after reset until the start of access on a memory board with an interface, and two control circuits on the central processing board based on the status signal. a selector circuit for selecting either one of the two, a central processing unit determines the interface attributes of the connected memory board, and automatically switches the interface control signal.