KR19990009178A - Digital Phase-Locked Loop and Phase Comparison and Charge Pumping Methods Without Dead Zones - Google Patents

Abstract

A dead zone free digital phase locked loop and phase comparison and charge pumping method is disclosed. The dead zone-free digital phase locked loop according to the present invention divides a signal having an oscillation frequency and a voltage controlled oscillator for outputting a signal having a frequency oscillated in response to a control voltage output from a low pass filter at a predetermined rate, In a dead zone-free digital phase-lock loop having a programmable divider for outputting a divided signal, a phase difference between the divided signal and the reference frequency signal is compared, and the result of the comparison is output as an up / down signal, A phase comparator which is reset in response, a charge pump generating a supply / sink drive signal in response to an up / down signal, and supplying / sinking a current corresponding to the phase difference to / from the low pass filter in response to the supply / sink drive signal, and Generates a reset signal that logically combines the supply drive signal and the sink drive signal and outputs the logical combined result as a reset signal. It is characterized by comprising a sex means.

Description

Digital Phase-Locked Loop and Phase Comparison and Charge Pumping Methods Without Dead Zones

FIELD OF THE INVENTION The present invention relates to digital phase locked loops, and more particularly, to digital phase locked loops with no dead zone and phase comparison and charge pumping methods that can eliminate dead zones using a reset signal generated from a charge pump. will be.

In general, a digital phase locked loop (Digital PLL) compares a frequency and a phase difference by a phase comparator (PC), generates an error signal corresponding to the difference, and corresponds to the generated error signal. Get frequency

FIG. 1 is a schematic block diagram illustrating a general digital PLL including a phase comparator 10, a charge pump 12, a low pass filter 14, and a voltage controlled oscillator (VCO). 16), programmable divider 18.

The phase comparator 10 shown in FIG. 1 compares a phase of an input reference frequency signal with an oscillation frequency signal of the divided VCO 16, outputs an up signal and a down signal corresponding to the phase difference, and includes a charge pump ( 12 supplies or reduces the charge to the low pass filter 14 in response to the up and down signals output from the phase comparator 10. The low pass filter 14 filters the signal output from the charge pump 12 and outputs the filtered DC voltage. The VCO 16 inputs the voltage output from the low pass filter 14 as a control voltage to control the voltage. Generate an oscillation frequency signal corresponding to. The oscillation frequency of this signal is N times the reference frequency signal, and the programmable divider 18 changes the oscillation frequency signal of the VCO 16 to 1 / N as a divider that can change the division ratio by modifying an internal program. The divided signals are output to the phase comparator 10. Here, the phase comparator 10 and the charge pump 12 determine the performance of the entire PLL.

2 is a graph showing an error voltage according to a phase error of the conventional phase comparator 10. When the phase difference is small, an output corresponding to the phase difference, that is, a portion where no error voltage is generated is the dead zone 20.

An important figure of merit in a phase-locked loop for a frequency synthesizer is jitter, in which phase noise and pulses transmitted through the transmission line cause phase shifts in the pulse position. The main cause of jitter in the phase comparator 10 and the charge pump 12 occurs when the two comparison frequencies are the same and the phase difference is small, as shown in FIG. This occurs because the charge pump 12 does not respond properly to the up signal UP and the down signal DOWN of the small pulse of the phase comparator 10.

3 is a circuit diagram illustrating a conventional phase comparator 10 for solving a dead zone that has the greatest influence on jitter, and includes a first NAND gate 310. First flip-flop 320, second flip-flop 330, second NAND gate 340, third NAND gate 350, delay unit 360, fourth NAND gate 370, fifth NAND gate It consists of 380.

The first NAND gate 310 and the second NAND gate 340 illustrated in FIG. 3 are input gates to which a reference frequency signal and a divided oscillation frequency signal are input. In addition, the delay unit 360 generally uses four series inverters, and provides a signal delay between the third NAND gate 350 as the reset gate and the fourth and fifth NAND gates 370 and 380 as the output gates. do. In this way, the reset signal is generated through the delay unit 360 to make the pulse width of the up signal UP and the down signal DOWN larger than the actual one, and thus the dead zone can be eliminated by allowing the charge pump to respond appropriately. have. The delay time should be appropriately determined so that the charge pump 12 operates correctly in the interval after the phase comparator 10 is reset to cause charge sourcing and charge sinking. However, such a conventional method is difficult to adjust the delay time, the characteristics of the phase comparator 10 may vary according to the delay time, and the unnecessary current during the delay of the up signal UP and the down signal DOWN is generated. There is a problem that is consumed.

An object of the present invention is to provide a digital phase locked loop without a dead zone capable of removing dead zones by receiving a reset signal from a charge pump.

Another object of the present invention is to provide a phase comparison and charge pumping method performed in the digital phase locked loop.

1 is a schematic block diagram for explaining a general digital phase locked loop.

FIG. 2 is a circuit diagram illustrating a phase comparator of the conventional digital phase locked loop shown in FIG.

FIG. 3 is a graph for explaining dead zones occurring in the phase comparator shown in FIG. 2.

4 is a schematic block diagram illustrating a digital phase locked loop without a dead zone according to the present invention.

5 is a circuit diagram of one preferred embodiment for explaining the phase comparator and charge pump of the digital phase locked loop shown in FIG.

FIG. 6 is a flowchart for explaining a phase comparison and a charge pumping method performed in the phase comparator and the charge pump shown in FIG. 5.

7A to 6E show simulation results of outputs for a short time when the oscillation frequency divided by the phase comparator shown in FIG. 5 is ahead of a reference frequency signal.

8A to 8E show results of a short time simulation of the output when the reference frequency is in phase with the divided oscillation frequency signal in the phase comparator shown in FIG. 4.

9A to 9E show results of a short time simulation of the output when the phase of the oscillation frequency signal divided by the reference frequency signal coincides with the phase comparator shown in FIG. 4.

FIG. 10 is a result of a long time simulation of the output of each part of the phase comparator and the charge pump shown in FIG. 5.

FIG. 11 is a result of simulating an error current according to a phase error of the phase comparator shown in FIG. 5.

In order to achieve the above object, the dead zone-free digital phase locked loop according to the present invention comprises a voltage controlled oscillator for outputting a signal having a frequency oscillated in response to a control voltage output from a low pass filter and a signal having an oscillation frequency. In a dead zone-free digital phase-lock loop having a programmable divider that divides at a predetermined rate and outputs a divided signal, the phase difference between the divided signal and the reference frequency signal is compared and the compared result is used as an up / down signal. A phase comparator that is reset in response to a reset signal, and generates a supply / sink drive signal in response to an up / down signal, and supplies a current equal to the phase difference to / from a low pass filter in response to the supply / sink drive signal. A charge pump to sink, and a logic combination of the supply drive signal and the sink drive signal, and the logic combined result to reset the signal. Up output is constituted by the reset signal generating means is preferable to.

In order to achieve the above object, a phase comparison and charge pumping method of a digital phase locked loop according to the present invention includes a voltage controlled oscillator and an oscillation frequency for outputting a signal having an oscillating frequency corresponding to a control voltage output from a low pass filter. A phase comparison and charge pumping method performed in a digital phase locked loop having a divider for dividing a signal having a predetermined ratio and outputting the same, the method comprising: (a) comparing a phase of a reference frequency signal with a phase of a divided signal; b) generating an up / down signal corresponding to the compared result, supplying / sinking a current corresponding to the compared phase difference in response to the up / down signal to / from the low pass filter; And initiating phase comparison after supplying / sinking a current.

Hereinafter, a digital phase locked loop according to the present invention will be described with reference to the accompanying drawings.

4 is a schematic block diagram illustrating a digital phase locked loop according to the present invention, which includes a phase comparator 400, a charge pump 402, a low pass filter 404, a reset signal generator 406, and a VC0 ( 412, a programmable divider 410.

The phase comparator 400 illustrated in FIG. 4 compares the phase of the input reference frequency signal f _R with the oscillation frequency signal f _V of the divided VCO 412, and the up signal UP corresponding to the phase difference. ) And a down signal DOWN, and the charge pump 402 outputs a phase difference current to the low pass filter 404 in response to the up signal UP and the down signal DOWN output from the phase comparator 400. Supply or sink current from the low pass filter 404. The reset signal generator 406 resets the phase comparator 400 by generating a reset signal RS after the charge pump 402 operates. The low pass filter 404 removes the high frequency components of the signal output from the charge pump 402 and outputs the filtered DC voltage, and the VCO 412 inputs the voltage output from the low pass filter 404 as a control voltage. To generate an oscillation frequency signal f _V corresponding to the control voltage. The oscillation frequency of this signal is N times the reference frequency signal f _R , and the programmable divider 410 divides the oscillation frequency signal of the VCO 404 at 1 / N, and divides the divided signal into the phase comparator 400. Will output

FIG. 5 is a circuit diagram of a preferred embodiment for explaining the phase comparator 400 and the charge pump 402 of the digital PLL shown in FIG. 4, wherein the phase comparator 400 includes a first NAND gate 510 and a first flip. A flop 520, a second flip flop 530, a third NAND gate 540, a fourth NAND gate 550, a fifth NAND gate 560, and a sixth NAND gate 570. In addition, the charge pump 402 includes a current sourcing 591 and a current sink 595, and the current supply 591 includes an inverter 594, an nMOS transistor M1, and a first source. 1 resistor R1, pMOS transistors M3 and M5, and the current sink 595 includes a pMOS transistor M7, a second resistor R2, nMOS transistors M9, M11, and M13. It consists of three resistors (R3).

The first NAND gate 510 shown in FIG. 5 inverts ANDs the reference frequency signal f _R and the up signal UP of the previous state of the phase comparator 400 and consists of NAND gates 524 and 526. The first flip-flop 520 inputs an output of the first NAND gate 510, which is an input gate, to generate an output corresponding to the reset signal RS. The second NAND gate 540 inverts the OR signal of the oscillation frequency signal f _v of the VCO divided at a predetermined rate, that is, 1 / N, and the down signal DOWN of the previous state of the phase comparator 400, and the NAND gates The second flip-flop 530 composed of 534 and 536 receives data from the output of the second NAND gate 540 to generate an output corresponding to the reset signal RS. The third NAND gate 550 returns the up signal UP and the down signal DOWN to the original high level corresponding to the input reset signal RS. The fourth NAND gate 560, that is, the output control gate that controls the output of the up signal UP, inverts the outputs of the first NAND gate 510, the first flip-flop 520, and the third NAND gate 550. The AND signal generates an up signal UP. Up signal UP drives current supply portion 591 of charge pump 402 to supply current to low pass filter 404 to match the phase of oscillation frequency signal f _V of VC0 412.

Similarly, the fifth NAND gate 570, that is, the output control gate that controls the output of the down signal DOWN, includes the second NAND gate 540, the output of the second flip-flop 530, and the third NAND gate 550. Inverted AND of the output of to generate a down signal (DOWN). The down signal DOWN drives the current sink 595 of the charge pump 402 to sink current from the low pass filter 404, thereby reducing the amount of current in the low pass filter 404, and reducing the VCO 412. The phase of the oscillation frequency signal f _V of the signal is delayed to match the phase of the two signals input to the phase comparator 400. The OR gate 406 generates a reset signal RS by ORing the supply driving signal D1 and the sink driving signal D2 applied from the charge pump 402 as a reset signal generation unit, and generates the phase comparator 400. Reset it.

Hereinafter, the operation of the digital phase locked loop, in particular the phase comparator 400 and the charge pump 402, the phase comparison and the charge pumping method according to the present invention will be described in detail.

FIG. 6 is a flowchart illustrating a phase comparison and charge pumping method of a digital PLL according to the present invention, and comparing and comparing phases of a reference frequency signal f _R and an oscillation frequency signal f _{V of a} divided VCO. Generating an up / down signal in accordance with the result (steps 602 to 610), performing a current supply / sink in response to the up / down signal (step 620), and a phase after supplying / sinking the current. Initializing the comparison (operation 630).

The phase comparator 400 illustrated in FIG. 4 compares the phase difference between the two signals when the reference frequency signal f _R and the oscillation frequency signal f _{V of the} divided VCO are applied. In this case, when the dead zone occurs, the frequencies of the two signals are the same and the phase difference is small. Therefore, it is assumed that the frequencies of the two input signals are the same.

If the phase locked loop is locked and the phases of the frequency signal f _V and the reference frequency signal f _{R of the} divided VCO are completely coincident (step 602), the low level up signal UP and the down signal ( DOWN) occurs simultaneously (step 606), and the signals are inputted to the current supply unit 591 and the current sink unit 595 of the charge pump 402 to simultaneously perform current supply and current sinking (step 620). At that moment, the reset signal RS is generated by the reset signal generator 406 implemented as the OR gate, and the phase comparator 400 is initialized (step 630), and currents cancel each other, so that an error voltage does not occur. .

In addition, when the reference frequency signal f _R is out of phase with the oscillation frequency signal f _v divided among the two signals (operation 604), the up signal UP is generated first and becomes low (operation 608). . In other words, as soon as the input reference frequency signal (f _R) is lowered from the high level to the low level, the first NAND gate 510 is the previous state of the high level of the input reference frequency signal (f _R) and an up signal (UP) To invert the AND, and generate a high-level output. In addition, the fourth NAND gate 560 inverts and outputs the output of the first NAND gate 510, the output of the first flip-flop 520, and the output of the third NAND gate 550, thereby raising a low level UP signal UP. ) Here, the down signal DOWN remains high until the oscillation frequency signal f _V of the VCO 412 changes to the low level.

The low level up signal UP is input to the current supply unit 591 of the charge pump 402 and inverted through the inverter 594. The nMOS transistor M1 is driven to lower the drain voltage of the transistor M1. The drain voltage is output as the supply drive signal D1 and applied to the reset signal generator 406. In addition, the pMOS transistors M3 and M5 are driven to make the voltage output through the output terminal OUT of the charge pump higher than before. That is, the low-pass filter 404 is supplied with a current by the phase difference of the two signals (step 620), and operates in a direction to advance the phase of the oscillation frequency signal f _V of the VCO. At this time, when the oscillation frequency f _V of the VCO falls from high to low level after the up signal UP in the low state occurs, the second NAND gate 540 is at the previous high level of the down signal DOWN. The signal and the divided oscillation frequency signal f _V are inversely ANDed to generate a high level output, and the fifth NAND gate 570 outputs the second NAND gate 540 and the output of the second flip-flop 530. And an inverted AND of the output of the third NAND gate 550 to generate a down signal DOWN in a low state. The generated down signal DOWN is input to the current sink 595 of the charge pump 402 and at the moment when the current sink is to be performed, the drain voltage of the nMOS transistor M1 of the current supply unit 591, that is, the low state The supply driving signal D1 and the drain voltage of the nMOS transistor M13 of the current sink 495, that is, the low level sink driving signal D2 are ORed in the reset generator 406 to output a low level signal. The signal is input as the reset signal RS to initialize the phase comparator 400 (operation 630). Here, the up signal UP and the down signal DOWN are temporarily lowered to the low level and then changed back to the original high level by the reset signal, thereby reducing the current consumption generated in the conventional phase comparator.

In addition, if the oscillation frequency signal f _V of the divided VCO is out of phase with the reference frequency signal f _R , the down signal DOWN is generated first and goes low (step 610). Has a high state. That is, as described above, at the moment when the oscillation frequency signal f _V of the divided VCO falls from the high level to the low level, the second NAND gate 540 becomes the high signal and the oscillation frequency of the previous state of the down signal DOWN. The signal f _V is inversely ANDed to generate an output of a high state, and the fifth NAND gate 570 is an output of the second NAND gate 440, an output of the second flip-flop 530, and a third NAND gate ( The output of 550 is inversely ANDed to generate a down signal DOWN in a low state. The down signal DOWN in the low state is input to the current sink 595 of the charge pump 402 to drive the pMOS transistor M7 to make the drain voltage of the transistor M7 high. Here, the current flowing in the drain of the transistor M7 drives the nMOS transistors M9, M11, and M13 through the second resistor R2 and through the output terminal OUT through the third resistor R3 than before. A low low level signal is output. The low level output sinks a current equal to the phase difference in the low pass filter 404 (step 620), and operates in a direction of slowing the phase of the VCO output frequency. At this time, the up signal UP is generated after the down signal DOWN in the low state is generated and input to the current supply unit 591 of the charge pump 402, and at the moment the current supply is to be made, the current sink unit 595. The low level sink drive signal D2 and the low level supply drive signal D1 of the current supply unit 591 are ORed by the reset signal generator 406 to output the low level reset signal RS. In operation 630, the phase comparator 400 is initialized.

7, 8, and 9 illustrate the results of simulating the outputs of the phase comparator 400 and the charge pump 402 of the digital phase locked loop according to the present invention for a short time, and FIGS. 7A to 7E are phase comparators ( 400 shows the output of each part when the oscillation frequency signal f _V of the divided VCO input to 400 is in phase before the reference frequency signal f _R , and FIGS. 8A to 8E show the reference frequency signal f _R. that would showing the output of each part in the case of the previous phase than the VCO frequency signal (f _V) frequency divider, FIG. 9a ~ 9e matches the phase of the reference frequency signal (f _R) and the VCO frequency signal (f _V) dispensing Output is shown.

Here, two signals input to the phase comparator 400, that is, the reference frequency signal f _R and the divided oscillation frequency signal f _V have a frequency of 10 MHz, and in the case where there is a phase difference, the time delay is For example, 1ns.

As described above, Figure 7a shows that the VC0 frequency signal (f _V) (72) frequency divider to be input to the earlier phase than the reference frequency signal (f _R) (74), a reference frequency signal (f _R) (74) Has a time delay of 1 ns. FIG. 7B illustrates the low level up signal UP output from the phase comparator 400, and FIG. 7C illustrates the inverse of the down signal generated before the up signal UP occurs. 7d shows the inverse of the down signal shown in FIG. ) Is generated first to cause sinking of the current, and then the up signal UP is generated to generate a low level reset signal RS. FIG. 7E illustrates 1 ns of two signals output from the charge pump 402. The sink current corresponding to the phase difference is shown.

8A shows that the reference frequency signal f _R 82 is input in phase ahead of the divided VCO oscillation frequency signal f _V 84, and the divided oscillation frequency signal f _V is 1 ns. Has a time delay. FIG. 8B illustrates the low level up signal UP output from the phase comparator 400, and FIG. 8C illustrates the inverse of the down signal generated after the up signal UP occurs. 8D shows the inverse of the down signal after the up signal UP shown in FIG. ) Is generated to generate a low level reset signal RS, and FIG. 8E illustrates a supply current corresponding to a phase difference of 1 ns between two signals output from the charge pump 402.

9A illustrates a case where the divided VC0 frequency signal f _V 92 and the reference frequency signal f _R 92 coincide with each other, and thus there is no delay time between the two signals. 9B and 9C show the inverses of the low level up signal UP and down signal simultaneously occurring from the phase comparator 400. 9d shows that the up signal UP and the down signal DOWN are simultaneously output and the low level reset signal RS is generated at the same time as the current supply and the current sink shown in FIG. 9e are simultaneously generated. It is shown. From here. As shown in FIG. 9E, when the phases of the two signals coincide with each other, since the current supply and the current sink are simultaneously performed according to the simultaneous generation of the up signal UP and the down signal DOWN, the two currents cancel each other to zero. It can be seen that.

10A to 10E show the results of simulating the output of the phase comparator 400 according to the present invention for a long time, and 10a shows the oscillation frequency signal f _V and the reference frequency signal f _{R of the} divided VCOs having different phase differences. 10b represents the state of the up signal UP output from the phase comparator 400, and 10c represents the inverse of the down signal DOWN output from the phase comparator 400, 10d represents the VCO control voltage output through the charge pump 402 and the low pass filter 404, that is, the PLL is locked while the error voltage is constant, and 10e represents a phase comparator ( The reset signal RS applied to 400 is shown.

11 is output from the charge pump 402 according to the phase difference between the oscillation frequency signal f _V and the reference frequency signal f _{R of the} divided VCO input to the phase comparator 400 of the digital PLL according to the present invention. As a result of simulating the error current, it can be seen that an error current is generated without a dead zone even in a section having a small phase error unlike the conventional art, and thus an error voltage is generated without a dead zone.

As a result, by allowing the phase comparator to react by the reset signal generated by the charge pump, dead zones can be eliminated by generating an error voltage even with a small phase error.

According to the present invention, the dead zone which has a large influence on the jitter generated in the digital phase locked loop can be eliminated irrespective of the delay time, and the amount of unnecessary current consumed in the system can be reduced.

Claims (7)

A dead zone having a voltage controlled oscillator for outputting a signal having an oscillation frequency in response to a control voltage output from a low pass filter, and a programmable divider for dividing the signal having the oscillation frequency at a predetermined rate and outputting the divided signal. In a digital phase locked loop without A phase comparator comparing the phase difference between the divided signal and the reference frequency signal, outputting the compared result as an up / down signal, and resetting in response to a reset signal; A charge pump generating a supply / sink drive signal in response to the up / down signal, and supplying / sinking a current equal to the phase difference to / from the low pass filter in response to the supply / sink drive signal; And And a reset signal generating means for logically combining the supply drive signal and the sink drive signal and outputting the logical combined result as the reset signal. The method of claim 1, wherein the phase comparator, First inverted AND product for inversely ANDing the reference frequency with an up signal in a previous state; A first flip-flop that receives an output of the first inversion AND function and generates a first output and a second output corresponding to the reset signal; A second flip-flop having an oscillation frequency of the divided voltage controlled oscillator as an input and generating a first output and a second output corresponding to the reset signal; Second inversion AND products for inverting AND the oscillation frequency of the divided voltage controlled oscillator and the down signal in a previous state; Third inverted AND means for inversely ANDing the second outputs of the first and second flip-flops; Fourth logical multiplication means for inverting AND outputting the first inverse AND product, the first output of the first flip-flop, and the output of the third inverted AND product; And And a fifth inversion AND function for inverting AND outputting the second inversion AND product, the first output of the second flip-flop and the output of the third inversion AND product, and outputting the signal as a down signal. Digital phase locked loop without zones. The method of claim 2, wherein the charge pump, A current supply unit supplying a current corresponding to a phase difference to the low pass filter in response to the up signal; And And a current sink for sinking a current corresponding to a phase difference from the low pass filter in response to the down signal. The method of claim 3, wherein the current supply unit, An inverter for inverting the up signal; A first transistor having a gate connected to an output of the inverter and a drain and a source connected between the supply driving signal and a reference power source; A first resistor connected to the drain of the first transistor; A second transistor having a drain and a gate connected to one side of the first resistor and a source connected to a supply power; And And a third transistor having a gate connected to one side of the first resistor and a source and a drain connected between the supply power and the output terminal. The method of claim 3, wherein the current sink unit, A fourth transistor having a gate connected to the down signal and a source connected to the supply power; A second resistor connected to one side of the fourth transistor; A fifth transistor having a drain and a gate connected to the other side of the second resistor, and a source connected to the reference power source; A sixth transistor having a gate connected to the other side of the second resistor and a drain and a source connected between the output terminal and the reference power source; A seventh transistor having a gate connected to the other side of the sixth resistor and a drain connected to the sink driving signal; And And a third resistor coupled between the supply power supply and the sink drive signal. Phase performed in a digital phase locked loop having a voltage controlled oscillator for outputting a signal having an oscillating frequency corresponding to the control voltage output from the low pass filter and a divider for dividing and outputting the signal having the oscillating frequency at a predetermined rate In the comparison and charge pumping method, (a) comparing the phase of the reference frequency signal with the phase of the divided signal; (b) generating an up / down signal corresponding to the compared result; Supplying / sinking current to / from the low pass filter corresponding to the phase difference compared in response to the up / down signal; And Initiating said phase comparison after said supplying / sinking said current. The method of claim 6, wherein the steps (a) and (b) Determining whether a phase of the reference frequency signal coincides with a phase of the divided signal; Simultaneously generating the up signal and the down signal when the reference frequency signal and the phase of the divided signal coincide with each other; Determining that the phase of the reference frequency signal is ahead of the phase of the divided signal if the reference frequency signal and the phase of the divided signal do not match; Generating the up signal when the phase of the reference frequency signal is ahead of the phase of the divided signal; And And generating the down signal when the phase of the divided signal is ahead of the phase of the reference frequency signal.