KR19990006042A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents
Capacitor Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990006042A KR19990006042A KR1019970030264A KR19970030264A KR19990006042A KR 19990006042 A KR19990006042 A KR 19990006042A KR 1019970030264 A KR1019970030264 A KR 1019970030264A KR 19970030264 A KR19970030264 A KR 19970030264A KR 19990006042 A KR19990006042 A KR 19990006042A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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Abstract
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 고유전 특성을 가지는 탄탈늄산화막을 캐패시터의 유전막으로 형성하되, LPCVD 탄탈늄산화막과 PECVD 탄탈늄산화막을 나누어 증착하여 PECVD에서의 나쁜 단차피복성과 LPCVD의 나쁜 전기적 특성을 개선하여 전하저장전극이 복잡한 구조를 가져도 단차피복성이 우수하고 누설전류 등 전기적 특성이 개선되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a tantalum oxide film having high dielectric properties is formed as a dielectric film of a capacitor, and the LPCVD tantalum oxide film and the PECVD tantalum oxide film are separated and deposited. Even if the charge storage electrode has a complicated structure by improving the bad electrical characteristics of, the step coverage is excellent and the electrical characteristics such as leakage current can be improved to improve process yield and reliability of device operation.
Description
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 특히 고집적 메모리 소자에 사용되는 캐패시터의 유전막을 고유전 특성을 지닌 탄탄륨 옥사이드를 저압 화학기상증착(Low Pressure Chemical Vapor Deposition; 이하 LPCVD라 칭함)법과 플라즈마 여기(Plasma Enhanced) CVD 법으로 형성하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, a low pressure chemical vapor deposition (LPCVD) method of tantalum oxide having high dielectric properties of a dielectric film of a capacitor used in a high density memory device and The present invention relates to a method for manufacturing a capacitor of a semiconductor device which can be formed by plasma enhanced CVD to improve process yield and reliability of device operation.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있어 리플레쉬 타임등의 소자 특성 확보와 고집적화가 어려워지고 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size, which makes it difficult to secure device characteristics such as refresh time and high integration.
이때 상기 캐패시터는 주로 다결정 실리콘을 도전체로 하여 산화막, 질화막 또는 그 적층막인 오.엔.오(oxide-nitride-oxide)막을 유전체로 사용하고 있다.At this time, the capacitor mainly uses an oxide film, a nitride film, or an O-oxide film (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor.
따라서 유전막의 유전상수(dielectric constant)와 캐패시터의 표면적에 비례하고, 유전막의 두께에 반비례하는 정전용량(C)을 증가시키기 위하여 유전상수가 높은 물질을 유전체로 사용하거나, 유전막을 얇게 형성하거나 또는 캐패시터의 표면적을 증가시키는 등의 방법이 있다.Therefore, in order to increase the capacitance (C) which is proportional to the dielectric constant of the dielectric film and the surface area of the capacitor and inversely proportional to the thickness of the dielectric film, a material having a high dielectric constant is used as the dielectric material, a thin dielectric film or a capacitor is formed. There is a method such as increasing the surface area of the.
그러나 이러한 방법들은 모두 각각의 문제점을 가지고 있다.However, all these methods have their own problems.
즉, 높은 유전상수를 갖는 유전물질, 예를들어 Ta2O5, TiO2또는 SrTiO3등이 연구되고 있으나, 이러한 물질들의 접합 파괴전압등과 같은 신뢰도 및 박막특성등이 확실하게 확인되어 있지 않아 실제 소자에 적용하기가 어렵고, 유전막 두께를 감소시키는 것은 소자 동작시 유전막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.That is, dielectric materials having high dielectric constants such as Ta 2 O 5 , TiO 2 or SrTiO 3 have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. Difficult to apply to a real device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.
더욱이 캐패시터의 전하저장전극의 표면적을 증가시키기 위하여 다결정 실리콘층을 다층으로 형성한 후, 이들을 관통하여 서로 연결시키는 핀(Pin) 구조로 형성하거나, 콘택의 상부에 실린더 형상의 전하저장전극을 형성하는 등의 복잡한 구조가 사용되기도 한다.Furthermore, in order to increase the surface area of the charge storage electrode of the capacitor, the polycrystalline silicon layer is formed in a multi-layer, and then formed into a pin structure through which they are connected to each other, or a cylindrical charge storage electrode is formed on the contact. Complex structures such as these may be used.
그러나 상기와 같은 복잡한 구조상에는 탄탈륨 옥사이드(Ta2O5)등의 고유전막을 적용하기 어려운 문제점이 있다.However, there is a problem in that it is difficult to apply a high dielectric film such as tantalum oxide (Ta 2 O 5 ) on such a complicated structure.
상기와 같은 복잡한 토폴로지를 가지는 고집적 소자의 전하저장전극상에 탄탈륨 옥사이드막을 도포하기 위하여는 양호한 단차피복성과 높은 유전율이 필수적으로 요구된다.In order to apply a tantalum oxide film on the charge storage electrode of the highly integrated device having such a complex topology, good step coverage and high dielectric constant are required.
종래 기술로서의 탄탈늄산화막 형성 방법은 크게 LPCVD법과 플라즈마를 여가시키는 PECVD 법으로 형성할 수 있다.The tantalum oxide film forming method of the prior art can be largely formed by the LPCVD method and the PECVD method which makes the plasma free.
먼저, PECVD법은 탄탈늄 에칠레이트(Ta(OC2CH5)5)를 기상상태로 만들어 N2O가스와 반응시켜 증착하는데, 상기 PECVD법에 의한 탄탈늄산화막는 캐패시턴스 등 전기적 특성은 우수하나 피복성이 불량하여 소자에 적용할 경우 누설전류 특성이 매우 나쁘다.First, the PECVD method deposits tantalum acrylate (Ta (OC 2 CH 5 ) 5 ) in a gaseous state and reacts with N 2 O gas. The tantalum oxide film by PECVD has excellent electrical characteristics such as capacitance but is coated. The leakage current characteristics are very bad when applied to devices due to poor properties.
또한 LPCVD법은 탄탈늄 에칠레이트(Ta(OC2CH5)5)를 기상상태로 만들어 산소와 반응시켜 증착하는데, LPCVD법으로 형성되는 탄탈늄산화막는 단차피복성은 좋으나, 평판상에서 전기적 누설전류 특성이 PECVD법으로 증착된 막에 비해 나쁜 특성을 가진다.In addition, the LPCVD method forms a tantalum acrylate (Ta (OC 2 CH 5 ) 5 ) in a gaseous state and reacts with oxygen to deposit the tantalum oxide film formed by the LPCVD method. It has poor properties compared to the film deposited by PECVD.
상기와 같이 종래 기술에 따른 반도체소자의 캐패시터 제조방법은 LPCVD법으로 증착된 탄탈늄산화막은 단차피복성은 우수하나 전기적 누설전류 특성이 떨어지고, PECVD법으로 증착된 탄탈늄산화막은 LPCVD법으로 증착된 막에 비하여 단차피복성이 떨어지는 특성을 가지고 있어서 실제 소자 적용 경우에 누설 전류 특성이 매우 열화되어 두가지 방법 모두 유전막으로 적용하기가 어려운 문제점이 있다.As described above, the capacitor manufacturing method of a semiconductor device according to the prior art is a tantalum oxide film deposited by LPCVD method is excellent in step coverage, but the electrical leakage current characteristics are inferior, the tantalum oxide film deposited by PECVD method is a film deposited by LPCVD method Compared with the characteristics of the step coverage, the leakage current characteristic is very deteriorated in the actual device application, and thus, both methods are difficult to apply as dielectric films.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 LPCVD법과 PECVD법의 탄탈늄산화막을 번갈아 증착하여 PECVD법에 의한 탄탈늄산화막막의 나쁜 단차피복성과 LPCVD 법으로 증착된 탄탈늄산화막의 열악한 누설전류 특성을 동시에 개선하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 캐패시터 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to alternately deposit the tantalum oxide film of the LPCVD method and the PECVD method, and the poor step coverage of the tantalum oxide film by the PECVD method and the tantalum deposited by the LPCVD method. The present invention provides a method of manufacturing a capacitor of a semiconductor device which can improve process yield and reliability of device operation by simultaneously improving poor leakage current characteristics of an oxide film.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 캐패시터 제조방법의 특징은 하부 전극과 유전막 및 상부전극으로 구성되는 반도체소자의 캐패시터 제조방법에 있어서, 상기 유전막의 총 두께중 일부 두께를 LPCVD법에 의한 탄탈늄산화막으로 형성하는 공정과, 상기 유전막의 나머지 두께를 PECVD법에 의한 탄탈늄산화막으로 형성하는 공정을 구비함에 있다.A feature of the method for manufacturing a capacitor of a semiconductor device according to the present invention for achieving the above object is a LPCVD method for manufacturing a capacitor of a semiconductor device consisting of a lower electrode, a dielectric film and an upper electrode, LPCVD is a part of the total thickness of the dielectric film Forming a tantalum oxide film by a method; and forming a remaining thickness of the dielectric film into a tantalum oxide film by a PECVD method.
이하, 본 발명에 따른 반도체소자의 캐패시터 제조방법에 관하여 상세히 살펴보면 다음과 같다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail.
먼저, 소정의 하부 구조, 예를들어 MOS FET와 비트선등을 구비하는 반도체 기판상에 전하저장전극 콘택홀을 구비하는 층간절연막을 형성하고, 상기 전하저장전극 콘택홀을 메우는 다결정 실리콘층으로된 전하저장전극을 형성한 후, LPCVD법과 PECVD법을 번갈아 탄탈늄산화막을 증착하여 유전막을 형성한다.First, an interlayer insulating film having charge storage electrode contact holes is formed on a semiconductor substrate having a predetermined substructure, for example, a MOS FET and a bit line, and a charge of a polycrystalline silicon layer filling the charge storage electrode contact holes is formed. After forming the storage electrode, a dielectric film is formed by depositing a tantalum oxide film alternately between LPCVD and PECVD.
이때 상기 LPCVD 방법은 탄탈륨 에칠레이트를 170℃∼190℃로 유지되는 기화기에서 기상상태로 만들고 산소와 혼합하여, 반응로 내의 압력을 0.8torr∼1.2torr로 유지하고, 산소양은 100∼200sccm, 350℃∼450℃로 가열된 웨이퍼에 전체 유전막 두께의 20∼60%정도를 증착한다. 이것은 PECVD의 단점을 보완 하기 위한 방법으로 LPCVD의 우수한 단차피복성을 이용하기 위한 것이다.At this time, the LPCVD method makes tantalum ethylate in a vapor phase in a vaporizer maintained at 170 ° C to 190 ° C and mixes it with oxygen to maintain the pressure in the reactor at 0.8torr to 1.2torr, and the amount of oxygen is 100 to 200sccm and 350 ° C. About 20 to 60% of the total dielectric film thickness is deposited on the wafer heated to ˜450 ° C. This is to take advantage of the excellent step coverage of LPCVD as a method to compensate for the disadvantage of PECVD.
그다음 상기의 LPCVD 탄탈늄산화막상에 탄탈늄 에칠레이트를 170℃∼190℃로 유지도는 기화기에서 기상상태로 만들고 N2O 가스와 혼합하여 반응로 내의 압력을 0.8torr∼1.2torr로 유지하고, N2O양은 80∼150sccm 350℃∼450℃로 가열된 웨이퍼에 80Watt∼200Watt의 플라즈마를 여기시켜 전체 두께의 40∼80%정도 두께로 형성한다. 이것은 LPCVD로 증착된 박막을 플라즈마 처리하여 전기적 특성을 개선시키기 위한 것이다.Then, on the LPCVD tantalum oxide film, tantalum acrylate is maintained at 170 ° C to 190 ° C in a vapor phase in a vaporizer and mixed with N 2 O gas to maintain a pressure in the reactor at 0.8torr to 1.2torr, The amount of N 2 O is excited by a plasma of 80 Watts to 200 Watts on a wafer heated to 80 to 150 sccm and 350 to 450 degrees Celsius to form a thickness of about 40 to 80% of the total thickness. This is to improve the electrical properties by plasma treatment of the thin film deposited by LPCVD.
또한 상기의 LPCVD 탄탈늄산화막을 각각 산소 또는 N2O 가스 플라즈마로 5∼15분간 처리하거나, PECVD 탄탈늄산화막을 N2O 가스 플라즈마로 5∼15분간 처리하고, LPCVD 탄탈늄산화막을 산소 분위기에서 750∼1000℃ 고온에서 열처리하거나, PECVD 탄탈늄산화막을 산소 가스 분위기에서 750∼1000℃ 고온 열처리하여 박막 특성을 향상시킬 수도 있다.In addition, the above-described LPCVD tantalum oxide film is treated with oxygen or N 2 O gas plasma for 5 to 15 minutes, or the PECVD tantalum oxide film is treated with N 2 O gas plasma for 5 to 15 minutes, and the LPCVD tantalum oxide film is treated in an oxygen atmosphere. The thin film characteristics may be improved by heat treatment at a high temperature of 750 to 1000 ° C. or by heat treatment of the PECVD tantalum oxide film at a high temperature of 750 to 1000 ° C. in an oxygen gas atmosphere.
더우기 상기의 LPCVD 및 PECVD 탄탈늄산화막을 번갈아 증착할 때 동일 챔버내에서 실시할 수도 있으며, 각기 다른 챔버에서 형성할때에도 하나의 시스템 내에서 진공이 깨지지 않는 로드록(loadlock) 시스템으로 실시할수도 있다. 이경우 진공이 깨지는 경우 보다 우수한 막질을 가지게되는 것을 알수 있다.Furthermore, the above LPCVD and PECVD tantalum oxide films may be alternately deposited in the same chamber, or may be implemented as a loadlock system in which vacuum is not broken in one system even when formed in different chambers. . In this case, it can be seen that the film quality is better than when the vacuum is broken.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 캐패시터 제조방법은 고유전 특성을 가지는 탄탈늄산화막을 캐패시터의 유전막으로 형성하되, LPCVD 탄탈늄산화막과 PECVD 탄탈늄산화막을 나누어 증착하여 PECVD에서의 나쁜 단차피복성과 LPCVD의 나쁜 전기적 특성을 개선하여 전하저장전극이 복잡한 구조를 가져도 단차피복성이 우수하고 누설전류 등 전기적 특성이 개선되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the capacitor manufacturing method of the semiconductor device according to the present invention, a tantalum oxide film having high dielectric properties is formed as a dielectric film of the capacitor, but the LPCVD tantalum oxide film and the PECVD tantalum oxide film are separated and deposited, thereby causing a bad process in PECVD. Even if the charge storage electrode has a complicated structure by improving step coverage and poor electrical characteristics of LPCVD, the step coverage is excellent and the electrical characteristics such as leakage current are improved, thereby improving process yield and device operation reliability.
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| KR1019970030264A KR100275330B1 (en) | 1997-06-30 | 1997-06-30 | Method of fabricating capacitor of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030264A KR100275330B1 (en) | 1997-06-30 | 1997-06-30 | Method of fabricating capacitor of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990006042A true KR19990006042A (en) | 1999-01-25 |
| KR100275330B1 KR100275330B1 (en) | 2000-12-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970030264A KR100275330B1 (en) | 1997-06-30 | 1997-06-30 | Method of fabricating capacitor of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR100275330B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100417860B1 (en) * | 2001-09-13 | 2004-02-05 | 주식회사 하이닉스반도체 | mehtod for fabricating capacitor |
| KR100417859B1 (en) * | 2001-09-13 | 2004-02-05 | 주식회사 하이닉스반도체 | mehtod for fabricating capacitor |
| KR100646921B1 (en) * | 2000-06-20 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor |
| KR100680491B1 (en) * | 2000-06-28 | 2007-02-08 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor |
-
1997
- 1997-06-30 KR KR1019970030264A patent/KR100275330B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100646921B1 (en) * | 2000-06-20 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor |
| KR100680491B1 (en) * | 2000-06-28 | 2007-02-08 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor |
| KR100417860B1 (en) * | 2001-09-13 | 2004-02-05 | 주식회사 하이닉스반도체 | mehtod for fabricating capacitor |
| KR100417859B1 (en) * | 2001-09-13 | 2004-02-05 | 주식회사 하이닉스반도체 | mehtod for fabricating capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100275330B1 (en) | 2000-12-15 |
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