KR19990006041A - Manufacturing method of MOS field effect transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS FET, wherein etching damage is performed after patterning a gate electrode in a process of forming a MOS FET having a gate electrode having a W-polyside structure, which is a laminated structure of a polycrystalline silicon layer and a W-silicide layer pattern. And a nitrogen fuse box in the heat treatment tube in order to maintain a large amount of diffused water reacted with W-silicide in a heat treatment process performed to compensate for the subsequent LDD ion implantation damage below a certain level. Since heat treatment was carried out in a nitrogen-excluded state and a screen oxide film was formed on the semiconductor substrate, moisture reacted with the W-silicide film was removed to prevent the formation of mushroom-shaped protrusions by the reaction of W-silicide and water. Subsequent LDD formation and source / drain regions have been formed, making it possible to form MOS FETs as designed Process yield and reliability of device operation can be improved.

Description

Manufacturing method of MOS field effect transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a metal oxide semi conductor field effect transistor (hereinafter referred to as a MOS FET), and particularly, to forming an insulating spacer in a gate electrode using a polyside structure of a polycrystalline silicon layer and a W-silicide layer. The present invention relates to a method of manufacturing a MOS FET which can remove external moisture and form an insulating film to prevent the formation of an ear-shaped protrusion by oxidation of the W-silicide film, thereby improving process yield and device operation reliability.

As the semiconductor devices become more integrated, the gate electrodes of the MOS FETs also decrease in width, but when the width of the gate electrodes decreases by N times, the electrical resistance of the gate electrodes increases by N times, which reduces the operating speed of the semiconductor devices. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon layer, which is a laminated structure of the polysilicon layer and the silicide, may be used as the low resistance gate by using the polysilicon layer / oxide layer interface property that exhibits the most stable MOSFET characteristics.

In general, the most important function of the transistors constituting the semiconductor circuit is current driving capability, and the channel width of the MOSFET is adjusted in consideration of this. The most widely used MOSFET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain region. Here, the sheet resistance of the gate electrode is about 30 to 70 kΩ / □, the sheet resistance of the source / drain regions is about 70 to 150 kΩ / □ for N +, about 100 to 250 kΩ / ㅁ for P +, and the gate electrode or source / In the case of a contact formed on the drain region, the contact resistance is about 30 to 70 mA / square per contact.

In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide layer may be formed only on the gate electrode and the source / drain regions using a salicide (self-aligned silicide) method or a selective metal film deposition method. The current driving capability of the MOS FET was increased. Among these silicides, TiSi ₂ has the lowest resistance, relatively excellent thermal stability, and an easy manufacturing method.

The use of Ti silicide significantly reduces the sheet resistance of the gate electrode and the source / drain regions to about 5 mA / W and the contact resistance is about 3 mA / W or less per contact, which increases the current driving capability of the MOSFET by more than 40%. It is possible.

Therefore, in the DRAM devices of more than giga-class or logic devices requiring high integration and high-speed operation, the need for lowering the sheet resistance by forming silicide films on the gate electrode and the source / drain regions is increasing, resulting in excellent thermal stability W-silicide films. Also used as a material of the gate electrode.

Referring to FIG. 1, a conventional method of manufacturing a gate electrode using W-silicide is as follows.

First, the gate oxide film 12 is formed on the semiconductor substrate 10, and then the doped polycrystalline silicon layer 14 and the W-silicide layer 16, which become gate electrodes, are formed on the semiconductor substrate 10. Patterning the W-silicide layer 16 and subsequently etching the polycrystalline silicon layer 14 to form a gate electrode having a pattern of the polycrystalline silicon layer 14 and the W-silicide layer 16, and forming the gate electrode pattern. After the thinning, a screen oxide film 18 is formed on the semiconductor substrate 10 in order to prevent damage to the substrate and compensation for etching damage caused by LDD ion implantation.

In the screen oxide film 18 forming step, the etching damage is compensated for about 1 hour in a N ₂ atmosphere at 750 ° C. before thermal oxidation, and a screen oxide film is formed in a dry O ₂ atmosphere at about 50 kPa.

After that, the LDD region 20 is formed on the semiconductor substrate 10 on both sides of the gate electrode with low concentration impurity, an oxide film is formed on the entire surface of the structure, and the oxide film is anisotropically etched from the front to insulate the sidewall of the gate electrode. The spacers 22 are formed, and the source / drain regions 24 are formed in the semiconductor substrate 10 by high concentration ion implantation.

As described above, in the method of manufacturing a semiconductor device according to the related art, the surface of the W-silicide layer reacts with external air in the heat treatment and oxidation process before the LDD region is formed to expand the volume, thereby forming a mushroom-shaped protrusion 26. . The mushroom shape appears to be caused by the air remaining between the wafers during wafer loading reacted with the etched damaged W-silicide, especially the H ₂ O and WSix bonds, which diffuse faster than oxygen. As a result, the effective channel length is longer than at design time, resulting in a decrease in reliability of device operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to etch damage compensation and screen which is performed after gate electrode patterning in the fabrication of a MOS FET in which a polycrystalline silicon layer W-silicide film pattern is used as a gate electrode. Using a nitrogen fuse box before the heat treatment process to form the oxide film, the moisture in the air in the heat-treating tube is controlled to 100 ppm or less, thereby preventing the formation of mushroom shape by the reaction of W-silicide and water during the heat treatment process. It is to provide a method of manufacturing a MOS FET that can improve the reliability.

1 is a cross-sectional view of a MOS FET formed according to the prior art.

2 is a cross-sectional view of a MOS FET formed in accordance with the present invention.

＊ Explanation of symbols on main parts of drawing

10: semiconductor substrate, 12: gate oxide film, 14: polycrystalline silicon layer, 16: W-silicide film, 18: screen oxide film, 20: LDD region, 22: spacer, 24: source / drain region, 26: protrusion

The MOS FET manufacturing method according to the present invention for achieving the above object is a step of forming a gate oxide film on a semiconductor substrate,

Forming a gate electrode having a polycrystalline silicon layer and a W-silicide layer pattern on the gate oxide layer;

Forming a screen oxide film on the exposed surface of the semiconductor substrate by heat-treating the semiconductor substrate of the structure, wherein the moisture in the air is below a predetermined level by a nitrogen fuse box during the loading process into the heat-treating tube;

And forming a low concentration impurity region in the semiconductor substrate on both sides of the gate electrode.

Hereinafter, a method of manufacturing a MOS FET according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a method of manufacturing a MOS FET according to the present invention.

First, a gate oxide film 12 is formed on a P-type silicon wafer semiconductor substrate 10, and a doped polycrystalline silicon layer 14 and a W-silicide film 16, which become gate electrodes, are sequentially formed thereon. Afterwards, the W-silicide layer 16 is patterned by an etching process using a tri layer resist (hereinafter referred to as a TLR) method, and the polycrystalline silicon layer 14 is continuously etched to form a polycrystalline silicon layer 14. A gate electrode having a polyside structure having a W-silicide film 16 pattern is formed.

Then, in order to prevent damage to the substrate due to the gate electrode patterning and subsequent damage to the LDD ion implantation, an annealing heat treatment process is performed to form the screen oxide film 18 on the semiconductor substrate 10. Here, the heat treatment process is first provided with a nitrogen fuse box in the heat treatment tube, and then maintain the nitrogen atmosphere from the wafer loading into the tube to discharge the moisture between the wafers to maintain a minimal level of 0.1 ~ 1000ppm during heat treatment, The heat treatment is performed for about 30 to ₂ hours in an N ₂ atmosphere at a temperature of about 700 to 850 ° C. to form a screen oxide film 18 having a thickness of about 30 to 100 Pa in a dry O ₂ atmosphere.

After that, the LDD region 20 is formed on the semiconductor substrate 10 on both sides of the gate electrode with low concentration impurity, and the insulating spacer 22 is formed on the sidewall of the gate electrode by applying an insulating film on the entire surface and an anisotropic etching method. Source / drain regions 24 are formed by implanting high concentration ions into the semiconductor substrate 10 on both sides of the electrode.

As described above, the method of manufacturing the MOS FET according to the present invention is a gate electrode in the process of forming a MOS FET having a gate electrode having a W-polyside structure, which is a laminated structure of a polycrystalline silicon layer and a W-silicide film pattern. In the heat treatment process performed to compensate for the etching damage and subsequent LDD ion implantation damage after the patterning, after the nitrogen fuse box is provided in the heat treatment tube to maintain the water having a large diffusion degree reacted with the W-silicide below a certain level, Since the heat treatment was carried out in a nitrogen-excluded state from the loading into the tube and a screen oxide film was formed on the semiconductor substrate, the water reacted with the W-silicide film was removed to form a mushroom by reaction of the W-silicide and water. To prevent the formation of overhangs and to form subsequent LDD formation and source / drain regions. To form a MOS FET's there is an advantage capable of improving the reliability of the process yield and device operation.

Claims (4)

Forming a gate oxide film on the semiconductor substrate, forming a gate electrode having a polycrystalline silicon layer and a W-silicide film pattern on the gate oxide film, and heat-treating the semiconductor substrate of the structure to expose the surface of the semiconductor substrate. Forming a screen oxide film on the substrate, and forming a low concentration impurity region on the semiconductor substrate on both sides of the gate electrode by a nitrogen fuse box during the loading process into the heat treatment tube. MOS FET manufacturing method. The method of manufacturing a MOS FET according to claim 1, wherein the heat treatment step is performed for 30 to ₂ hours in an N ₂ atmosphere at a temperature of about 700 to 850 ° C. The method of manufacturing a MOS FET according to claim 1, wherein the moisture during said heat treatment is maintained at a level of 0.1 to 1000 ppm. The method of manufacturing a MOS FET according to claim 1, wherein said screen oxide film is formed to have a thickness of 30 to 100 kHz in a dry O ₂ atmosphere.