KR19990006038A - Method for manufacturing gate electrode of semiconductor device - Google Patents
Method for manufacturing gate electrode of semiconductor device Download PDFInfo
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- KR19990006038A KR19990006038A KR1019970030260A KR19970030260A KR19990006038A KR 19990006038 A KR19990006038 A KR 19990006038A KR 1019970030260 A KR1019970030260 A KR 1019970030260A KR 19970030260 A KR19970030260 A KR 19970030260A KR 19990006038 A KR19990006038 A KR 19990006038A
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- polycrystalline silicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000009832 plasma treatment Methods 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 230000004888 barrier function Effects 0.000 abstract description 7
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 게이트전극 제조방법에 관한 것으로서, W-실리사이드 구조의 게이트전극을 형성함에 있어 다결정 실리콘층상에 형성된 얇은 W층을 질소 플라즈마 처리하여 확산방지막인 WNx층을 형성하고, 연속적으로 W층을 형성한 후, 패턴닝하여 W층과 WNx 및 다결정 실리콘층 패턴으로된 게이트전극을 형성하였으므로, 게이트전극의 면저항이 감소되어 소자의 동작 특성이 향상되고, 한번의 공정으로 W/WNx 막이 형성되므로 공정 스텝이 감소하고 제조 비용 및 시간이 절감할 수 있는 이점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a semiconductor device. In forming a gate electrode having a W-silicide structure, a thin W layer formed on a polycrystalline silicon layer is subjected to nitrogen plasma treatment to form a WNx layer, which is a diffusion barrier, and continuously W. After forming the layer, a gate electrode having a W layer, a WNx, and a polycrystalline silicon layer pattern was formed by patterning, thereby reducing the sheet resistance of the gate electrode, thereby improving the operation characteristics of the device, and forming a W / WNx film in one step. This reduces the number of process steps and reduces manufacturing costs and time.
Description
본 발명은 반도체소자의 게이트전극 제조방법에 관한 것으로서, 특히 모스전계효과 트랜지스터(Metal Oxide Semi conductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극을 다결정 실리콘층과 W층의 적층 구조로 형성하되, 두층 사이의 확산방지막을 얇은 W층의 질소 플라즈마 처리하는 방법으로 형성하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 게이트전극 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a semiconductor device. In particular, a gate electrode of a metal oxide semi-conductor field effect transistor (hereinafter referred to as a MOS FET) is formed in a stacked structure of a polycrystalline silicon layer and a W layer. The present invention relates to a method of manufacturing a gate electrode of a semiconductor device capable of improving the process yield and reliability of device operation by forming a diffusion barrier between two layers by a nitrogen plasma treatment of a thin W layer.
반도체소자가 고집적화되어 감에 따라 모스 전계효과 트랜지스터(Metal Oxide Semi conductor Field Effect Transistor; 이하 MOS FET라 칭함)의 게이트전극도 폭이 줄어들고 있으나, 게이트 전극의 폭이 N배 줄어들면 게이트전극의 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저 저항 게이트로서 사용된다.As semiconductor devices become more integrated, gate electrodes of metal oxide semi-conductor field effect transistors (hereinafter referred to as MOS FETs) are decreasing in width, but when the width of gate electrodes is reduced by N times, the electrical resistance of the gate electrode is reduced. This increases by N times, which causes a problem of lowering the operating speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate by using the property of the polysilicon layer / oxide layer interface showing the most stable MOSFET characteristics.
일반적으로 반도체 회로를 구성하는 트랜지스터의 기능에서 가장 중요한 기능은 전류구동능력이며, 이를 고려하여 MOSFET의 채널 폭을 조정한다. 가장 널리 쓰이는 MOSFET는 게이트 전극으로 불순물이 도핑된 폴리실리콘층을 사용하고, 소오소/드레인 영역은 반도체기판상에 불순물이 도핑된 확산 영역이 사용된다. 여기서 게이트전극의 면저항은 약 30∼70Ω/□ 정도이며, 소오스/드레인 영역의 면저항은 N+의 경우에는 약 70∼150Ω/□, P+의 경우 약 100∼250Ω/□ 정도이며, 게이트 전극이나 소오스/드레인 영역 상에 형성되는 콘택의 경우에는 콘택 저항이 하나의 콘택당 약 30∼70Ω/□ 정도이다.In general, the most important function of the transistors constituting the semiconductor circuit is current driving capability, and the channel width of the MOSFET is adjusted in consideration of this. The most widely used MOSFET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used for the source and drain regions. Here, the sheet resistance of the gate electrode is about 30 to 70 kΩ / □, the sheet resistance of the source / drain regions is about 70 to 150 kΩ / □ for N +, about 100 to 250 kΩ / □ for P +, and the gate electrode or source / In the case of a contact formed on the drain region, the contact resistance is about 30 to 70 mA / square per contact.
이와 같이 게이트전극과 소오스/드레인 영역의 높은 면저항 및 콘택 저항을 감소시키기 위하여 실리사이드(salicide; self-aligned silicide)방법이나 선택적 금속막 증착 방법으로 게이트전극과 소오스/드레인 영역의 상부에만 금속 실리사이드막을 형성하여 MOS FET의 전류구동능력을 증가시켰다. 이러한 실리사이드중에서 TiSi2는 저항이 가장 낮고, 비교적 열 안정성이 우수하고 제조방법이 용이하여 가장 각광받고 있다.In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide layer is formed only on the gate electrode and the source / drain regions by a method of silicide (self-aligned silicide) or selective metal film deposition. As a result, the current driving capability of the MOS FET is increased. Among these silicides, TiSi 2 has the lowest resistance, relatively excellent thermal stability, and an easy manufacturing method.
Ti 실리사이드를 사용하면 게이트전극과 소오스/드레인 영역의 면저항을 약 5Ω/□, 콘택저항은 콘택당 약 3Ω/□ 이하로 현저하게 감소되어 MOSFET의 전류구동능력이 40% 이상 증가되므로 MOSFET의 고집적화가 가능하다.The use of Ti silicide significantly reduces the sheet resistance of the gate electrode and the source / drain regions to about 5 mA / □ and the contact resistance is about 3 mA / □ or less per contact, which increases the current driving capability of the MOSFET by more than 40%. It is possible.
따라서 기가급 이상의 DRAM 소자나, 고집적화와 동시에 고속동작이 요구되는 로직 소자에서는 게이트전극과 소오스/드레인 영역의 표면에 실리사이드막을 형성하여 면저항을 낮추어 줄 필요성이 증가되고 있으며, 상기 Ti실리사이드막 보다 열적 안정성이 우수한 W-실리사이드막이 게이트전극으로 사용되기도 하지만 실리사이드막 자체의 저항이 통상의 금속보다는 높아 기가급 이상의 소자에서는 열적 안정성이 우수하고 저항이 낮은 W층을 사용하기도 한다.Therefore, in a DRAM device having a giga-level or more or a logic device requiring high integration and high-speed operation, the necessity of lowering sheet resistance by forming a silicide film on the surface of the gate electrode and the source / drain regions is increasing, and more thermal stability than the Ti silicide film. Although this excellent W-silicide film is used as a gate electrode, the resistance of the silicide film itself is higher than that of a conventional metal, so that a W layer having excellent thermal stability and low resistance may be used in a device having a giga-level or higher.
도시되어 있지는 않으나, 종래의 W층을 이용한 게이트전극 제조방법을 살펴보면 다음과 같다.Although not shown, a conventional method of manufacturing a gate electrode using a W layer is as follows.
먼저, 반도체기판상에 게이트산화막을 형성하고, 그 상부에 게이트전극이 되는 도핑된 다결정 실리콘층을 형성한 후, 상기 다결정 실리콘층상에 확산방지막으로 TiN이나 WNx층을 반응성 스퍼터링 방법으로 형성하고, W층을 형성하고, 패턴닝하여 W층과 확산방지막 및 다결정 실리콘층 패턴으로된 게이트전극을 형성한다.First, a gate oxide film is formed on a semiconductor substrate, and a doped polycrystalline silicon layer is formed on the semiconductor substrate, and then a TiN or WNx layer is formed on the polycrystalline silicon layer by a reactive sputtering method. A layer is formed and patterned to form a gate electrode having a W layer, a diffusion barrier film, and a polycrystalline silicon layer pattern.
상기와 같이 종래 기술에 따른 반도체소자의 저저항 게이트전극으로 다결정 실리콘층과 확산방지막 및 W층의 적층 구조를 사용하는데, 적층막이 다양하여 적층 공정시 불량 발생의 요인이 증가되고, 공정이 복잡하여 수율이 떨어지는 등의 문제점이 있다.As a low resistance gate electrode of the semiconductor device according to the prior art as described above, a multilayer structure of a polycrystalline silicon layer, a diffusion barrier film, and a W layer is used. There is a problem such as a poor yield.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 다결정 실리콘층과 W층의 적층 구조로된 게이트전극을 형성하되, 별도의 확산방지막 증착공정 없이 W/WNx/poly-Si 구조의 위드라인을 형성하여 공정이 간단하고, 확산방지가 이루어져 소자의 특성이 향상되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 게이트전극 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a gate electrode having a laminated structure of a polycrystalline silicon layer and W layer, W / WNx / poly-Si structure without a separate diffusion barrier film deposition process It is to provide a method for manufacturing a gate electrode of a semiconductor device that can be formed by the process of the process, the process is simple, diffusion prevention is made to improve the characteristics of the device to improve the process yield and the reliability of device operation.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 게이트전극 제조방법의 특징은,Features of the method for manufacturing a gate electrode of a semiconductor device according to the present invention for achieving the above object,
반도체기판상에 게이트 산화막을 형성하는 공정과,Forming a gate oxide film on the semiconductor substrate;
상기 게이트 산화막상에 다결정 실리콘막을 형성하는 공정과,Forming a polycrystalline silicon film on the gate oxide film;
상기 다결정 실리콘층상에 W층을 소정 두께 형성하는 공정과,Forming a predetermined thickness of the W layer on the polycrystalline silicon layer;
상기 W층 질소 플라즈마 처리하여 WNx층을 형성하는 공정과,Forming a WNx layer by treating the W layer with nitrogen plasma;
상기 WNx층 상에 W층을 형성하는 공정과,Forming a W layer on the WNx layer;
상기 W층과 WNx층 및 다결정 실리콘층을 순차적으로 게이트 패턴닝 마스크로 사진식각하여 게이트전극을 형성하는 공정을 구비함에 있다.And forming a gate electrode by sequentially etching the W layer, the WNx layer, and the polycrystalline silicon layer with a gate patterning mask.
이하, 본 발명에 따른 반도체소자의 게이트전극 제조방법에 관하여 상세히 설명한다.Hereinafter, a method of manufacturing a gate electrode of a semiconductor device according to the present invention will be described in detail.
먼저, 반도체기판상에 게이트 산화막과 다결정실리콘을 증착한 후, 자연산화막과 불순물 제거를 위한 세척 공정을 실시하고, 텅스텐 증착용 스퍼터링 챔버에서 제1W층을 30∼100Å 정도 두께로 증착한다. 여기서 상기 다결정 실리콘층 형성을 위한 소스 가스로는 SiH4, Si2H6또는 SiH2Cl2가스를 사용하며, 상기의 다결정 실리콘층은 PH3나 AsH3등의 가스를 환합 형성하여 P이나 As가 불순물로 포함된다. 또한 상기 다결정 실리콘층을 언도프트로 형성하고 후에 이온주입으로 도핑할 수도 있다.First, a gate oxide film and polysilicon are deposited on a semiconductor substrate, followed by a washing process for removing a native oxide film and impurities, and depositing a first W layer in a tungsten deposition sputtering chamber at a thickness of about 30 to 100 kW. Here, SiH 4 , Si 2 H 6, or SiH 2 Cl 2 gas is used as the source gas for forming the polycrystalline silicon layer, and the polycrystalline silicon layer is formed by combining a gas such as PH 3 or AsH 3 to form P or As. It is included as an impurity. The polycrystalline silicon layer may also be undoped and later doped with ion implantation.
또한 상기 제1W층은 스퍼터링 방법이나 WF6와 SiH4또는 H2가스를 사용하는 화학기상증착(Chemical Vapor Deposition; 이하 CVD라 칭함) 방법으로 형성할 수도 있다.In addition, the first W layer may be formed by a sputtering method or a chemical vapor deposition (CVD) method using WF 6 and SiH 4 or H 2 gas.
그다음 상기의 챔버에서 상기 제1W층을 1mTorr∼10Torr 질소 분위기에서, DC 나 Rf 또는 마이크로파등의 파워를 50∼1000W 파워로 질소 플라즈마 처리하면 30∼100Å 정도의 얇은 제1W층은 대부분 WNx막으로 바뀌게하고, 이 후 같은 챔버에서 300∼1000Å 정도 두께의 제2W층을 제1W층과 같은 방법으로 증착하여 게이트 전극의 증착 공정을 완료한다. 이때 상기 WNx막은 비정질 구조를 가지며 50Å이하의 얇은 두께에서도 텅스텐과 실리콘 사이의 우수한 확산방지막 성능을 나타내게 된다.Then, when the first W layer is 1mTorr to 10 Torr nitrogen atmosphere in the chamber, when the plasma of DC, Rf, or microwave is subjected to nitrogen plasma at 50 to 1000 W power, the thin 1W layer of about 30 to 100 kW is almost changed to WNx film. Subsequently, in the same chamber, a second W layer having a thickness of about 300 to 1000 mW is deposited in the same manner as the first W layer to complete the deposition process of the gate electrode. At this time, the WNx film has an amorphous structure and exhibits excellent diffusion barrier performance between tungsten and silicon even at a thin thickness of 50 Å or less.
그후, 상기 W층과 WNx층 및 다결정 실리콘층을 게이트 패터닝 마스크를 사용하여 순차적으로 패턴닝하여 게이트전극을 형성한다.Thereafter, the W layer, the WNx layer, and the polycrystalline silicon layer are sequentially patterned using a gate patterning mask to form a gate electrode.
상기와 같이 형성된 W/WNx/폴리-Si 구조의 워드라인은 면저항이 기존의 폴리사이드 구조의 워드라인에 비하여 1/5∼1/10 정도로 매우 적다.The word lines of the W / WNx / poly-Si structure formed as described above have very low sheet resistance as much as 1/5 to 1/10 of the word lines of the conventional polyside structure.
이상에서 설명한 바와 같이, 본 발명에 따른 W-폴리사이드 구조의 게이트전극을 구비하는 반도체소자의 제조방법은 얇은 W층을 질소 플라즈마 처리하여 확산 방지막인 WNx층을 형성하고, 연속적으로 W층을 형성하였으므로, 게이트전극의 면저항이 감소되어 소자의 동작 특성이 향상되고, 한번의 공정으로 W/WNx 막이 형성되므로 공정 스텝이 감소하고 제조 비용 및 시간이 절감할 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device having a gate electrode having a W-polyside structure according to the present invention, a thin W layer is subjected to nitrogen plasma treatment to form a WNx layer, which is a diffusion barrier, and a W layer is continuously formed. Since the sheet resistance of the gate electrode is reduced, the operation characteristics of the device are improved, and since the W / WNx film is formed in one step, the process step is reduced and manufacturing cost and time are reduced.
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| KR100393964B1 (en) * | 2000-12-18 | 2003-08-06 | 주식회사 하이닉스반도체 | Method of forming Gate of SRAM Device |
| KR100696763B1 (en) * | 2001-06-22 | 2007-03-19 | 주식회사 하이닉스반도체 | Forming method for gate electrode of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100393964B1 (en) * | 2000-12-18 | 2003-08-06 | 주식회사 하이닉스반도체 | Method of forming Gate of SRAM Device |
| KR100696763B1 (en) * | 2001-06-22 | 2007-03-19 | 주식회사 하이닉스반도체 | Forming method for gate electrode of semiconductor device |
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