KR19990005993A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
- Publication number
- KR19990005993A KR19990005993A KR1019970030215A KR19970030215A KR19990005993A KR 19990005993 A KR19990005993 A KR 19990005993A KR 1019970030215 A KR1019970030215 A KR 1019970030215A KR 19970030215 A KR19970030215 A KR 19970030215A KR 19990005993 A KR19990005993 A KR 19990005993A
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- tisi
- semiconductor device
- ticl
- forming
- metal wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
본 발명은 반도체 소자에서 금속과 반도체 기판 사이의 오믹 (ohmic) 콘택을 형성시키기 위해 사용되는 TiSi2를 ALE (Atomic Layer Epitaxy) CVD 방법으로 형성하는 것으로, ALE CVD 방법을 이용함으로서 두께조절이 용이하고 결함이 적은 TiSi2를 형성하여 반도체 소자의 신뢰성을 향상시키는 기술이다.The present invention is to form TiSi 2 , which is used to form an ohmic contact between a metal and a semiconductor substrate in a semiconductor device, by the ALE (Atomic Layer Epitaxy) CVD method. It is a technique of improving the reliability of a semiconductor device by forming TiSi 2 with few defects.
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게는 반도체 소자에서 금속과 반도체 기판 사이의 오믹 (ohmic) 콘택을 형성시키기 위해 사용되는 티타늄실리사이드 (TiSi2) 를 ALE (Atomic Layer Epitaxy) CVD 방법으로 형성하여 TiSi2의 조성과 두께를 조절하기에 용이하게 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a layer of titanium silicide (TiSi 2 ) used to form an ohmic contact between a metal and a semiconductor substrate in a semiconductor device. The present invention relates to a method for facilitating the composition and thickness of TiSi 2 by forming by CVD.
현재 사용되고 있는 TiSi2는 Si 기판 위에 이온주사방법에 의해 원하는 종류의 이온도핑을 실시하고, 그 상부에 적당한 두께의 Ti 박막을 증착한 다음 짧은 시간 동안 열처리 (RTP) 를 행하여 상호 확산시켜 형성한다. 그러나, RTP 공정의 특성상 확산에 의한 TiSi2형성시 정확한 두께 조절이 어려워 하나의 웨이퍼 내에 균일한 두께의 TiSi2를 형성하는 것이 어려운 문제점이 있으며, 또한 RTP 공정시 Ti 원소가 이온주입된 이온들과 반응을 일으킬 수 있는 문제점이 있다.TiSi 2 currently used is formed by ion doping of a desired kind on an Si substrate by an ion scanning method, depositing a Ti thin film of a suitable thickness on top thereof, and then performing heat treatment (RTP) for a short time to form a mutual diffusion. However, there is a difficult problem that the accurate thickness control during TiSi 2 formed by the nature of the diffusion of the RTP process difficult to form a uniform thickness within one wafer TiSi 2, also the Ti element when RTP process with an ion implanted ions There is a problem that can cause a reaction.
이러한 문제점들로 인해, 반도체 소자의 콘택저항이 불량해지고, 누설전류가 증가하여 반도체 소자의 전반적 특성을 열화시키는 문제점이 있다.Due to these problems, there is a problem in that the contact resistance of the semiconductor device is poor, and the leakage current increases to deteriorate the overall characteristics of the semiconductor device.
본 발명은 상기한 문제점을 해결하기 위한 것으로, 종래의 물리기상증착(PVD) 방법이나 화학기상증착 (CVD) 방법이 아닌 ALE CVD 방법을 이용하여 결함이 적고, 원하는 조성과 두께조절이 가능한 TiSi2를 형성시킴으로서, 종래의 RTP 공정을 생략할 수 있으며, 반도체 소자의 전반적인 특성을 향상시키는 방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above problems, TiSi 2 is less defects using the ALE CVD method than the conventional physical vapor deposition (PVD) method or chemical vapor deposition (CVD) method, the desired composition and thickness control is possible TiSi 2 It is possible to omit the conventional RTP process by forming the present invention, and an object thereof is to provide a method for improving overall characteristics of a semiconductor device.
도 1 내지 도 9 는 본 발명에 따른 ALE CVD 방법을 이용한 TiSi2형성방법을 도시한 공정도.1 to 9 are process charts showing a TiSi 2 formation method using the ALE CVD method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판, 12, 15, 18 : TiCl4, 13, 16 : SiH4, 14, 17 : TiSi2, 19 : H2가스, 20 : Ti, 박막11: semiconductor substrate, 12, 15, 18: TiCl 4 , 13, 16: SiH 4 , 14, 17: TiSi 2 , 19: H 2 gas, 20: Ti, thin film
상기한 목적을 달성하기 위해 본 발명은,The present invention to achieve the above object,
ALE CVD 방법을 이용하여 금속 배선을 형성하는 방법으로서,As a method of forming a metal wiring using the ALE CVD method,
반도체 기판 상부에 TiCl4를 흡착하는 단계와,Adsorbing TiCl 4 on the semiconductor substrate;
상기 TiCl4위에 SiH4를 흡착하여 TiSi2를 형성하는 단계와,Forming the TiSi 2 by attracting the SiH 4 on the TiCl 4,
상기 TiSi2상부에 TiCl4를 흡착하는 단계와,Adsorbing TiCl 4 on the TiSi 2 ;
상기 TiCl4위에 H2를 흡착하여 Ti 를 형성하는 단계를 포함하는 것을 특징으로 한다.Adsorbing H 2 on the TiCl 4 to form Ti.
본 발명에서 사용된 ALE CVD 방법은 소스, 퍼지가스 그리고 반응기체를 싸이클릭 펄스 (cyclic pu1se) 로 공급하여 싸이클릭-딘일층을 증착하는 방법으로서, 반도체 기판 표면에서 흡착과 탈착 메카니즘을 이용해 매우 얇은 박막 두께(10 Å 까지) 를 균일하게 조절할 수 있다. 이러한 ALE CVD 방법을 사용할 경우 단일층 증착에 의해 다원계 박막의 조성을 정밀히 제어할 수 있고, 박막 결함의 성장과 확산을 억제할 수 있다.The ALE CVD method used in the present invention is a method of depositing a cyclic dean layer by supplying a source, a purge gas, and a reactive gas in a cyclic pulse (cyclic pu1se). Thin film thickness (up to 10 microseconds) can be adjusted uniformly. When the ALE CVD method is used, the composition of the multi-element thin film can be precisely controlled by single layer deposition, and growth and diffusion of thin film defects can be suppressed.
이하에 첨부된 도면을 참조하여 본 발명에 따른 TiSi2형성방법을 설명한다.Hereinafter, a method of forming TiSi 2 according to the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 9 는 본 발명에 따른 ALE CVD 방법을 이용한 TiSi2형성방법을 도시한 공정순서도이다.1 to 9 are process flowcharts showing a TiSi 2 formation method using the ALE CVD method according to the present invention.
ALE CVD 방법으로 TiSi2를 형성하는 공정에서는, 소스가스로 TiCl4를 사용하고, 반응가스로서 사이레인 (SiH4) 을 사용한다.In the process of forming TiSi 2 by the ALE CVD method, TiCl 4 is used as the source gas and silane (SiH 4 ) is used as the reaction gas.
먼저, 도 1 에 도시한 바와 같이, 소스가스인 TiCl4(12) 를 0.1 초∼1 분간 10∼1000 sccm 의 유량만큼 한정적으로 공급하여 반도체 기판(11) 위에 흡착한다.First, as shown in FIG. 1, TiCl 4 (12), which is a source gas, is supplied at a flow rate of 10 to 1000 sccm for 0.1 seconds to 1 minute and adsorbed onto the semiconductor substrate 11.
그 다음 바로 아르곤 가스를 10∼1000 sccm 정도 흘려주어 소스퍼지를 0.1 초∼2분간 실시한다.Immediately after that, argon gas is flowed about 10 to 1000 sccm, and source purge is performed for 0.1 second to 2 minutes.
그 후, 0.1 초∼1 분간 반응가스를 10∼1000 sccm 정도 흘려주어 SiH4(13) 를 상기 TiCl4(12) 위에 흡착한다 (도 2 참조).Thereafter, the reaction gas is flowed about 10 to 1000 sccm for 0.1 second to 1 minute to adsorb SiH 4 (13) onto the TiCl 4 (12) (see FIG. 2).
이때, 아래와 반응식에 의한 반응을 일으켜 반도체 기판 위에는 TiSi2(14)가 형성된다. 여기서 반응기내의 전체 압력은 0.1∼5 Torr 정도를유지한다.At this time, TiSi 2 (14) is formed on the semiconductor substrate by causing a reaction according to the following reaction formula. Here, the total pressure in the reactor is maintained at about 0.1 to 5 Torr.
TiCl4(g) + 2SiH4(g) = TiSi2(s) + 4HCl (g) + 2H2(g)TiCl 4 (g) + 2SiH 4 (g) = TiSi 2 (s) + 4HCl (g) + 2H 2 (g)
그후, 반응기체와 부산물 (HCl) 을 아르곤 가스를 흘려주어 퍼지시킨다 (도 3 참조).The reactor and byproduct (HCl) are then purged by flowing argon gas (see FIG. 3).
도 4 내지 도 6 은 상기한 방법과 동일한 방법을 도시한 도면이므로 이에 대한 설명은 생략한다.4 to 6 illustrate the same method as the above method, and thus description thereof will be omitted.
상기와 같은 싸이클을 5∼2000 회 정도 반복하여 TiSi2두께를 10∼500 Å 정도까지 형성시킨 다음, 도 8 및 도 9 에 도시된 바와 같이, H2가스(19)를 TiCl4에 흡착시켜 아래와 같은 반응식에 의한 반응을 일으켜 Ti 박막(20)을 형성한다.By repeating the above cycle 5 to 2000 times to form a TiSi 2 thickness of about 10 to 500 kPa, as shown in Figures 8 and 9, by adsorbing the H 2 gas (19) to TiCl 4 The Ti thin film 20 is formed by reacting with the same reaction formula.
TiCl4(g) + 2H2(g) = Ti (s) + 4HCl (g)TiCl 4 (g) + 2H 2 (g) = Ti (s) + 4HCl (g)
상기와 같은 싸이클을 5∼2000 회 정도 반복하여 10-600 Å 두께의 Ti 를 형성시킨다.The above cycle is repeated 5 to 2000 times to form 10-600 mm 3 Ti.
상기와 같이 형성된 TiSi2박막은 두께 조절이 용이하고, 치밀하며, 결함이 적은 장점을 갖는다.The TiSi 2 thin film formed as described above has an advantage of easy thickness control, compactness, and low defects.
상기한 바와같이 본 발명에 따르면, ALE CVD 방법을 이용함으로써 두께 조절이 용이하고 결함이 적은 TiSi2를 형성하여 반도체 소자의 신뢰성을 향상시킬수 있으며, TiSi2와 금속확산방지막 형성공정이 한 반응기 내에서 가능하기 때문에, 종래의 RTP 공정시 문제시 되었던 공기에 의한 문제를 줄일 수 있다.As described above, according to the present invention, by using the ALE CVD method, it is possible to improve the reliability of the semiconductor device by forming the TiSi 2 , which is easy to control the thickness and has less defects, and the TiSi 2 and the metal diffusion barrier formation process are performed in one reactor. Since it is possible, it is possible to reduce the problem caused by air, which has been a problem in the conventional RTP process.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970030215A KR100248145B1 (en) | 1997-06-30 | 1997-06-30 | Process for forming metal wire of semiconductor device |
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| KR1019970030215A KR100248145B1 (en) | 1997-06-30 | 1997-06-30 | Process for forming metal wire of semiconductor device |
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| KR19990005993A true KR19990005993A (en) | 1999-01-25 |
| KR100248145B1 KR100248145B1 (en) | 2000-03-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100728942B1 (en) * | 2001-05-31 | 2007-06-15 | 주식회사 하이닉스반도체 | method of forming ohmic contact layer |
| KR20190042108A (en) * | 2016-09-15 | 2019-04-23 | 어플라이드 머티어리얼스, 인코포레이티드 | Contact integration and selective silicide formation methods |
-
1997
- 1997-06-30 KR KR1019970030215A patent/KR100248145B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100728942B1 (en) * | 2001-05-31 | 2007-06-15 | 주식회사 하이닉스반도체 | method of forming ohmic contact layer |
| KR20190042108A (en) * | 2016-09-15 | 2019-04-23 | 어플라이드 머티어리얼스, 인코포레이티드 | Contact integration and selective silicide formation methods |
| US10964544B2 (en) | 2016-09-15 | 2021-03-30 | Applied Materials, Inc. | Contact integration and selective silicide formation methods |
| KR20210064429A (en) * | 2016-09-15 | 2021-06-02 | 어플라이드 머티어리얼스, 인코포레이티드 | Contact integration and selective silicide formation methods |
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| Publication number | Publication date |
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| KR100248145B1 (en) | 2000-03-15 |
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