KR19990005643A - Signal processing device using two-stage Viterbi - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system using a DVD, and more particularly, to convert analog signals into digital signals, thereby eliminating errors in the signals, and processing analog signals such as waveform shaping of signals read from a disk to improve reliability. An analog signal processor 1000; A synchronization detector 2000 which detects a frame synchronization signal necessary for Viterbi decoding and outputs 1 when synchronization is detected; A Viterbi decoder 3000 for decoding the signal output from the analog signal processor 1000 in units of frames in accordance with frame synchronization and then outputting the signal; A digital signal processor 4000 which processes the signal output from the Viterbi decoder 3000 into a digital signal by performing error correction or the like, and extracts and uses only necessary information such as removing a synchronization signal or an error correction parity, etc. The present invention has the effect of reducing the error occurrence rate and improving the performance of the entire system.

Description

Signal processing device using two-stage Viterbi

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system using a DVD (Digital Video Disc), and in particular, decoding using a two-step Viterbi to convert an analog signal into a digital signal, thereby eliminating signal errors and increasing reliability. Relates to a device.

Conventionally, when converting an analog signal into a digital signal, a method of converting an input analog signal to a predetermined value when it is larger than a predetermined value is 1, and when it is smaller, is converted to 0.

As is well known, if the above method is used, the circuit is simple, but there is no error correction capability. Therefore, an incorrect value is output for an error occurring in an input signal and there is a problem in that the error cannot be corrected.

The present invention is to solve the above-mentioned conventional problems, in particular, by using a Viterbi decoding device which is a method of looking at a certain number of bits as a bundle and finding a transform bundle that is most similar to the entire bundle. In order to minimize the conversion error and reduce the Viterbi decoding, the values of the starting point and the ending point must be constant, and according to the DVD specification, at least two bits of consecutive zeros exist immediately after every frame synchronization signal. The present invention provides a signal processing apparatus using a two-stage Viterbi using a second 0 of a bit as a starting point and a first 0 of two consecutive bits of 0 as an end point immediately after a synchronization signal of a next frame.

In order to achieve the above object, a signal processing apparatus using the second step Viterbi of the present invention includes an analog signal processing unit for processing an analog signal such as waveform shaping of a signal read from a disk; A synchronization detector for detecting a frame synchronization signal necessary for Viterbi decoding and outputting a 1 when synchronization is detected; A Viterbi decoding unit which decodes the signal output from the analog signal processing unit in frame units in accordance with frame synchronization and outputs the decoded unit; And a digital signal processing unit for processing the signal output from the Viterbi decoding unit as a digital signal by performing error correction or the like, and extracting and using only necessary information such as removing a synchronization signal or an error correction parity. .

1 is a block diagram showing a system using a signal processing apparatus using a two-step Viterbi according to an embodiment of the present invention;

2 is a block diagram showing a signal processing apparatus using a two-stage Viterbi according to an embodiment of the present invention;

3 is a block diagram showing a calculation unit in a signal processing apparatus using a two-stage Viterbi according to an embodiment of the present invention;

4 is a block diagram illustrating a first memory unit in a signal processing apparatus using a two-stage Viterbi according to an embodiment of the present invention;

5 is a block diagram illustrating a second memory unit in a signal processing apparatus using a two-stage Viterbi according to an embodiment of the present invention;

6 is a block diagram illustrating a decoding unit in a signal processing apparatus using a two-step Viterbi according to an embodiment of the present invention;

7 is a block diagram illustrating a third memory unit in a signal processing apparatus using a two-stage Viterbi according to an embodiment of the present invention;

8 is a result diagram illustrating a result of a signal processing apparatus using a two-stage Viterbi according to an embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

1000: analog signal processing unit 2000: synchronization detection unit

3000: Viterbi decoding unit 3100: A / D conversion unit

3200: calculation unit 3201: first switching unit

3202, first distance calculator 3203, third switch

3204: first adding unit 3205: first temporary storage unit

3206: second distance calculation unit 3207: fourth switching unit

3208: second addition unit 3209: second temporary storage unit

3210: first comparator 3211: fifth switch

3212: second switching unit 3213: third distance calculating unit

3214: third adder 3215: third temporary storage

3216: fourth distance calculator 3217: fourth adder

3218: fourth temporary storage unit 3219: second comparison unit

3220: sixth switching unit 3300: first memory unit

3301: seventh switching unit 3302: first converting unit

3303: first ram 3304: second ram

3305: eighth switching unit 3400: second memory unit

3401: 9th switching unit 3402: 2nd conversion unit

3403: third ram 3404: fourth ram

3405: tenth switching unit 3500: decryption unit

3501: eleventh switching unit 3502: delay unit

3503: 12th switching unit 3600: 3rd memory unit

3601: 13th switching unit 3602: 3rd conversion unit

3603: fifth ram 3604: sixth ram

3605: 14th switching unit 3700: control unit

Hereinafter, the above-described contents will be described in detail through an embodiment according to the present invention.

As shown in FIG. 1, the analog signal processor 1000 first outputs a signal read from a disc (not shown) by analog processing, and the synchronization detector 2000 outputs the signal from the analog signal processor 1000. The frame sync signal required to decode the received signal is output, and the Viterbi decoder 3000 receives the signal output from the sync detector 2000 and outputs it in units of frames, and the digital signal processor 4000. In the present embodiment, the signal output from the Viterbi decoding unit 3000 is digitally processed to extract and use only necessary information, thereby configuring the present embodiment.

In addition, as shown in FIG. 2, the Viterbi decoding unit 3000 first converts the input analog signal into a digital signal in the A / D converter 3100 and outputs the digital signal, and in the calculator 3200, the A signal. Receives the digital signal output from the / D converter 3100, calculates a difference between the input signal and four possible values, and outputs a path having the smallest difference, that is, the most similar value, and the first memory. The unit 3300 receives and outputs the signal output from the calculation unit 3200, and the second memory unit 3400 transmits the signal output from the calculation unit 3200 to the first memory unit 3300. Simultaneously input and output the data, and the decryption unit 3500 decodes the signals output from the first and second memories 3300 and 3400 to correct the error and outputs the data. The signals converted and output from the first and second memory units 3300 and 3400 are again In this case, the controller 3700 outputs an end signal at the first bit time and a start signal at the second bit time so that the calculator 3200 and the decoder 3500 may perform preprocessing and postprocessing. By configuring the present embodiment.

In addition, as shown in FIG. 3, the calculation unit 3200 selects one of two signals input from the first switching unit 3201, outputs -2 in the initialization process, and outputs 0 in other cases. The second switching unit 3212 outputs 0 during the initialization process, and outputs 2 in other cases.

The first distance calculator 3202 calculates and outputs a difference between the two input values, and the third switch 3203 receives the signal output from the first distance calculator 3202 and terminates the received signal. In the process, 0 is output. Otherwise, the signal output from the first distance calculator 3202 is output as it is, and the first adder 3204 adds two input signals and outputs the first temporary storage unit ( In step 3205, the signal output from the first adder 3204 is input to record the result in a 1-bit memory and output the result.

In addition, the second distance calculator 3206 calculates and outputs the distance between the two input values, and the fourth switch 3207 receives the signal output from the second distance calculator 3206 to initialize the process. Outputs 4, otherwise the output of the second distance calculator 3206 is output as it is, and the second adder 3208 adds the two input signals and outputs the second temporary storage 3209. In the following example, the signal output from the second adder 3208 is written into a 1-bit memory, and the result is output.

In addition, the first comparator 3210 outputs 1 when the value of the first temporary storage unit 3205 is greater than the value of the second temporary storage unit 3209, otherwise outputs 0, and fifth switching. The unit 3211 outputs the value of the second temporary storage unit 3209 to the first adding unit 3204 and the second adding unit 3208 if the output of the first comparison unit 3210 is 1; The first temporary storage unit 3205 outputs the values of the first temporary storage unit 3205 to the first adding unit 3204 and the second adding unit 3208.

On the other hand, the third distance calculator 3213 calculates and outputs the distance between the two input values, and the third adder 3214 adds and outputs two input signals, and in the third temporary storage unit 3215, 1 The result of the third adder 3214 is recorded and output to the bit memory, and the fourth distance calculator 3216 calculates and outputs the distance between the two input values, and the fourth adder 3217 When the two input signals are added and output, the fourth temporary storage unit 3218 records and outputs the result to the 1-bit memory.

In addition, the second comparator 3319 outputs 1 when the value of the third temporary storage part 3215 is greater than the value of the fourth temporary storage part 3218, and if it is 0, the sixth switching part ( 3220 outputs the value of the third temporary storage part 3215 to the third adding part 3214 and the fourth adding part 3217 if the output from the second comparator 3319 is 1; The value of the 4th temporary storage part 3218 is output to the 3rd adding part 3215 and the 4th adding part 3218.

In addition, as shown in FIG. 4, the first memory unit 3300 first selects and outputs a location in which the input signal is to be stored in the seventh switching unit 3301, and the seventh switching unit in the first conversion unit 3302. The signal output from the unit 3301 may be converted and output. The first RAM 3303 receives and stores a signal when the signal output from the seventh switching unit 3301 is 0, and stores the second RAM. In operation 3304, when the signal output from the seventh switching unit 3301 is stored in the first RAM 3303, the seventh switching unit 3301 outputs a signal previously stored in advance.

Then, the eighth switching unit 3305 receives and outputs the signal output from the second RAM 3304.

In addition, as shown in FIG. 5, the second memory 3400 first selects and outputs a location in which the input signal is to be stored in the ninth switching unit 3401, and the second conversion unit 3402 converts the ninth switching. The signal output from the unit 3401 may be converted and output. The third RAM 3403 receives and stores a signal when the signal output from the ninth switching unit 3401 is 0, and stores the fourth RAM. In operation 3404, when the signal output from the ninth switching unit 3401 is stored in the third RAM 3403, the ninth switching unit 3401 outputs a signal previously stored in advance.

Then, the tenth switching unit 3405 receives and outputs a signal output from the fourth RAM 3404.

In addition, as shown in FIG. 6, the decoding unit 3500 first outputs an initialization signal −1 from the eleventh switching unit 3501, and outputs from the eleventh switching unit 3501 from the delay unit 3502. Receives a 1-bit signal and outputs the delayed signal once, and the twelfth switching unit 3503 receives the signal output from the delay unit 3502 and outputs a positive value if the delay value is 1; If it is 0, it outputs negative value.

In addition, as shown in FIG. 7, when the third memory unit 3600 selects and outputs a location in which the input signal is to be stored in the thirteenth switching unit 3601, the third conversion unit 3602 has the thirteenth switching unit. The signal output from the 3603 is converted to be adjusted and output. The fifth RAM 3603 receives and stores a signal when the signal output from the thirteenth switching unit 3601 is 0, and stores the signal. In operation 3604, when the signal output from the thirteenth switching unit 3601 is stored in the fifth RAM 3603, the thirteenth switching unit 3601 outputs a signal previously stored.

Then, the fourteenth switching unit 3605 receives and outputs a signal output from the sixth RAM 3604.

Hereinafter, the operation of the decryption apparatus using the two-step Viterbi configured as described above is as follows.

When the analog signal processor 1000 outputs a signal read from a disk (not shown) by analog signal processing such as waveform shaping, the signal output from the analog signal processor 1000 is input from the sync detector 2000. Detects the frame sync signal needed for non-decryption and outputs 1 when sync is detected.

Then, the signal output from the synchronization detector 2000 is inputted from the Viterbi decoder 3000, the output signal of the analog signal processor 1000 decodes the frame unit in accordance with frame synchronization, and then outputs the digital signal. The processor 4000 receives the output signal decoded in units of frames by the Viterbi decoder 3000 and processes it digitally through error correction and the like, and removes a synchronization signal or an error correction parity, and only needs information. Extract it and use it.

In addition, the Viterbi decoder 3000 converts the analog signal input from the A / D converter 3100 into digital information and outputs the converted digital signal to the calculator 3200. ) And calculate the difference between the input signal and the four possible values (there are four possible values since the current value and the past value can each be 1 or 0), so that the smallest difference, Outputs 1, 0 paths for each value (when the current value is 1 and 0).

When the current value is 1, the value is output to the first memory unit 3300, and when the current value is 0, the value is output to the second memory unit 3400, which is an output signal of the controller 3700. Preprocessing and postprocessing are performed in accordance with the signal and the end signal.

Then, the signal output from the calculator 3200 is input from the first and second memory units 3300 and 3400, and is composed of two RAMs of 1488 bits and a selection signal. Two RAMs alternately output signals according to odd / even signals so that the decryption unit 3500 can operate continuously.

In addition, the decoder 3500 traces back the path information recorded by the calculator 3200, searches a path of 1488 bits of one frame, and outputs paths 1 and 0 for every bit of error correction, and the decoder After the error is corrected at 3500, the output 1, 0 signal is inputted from the third memory unit 3600, and the order of bits is changed again in the first and second memory units 3300 and 3400. Inverted and output in the original order.

In addition, when the calculation unit 3200 calculates and outputs the distance according to the values of the two signals input from the first distance calculation unit 3202, the third switching unit outputs the signal output from the first distance calculation unit 3202. In response to the input from the unit 3203, 0 is output in the termination process, and otherwise, the value of the first distance calculator 3202 is output as it is.

Then, when the first adder 3204 adds the signal output from the third switching unit 3203 and the accumulated signal, the first adder 3204 stores the first temporary storage unit 3205.

In addition, when one of the signals input from the first switching unit 3201 is selected and outputted, the second distance calculating unit 3206 receives an input signal and a signal output from the first switching unit 3201 and receives the input signal. The distance between the two values is calculated and outputted. The signal output from the second distance calculator 3206 is inputted by the fourth switching unit 3207, and 4 is output in the termination process. The value of the distance calculator 3206 is output as it is.

Then, the signal added from the fourth switcher 3207 and the accumulated signal are added to the second adder 3208 and output, and the signal output from the second adder 3208 is temporarily stored. It is input from the unit 3209 and stored.

In this way, the first temporary storage unit 3205 receives a signal output from the first temporary storage unit 3205 and a signal output from the second temporary storage unit 3209 from the first comparison unit 3210, and thus the value of the first temporary storage unit 3205 is changed. When the value is greater than the value of the second temporary storage unit 3209, 1 is output. Otherwise, a value generated by outputting 0 becomes a negative unit output value.

In addition, when the signal output from the first comparator 3210 is input from the fifth switch 3211 and the output value is 1, the value of the second temporary storage part 3209 and the first adder 3204 and the second value are added. The second adder 3208 outputs the data to the first adder 3204 and the second adder 3208.

When the third distance calculator 3213 calculates and outputs the distance between the two input values, the third adder 3214 outputs the accumulated value with the signal output from the third distance calculator 3213. The result of comparison is output, and the signal output from the third adder 3214 is received from the third temporary storage part 3215 and stored.

In addition, when the second switching unit 3212 outputs 0 during the initialization process and 2 otherwise, the second switching unit 3212 outputs 2, and the fourth distance calculator 3216 outputs an input signal and a signal output from the second switching unit 3212. The input unit calculates and outputs a distance between two input values, and receives a signal output from the fourth distance calculator 3216 from the fourth temporary storage unit 3218.

Then, the signal output from the third temporary storage unit 3215 and the signal output from the fourth temporary storage unit 3218 are inputted from the second comparator 3213 to obtain a value of the third temporary storage unit 3215. When the value is greater than the value of the fourth temporary storage part 3218, a value of 1 is output. Otherwise, a value generated by outputting 0 becomes an output value of the positive part.

In addition, when the signal output from the second comparator 3213 is input from the sixth switching unit 3220, the value of the third temporary storage unit 3215 is added to the third adder 3214 and the fourth adder. And outputs the values of the fourth temporary storage part 3218 to the third adding part 3214 and the fourth adding part 3217.

In addition, the first memory unit 3300 receives the negative unit signal output from the calculator 3200 by the seventh switching unit 3301 and selects and outputs a place where the input signal is to be stored. In operation 3302, the signal output from the seventh switching unit 3301 is converted and output.

For example, when the signal output from the seventh switching unit 3301 is stored in the first RAM 3303, the signal stored in the second RAM 3304 is output to the eighth switching unit 3305. When the signal output from the seventh switching unit 3301 is stored in the second RAM 3304, the signal stored in the first RAM 3303 is output to the eighth switching unit 3305.

In addition, the second memory unit 3400 receives the positive part signal output from the calculator 3200 from the ninth switching part 3401 and selects and outputs a location where the input signal is to be stored. In operation 3402, the signal output from the ninth switching unit 3401 may be converted and output.

For example, when the signal output from the ninth switching unit 3401 is stored in the third RAM 3403, the signal stored in the fourth RAM 3404 is output to the tenth switching unit 3405. If the signal output from the ninth switch 3401 is stored in the fourth RAM 3404, the signal stored in the third RAM 3403 is output to the tenth switch 3405.

In addition, the decoding unit 3500 outputs the initialization signal -1 from the eleventh switching unit 3501, and the delay unit 3502 receives the 1-bit signal output from the eleventh switching unit 3501 once. After outputting the delay, the signal output from the first memory unit 3300 and the second memory unit 3400 and the signal output from the delay unit 3502 are simultaneously received by the twelfth switching unit 3503. If the delay value of the signal output from the delay unit 3502 is 1, the value of the positive part is output, and if the delay value is 0, the negative part value is output.

In addition, the third memory unit 3600 receives a signal output from the decryption unit 3500 and a signal output from the control unit 3700 from the thirteenth switching unit 3601, and selects and outputs a location where an input signal is to be stored. In this case, the third converter 3602 controls the signal output from the thirteenth switch 3601 to be converted and output.

For example, when the signal output from the thirteenth switching unit 3601 is stored in the fifth RAM 3603, the signal stored in the sixth RAM 3604 is output to the fourteenth switching unit 3605. When the signal output from the thirteenth switching unit 3601 is stored in the sixth RAM 3604, the signal stored in the fifth RAM 3603 is output to the fourteenth switching unit 3605.

On the other hand, the result of the error decoding apparatus using the two-stage Viterbi of the present invention, as shown in Figure 8, the horizontal axis is the signal-to-noise ratio, the vertical axis is the error rate, the solid line is the result of the conversion method using the conventional method, the dotted line Is the result of using the Viterbi decryption section.

As described above, the signal processing apparatus using the second-stage Viterbi of the present invention performs an analog signal processing such as waveform shaping on a signal read from the disk, and then detects a frame sync signal required for Viterbi decoding by the sync detection unit, When the analog signal processed signal is decoded in units of frames in accordance with frame synchronization, the Viterbi decoder decodes the synchronization signal, error correction parity, etc., and extracts only necessary information. The incidence rate is reduced, and there is an effect that can improve the performance of the entire system.

Claims (7)

An analog signal processor for processing analog signals, such as waveform shaping, of a signal read from the disk; A synchronization detector for detecting a frame synchronization signal necessary for Viterbi decoding and outputting a 1 when synchronization is detected; A Viterbi decoding unit which decodes the signal output from the analog signal processing unit in frame units in accordance with frame synchronization and outputs the decoded unit; And a digital signal processing unit for processing the signal output from the Viterbi decoding unit as a digital signal by performing error correction or the like, and extracting and using only necessary information such as removing a synchronization signal or an error correction parity. Signal processing device using two-stage Viterbi. The apparatus of claim 1, wherein the Viterbi decoding unit comprises: an A / D converter converting an input analog signal into a digital signal and outputting the digital signal; A calculator which receives a digital signal output from the A / D converter and calculates a difference between the input signal and four possible values, and outputs a path having the smallest difference, that is, the most similar value; A first memory unit configured to receive and output a signal output from the calculator; A second memory unit for receiving and outputting a signal output from the calculator simultaneously with the first memory unit; A decoding unit for decoding the signals output from the first and second memory units to correct an error and output the corrected error; A third memory unit which converts the signal converted and output from the first and second memory units into an output state by converting the signal output through the decryption unit again; Signal processing using a two-stage Viterbi, characterized in that it comprises a control unit for outputting the end signal in the first bit time and the start signal in the second bit time to indicate the time to the pre-processing and post-processing unit Device. 3. The apparatus of claim 2, wherein the calculation unit comprises: a first switching unit which selects one of two input signals and outputs -2 in an initialization process, and outputs 0 in other cases; A second switching unit which outputs 0 in the initialization process and outputs 2 in other cases; A first distance calculator for calculating and outputting a difference between two input values; A third switching unit for receiving a signal output from the first distance calculator and outputting zero in a termination process, and otherwise outputting the signal output from the first distance calculator; A first adder for adding and outputting two input signals; A first temporary storage unit for receiving a signal output from the first adder and recording and outputting a result to a 1-bit memory; A second distance calculator for calculating a distance between two input values and outputting the distance; A fourth switching unit for receiving a signal output from the second distance calculating unit and outputting 4 in an initialization process, and otherwise outputting the output of the second distance calculating unit as it is; A second adder for adding and outputting two input signals; A second temporary storage unit for recording and outputting a result of the signal output from the second adder into a 1-bit memory; A first comparing unit which outputs 1 when the value of the first temporary storage unit is greater than the value of the second temporary storage unit, and outputs 0 otherwise; Outputting the value of the second temporary storage unit to the first adding unit and the second adding unit if the output of the first comparing unit is 1; otherwise, outputting the value of the first temporary storage unit to the first adding unit and the second adding unit. 5 switching section; A third distance calculator configured to calculate and output a distance between two input values; A third adder for adding and outputting two input signals; A third temporary storage unit for recording and outputting the result of the third adding unit into a 1-bit memory; A fourth distance calculator configured to calculate and output a distance between two input values; A fourth adder for adding and outputting two input signals; A fourth temporary storage unit for recording and outputting the result into the 1-bit memory; A second comparing unit which outputs 1 when the value of the third temporary storage unit is greater than the value of the fourth temporary storage unit, and outputs 0 otherwise; If the output from the second comparison unit is 1, the value of the third temporary storage unit is output to the third adding unit and the fourth adding unit, otherwise the value of the fourth temporary storage unit is output to the third adding unit and the fourth adding unit. Signal processing field device using a two-stage Viterbi characterized in that it comprises a sixth switching unit. 3. The apparatus of claim 2, wherein the first memory unit comprises: a seventh switching unit for selecting and outputting a location where an input signal is to be stored; A first converter configured to convert the signal output from the seventh switch and output the converted signal; A first RAM configured to receive and store the output signal when the signal output from the seventh switching unit is 0; A second RAM for outputting a signal previously stored in the seventh switching unit when the signal output from the seventh switching unit is stored in the first RAM; And a eighth switching unit configured to receive and output a signal output from the second RAM. The display apparatus of claim 2, wherein the second memory unit comprises: a ninth switching unit for selecting and outputting a location where an input signal is to be stored; A second conversion unit configured to convert the signal output from the ninth switching unit and output the converted signal; A third RAM configured to receive and store a signal when the signal output from the ninth switching unit is 0; A fourth RAM for outputting a signal previously stored in the ninth switching unit when the signal output from the ninth switching unit is stored in the third RAM; And a tenth switching unit configured to receive and output a signal output from the fourth RAM. The display device of claim 2, wherein the decryption unit comprises: an eleventh switching unit configured to output an initialization signal −1; A delay unit for receiving a 1-bit signal output from the eleventh switching unit and outputting a delay once; Signal processing using a two-stage Viterbi, characterized in that it comprises a twelfth switching unit for receiving the signal output from the delay unit outputs a positive value when the delay value is 1, and outputs a negative value when the delay value is 0 Device. 3. The apparatus of claim 2, wherein the third memory unit comprises: a thirteenth switching unit for selecting and outputting a location where an input signal is to be stored; A third converter configured to convert the signal output from the thirteenth switch and output the converted signal; A fifth RAM for receiving and storing a signal when the signal output from the thirteenth switching unit is 0; A sixth RAM for outputting a signal previously stored in the thirteenth switching unit when the signal output from the thirteenth switching unit is stored in the fifth RAM; And a fourteenth switching unit configured to receive and output a signal output from the sixth RAM.