KR19990004932A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19990004932A KR19990004932A KR1019970029092A KR19970029092A KR19990004932A KR 19990004932 A KR19990004932 A KR 19990004932A KR 1019970029092 A KR1019970029092 A KR 1019970029092A KR 19970029092 A KR19970029092 A KR 19970029092A KR 19990004932 A KR19990004932 A KR 19990004932A
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- film
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- insulating film
- nitride film
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 20
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 9
- -1 oxygen ions Chemical class 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술 분야1. The technical field to which the invention described in the claims belongs
반도체 제조 분야에 관한 것임.Regarding the field of semiconductor manufacturing.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
저농도 도핑 드레인 구조를 갖는 반도체 장치의 게이트 전극 측벽에 산화막 및 질화막으로 이루어지는 스페이서로 인한 콘택홀 면적의 감소를 줄일 수 있는 반도체 장치 제조 방법을 제공한다.Provided is a method of manufacturing a semiconductor device capable of reducing a decrease in contact hole area due to a spacer made of an oxide film and a nitride film on a sidewall of a gate electrode of a semiconductor device having a lightly doped drain structure.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
절연막 및 텅스텐실리사이드막으로 게이트전극 패턴의 일부를 형성하고, 절연막 및 텅스텐실리사이드막을 통하여 하부의 게이트 전극을 이루는 폴리실리콘막에 산소를 이온 주입하는데, 일부 형성된 게이트 전극 패턴의 측벽에는 산소 이온이 주입되지 않도록하여 이후의 질화막 형성 공정에서 게이트 전극의 측벽을 제외한 질화막 하부에 산화막을 형성한다.A portion of the gate electrode pattern is formed of the insulating film and the tungsten silicide film, and oxygen is ion implanted into the polysilicon film forming the lower gate electrode through the insulating film and the tungsten silicide film. In the subsequent nitride film forming process, an oxide film is formed below the nitride film except for the sidewall of the gate electrode.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치 제조 공정에 이용됨Used in semiconductor device manufacturing process
Description
본 발명은 일반적으로 반도체 장치 제조 방법에 관한 것으로 특히, 저농도 도핑 드레인 구조를 갖는 반도체 장치의 콘택홀 면적을 증가시킬 수 있는 반도체 장치 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of increasing the contact hole area of a semiconductor device having a low concentration doped drain structure.
이하, 첨부된 도면을 참조하여 종래 기술의 문제점을 설명한다.Hereinafter, the problems of the prior art will be described with reference to the accompanying drawings.
도1에 도시한 바와 같이 반도체 기판(10) 상에 소자분리막(11)을 형성한 후 게이트 절연막(12)을 형성한다. 다음으로 폴리실리콘막(13) 및 텅스텐실리사이드막(14)으로 게이트 전극을 형성한 후 상기 게이트 전극에 마스크 절연막(15)을 형성한다. 다음으로 산화막(16)을 성장하고 불순물을 이온 주입하여 저농도 도핑 드레인(lightly doped drain) 영역(17)을 형성한 다음 화학 기상 증착법으로 균일한 두께의 질화막(18)을 형성한다. 이어서 상기 질화막(18) 상에 층간절연막(19)을 형성한 후 상기 층간절연막(19), 질화막(18) 및 산화막(16)을 선택적으로 식각하여 콘택홀을 형성한다.As shown in FIG. 1, after the device isolation layer 11 is formed on the semiconductor substrate 10, the gate insulating layer 12 is formed. Next, after forming a gate electrode with the polysilicon film 13 and the tungsten silicide film 14, a mask insulating film 15 is formed on the gate electrode. Next, the oxide film 16 is grown and impurities are ion implanted to form a lightly doped drain region 17, and then a nitride film 18 having a uniform thickness is formed by chemical vapor deposition. Subsequently, after the interlayer insulating film 19 is formed on the nitride film 18, the interlayer insulating film 19, the nitride film 18, and the oxide film 16 are selectively etched to form contact holes.
상기 질화막(18) 하부층의 산화막(16)은 질화막 스페이서가 디바이스의 신뢰성 저하를 감소시키기 위한 위한 완충막의 역할을 한다. 그러나, 게이트 측벽에 스페이서로 형성되는 산화막은 그 폭(a) 만큼 콘택홀 면적을 감소시켜 콘택홀 폭(b)을 줄이기 때문에 접촉 저항을 증가시키는 단점이 있다.The oxide film 16 of the lower layer of the nitride film 18 serves as a buffer for the nitride film spacer to reduce the reliability degradation of the device. However, an oxide film formed as a spacer on the gate sidewall has a disadvantage in that the contact resistance is increased because the contact hole area is reduced by the width a to reduce the contact hole width b.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 저농도 도핑 드레인 구조를 갖는 반도체 장치의 콘택홀의 면적을 증가시킬 수 있는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of increasing the area of a contact hole of a semiconductor device having a lightly doped drain structure.
도1은 종래 기술에 따른 저농도 도핑 드레인 구조를 갖는 반도체 장치의 콘택홀 형성 단면도.1 is a cross-sectional view of contact hole formation of a semiconductor device having a lightly doped drain structure according to the prior art;
도2a 내지 도2d는 본 발명의 일실시예에 따른 저농도 도핑 드레인 구조를 갖는 반도체 장치의 콘택홀 형성 공정 단면도.2A to 2D are cross-sectional views of a contact hole forming process of a semiconductor device having a lightly doped drain structure according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing
10, 20: 반도체 기판11, 21: 소자분리막10, 20: semiconductor substrate 11, 21: device isolation film
12, 22: 게이트 절연막13, 23: 폴리실리콘막12, 22: gate insulating film 13, 23: polysilicon film
14, 24: 텅스텐실리사이드막15, 25: 마스크 절연막14, 24: tungsten silicide film 15, 25: mask insulating film
16, 28: 산화막17, 26: 저농도 도핑 드레인 영역16, 28: oxide film 17, 26: low concentration doped drain region
18, 27: 질화막19, 29: 층간절연막18, 27: nitride film 19, 29: interlayer insulating film
상기 목적을 달성하기 위한 본 발명은 반도체 장치 제조 방법에 있어서, 소정의 하부층이 형성된 반도체 기판 위에 게이트 절연막, 폴리실리콘막 및 텅스텐실리사이드막, 절연막 차례로 형성하는 제1단계; 상기 텅스텐실리사이드막 및 절연막을 선택적으로 식각하여 게이트 전극 패턴의 일부를 형성하는 제2단계; 상기 절연막 및 텅스텐실리사이드막을 통하여 상기 폴리실리콘막에 산소 이온을 주입하는 제3단계; 상기 폴리실리콘막 및 게이트 절연막을 선택적으로 식각하여 게이트 전극을 형성하는 제4단계; 상기 게이트 전극을 이온주입 방지막으로 이온 주입을 실시하여 저농도 불순물 영역을 형성하는 제5단계; 상기 제5단계가 완료된 반도체 기판 상부에 질화막을 증착하며 질화막의 증착 과정에서 게이트 전극의 측벽에 형성된 질화막을 제외한 나머지 질화막의 하층부분에 산화막을 형성하는 제6단계; 상기 제6단계가 완료된 반도체 기판 상부에 층간절연막을 형성하는 제7단계; 및 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 제8단계를 포함하여 이루어진다.In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: a first step of sequentially forming a gate insulating film, a polysilicon film, a tungsten silicide film, and an insulating film on a semiconductor substrate on which a predetermined lower layer is formed; Selectively etching the tungsten silicide layer and the insulating layer to form part of a gate electrode pattern; Injecting oxygen ions into the polysilicon film through the insulating film and the tungsten silicide film; Selectively etching the polysilicon film and the gate insulating film to form a gate electrode; A fifth step of implanting the gate electrode into the ion implantation prevention layer to form a low concentration impurity region; A sixth step of depositing a nitride film on the semiconductor substrate on which the fifth step is completed and forming an oxide film on the lower portion of the nitride film except for the nitride film formed on the sidewall of the gate electrode during the deposition of the nitride film; A seventh step of forming an interlayer insulating film on the semiconductor substrate on which the sixth step is completed; And an eighth step of selectively etching the interlayer insulating layer to form contact holes.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 살펴본다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도2a에 도시한 바와 같이 반도체 기판(20) 상에 소자분리막(21), 게이트 절연막(22), 폴리실리콘막(23) 및 텅스텐실리사이드막(24) 및 마스크 절연막(25) 차례로 형성한 후 상기 절연막(25) 및 텅스텐실리사이드막(24)을 선택적으로 식각하여 게이트 전극 패턴을 형성한 다음, 상기 절연막(25) 및 텅스텐실리사이드막(24)을 통하여 상기 폴리실리콘막(23)에 산소 이온을 주입한다. 이때 경사도 0。로 산소 이온을 주입하여 게이트 전극의 측면에는 산소 이온이 주입되지 않도록 한다.First, as shown in FIG. 2A, a device isolation film 21, a gate insulating film 22, a polysilicon film 23, a tungsten silicide film 24, and a mask insulating film 25 are sequentially formed on the semiconductor substrate 20. Thereafter, the insulating film 25 and the tungsten silicide film 24 are selectively etched to form a gate electrode pattern, and then oxygen ions are formed in the polysilicon film 23 through the insulating film 25 and the tungsten silicide film 24. Inject At this time, oxygen ions are implanted at an inclination of 0 ° so that oxygen ions are not implanted into the side of the gate electrode.
다음으로, 도2b에 도시한 바와 같이, 상기 폴리실리콘막(23) 및 게이트 절연막(22)을 선택적으로 식각하여 게이트 전극을 형성하고 불순물 이온주입을 실시하여 저농도 도핑 드레인 영역(26)을 형성한다.Next, as shown in FIG. 2B, the polysilicon film 23 and the gate insulating film 22 are selectively etched to form a gate electrode, and impurity ion implantation is performed to form a low concentration doped drain region 26. .
다음으로, 도2c에 도시한 바와 같이 전체 구조에 700 내지 900 ℃의 온도 범위에서 질화막(27)을 증착하여 질화막의 하층 부분에만 산화막(28)을 형성한다.Next, as shown in FIG. 2C, the nitride film 27 is deposited over the entire structure in the temperature range of 700 to 900 ° C. to form the oxide film 28 only in the lower portion of the nitride film.
다음으로, 도2d에 도시한 바와 같이 SiO2, PSG(phospho-silicate glass), BPSG(borophospo-silicate glass) 등으로 층간절연막(29)을 형성한 후 선택적으로 식각하여 콘택홀을 형성한다. 도시한 바와 같이 게이트 전극의 측벽에 산화막이 형성되지 않아 콘택홀의 폭(b′)이 증가하여 접촉 저항을 감소시킬 수 있다.Next, as shown in FIG. 2D, an interlayer insulating layer 29 is formed of SiO 2 , phospho-silicate glass (PSG), borophospo-silicate glass (BPSG), or the like, and then selectively etched to form a contact hole. As shown in the drawing, the oxide film is not formed on the sidewall of the gate electrode, thereby increasing the width b ′ of the contact hole, thereby reducing the contact resistance.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 콘택홀 면적의 감소를 방지하여 접촉 저항이 증가에 따른 소자의 특성 저하를 억제할 수 있다.The present invention made as described above can prevent the reduction of the contact hole area to suppress the deterioration of the characteristics of the device as the contact resistance increases.
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| KR20010063268A (en) * | 1999-12-22 | 2001-07-09 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device |
| KR100420119B1 (en) * | 2001-05-04 | 2004-03-02 | 삼성전자주식회사 | Semiconductor device having LDD-type source/drain regions and fabrication method thereof |
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| JPS6370574A (en) * | 1986-09-12 | 1988-03-30 | Nec Corp | Manufacture of mis type field-effect transistor |
| JPH02125449A (en) * | 1988-06-29 | 1990-05-14 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH04159725A (en) * | 1990-10-23 | 1992-06-02 | Nec Corp | Manufacture of semiconductor device |
| KR950000151B1 (en) * | 1992-03-07 | 1995-01-10 | 재단법인 한국전자통신연구소 | Manufacturing method of semiconductor device of it ldd structre |
| KR100281268B1 (en) * | 1994-05-20 | 2001-03-02 | 김영환 | Method of forming a connection device for a semiconductor device |
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| KR20010063268A (en) * | 1999-12-22 | 2001-07-09 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device |
| KR100420119B1 (en) * | 2001-05-04 | 2004-03-02 | 삼성전자주식회사 | Semiconductor device having LDD-type source/drain regions and fabrication method thereof |
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