KR19990004550A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19990004550A KR19990004550A KR1019970028677A KR19970028677A KR19990004550A KR 19990004550 A KR19990004550 A KR 19990004550A KR 1019970028677 A KR1019970028677 A KR 1019970028677A KR 19970028677 A KR19970028677 A KR 19970028677A KR 19990004550 A KR19990004550 A KR 19990004550A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로 워드라인으로 형성되는 다결정실리콘 및 게이트 산화막을 먼저 형성한 다음에 트렌치를 이용한 소자분리막을 형성함으로써 희생산화공정 및 게이트 공정을 하지 않아도 되므로 세정공정중 필드산화막의 손실을 방지할 수 있고 트렌치의 모서리부근에서의 절연막이 활성영역보다 밑으로 내려가는 것을 방지하여 상기 모서리부근에서의 전기장 집중에 의한 누설전류를 억제하며, 게이트 산화막의 씨닝(Thinning)현상을 막아 전기적 특성 열화를 방지하는 기술이다.Field of the Invention The present invention relates to a method for fabricating a semiconductor device. Since a polysilicon and a gate oxide film formed of a word line are formed first, and then a device isolation film using a trench is formed, a sacrificial oxidation process and a gate process do not need to be performed. Can prevent the loss of the insulating film near the corners of the trench below the active area to suppress the leakage current due to the concentration of the electric field near the corners, and prevent the thinning of the gate oxide film It is a technology to prevent deterioration of characteristics
Description
본 발명은 반도체소자의 제조방법에 관한 것으로 특히 트렌치를 이용한 소자분리막 형성시 상기 트렌치의 모서리부근에서의 절연막이 활성영역보다 밑으로 내려가는 현상을 방지하여 게이트 산화막의 씨닝현상을 방지하고 소자의 전기적 특성을 향상시키는 기술에 관한 것이다.The present invention relates to a method of fabricating a semiconductor device. In particular, when forming a device isolation layer using a trench, an insulating film near the corner of the trench is lowered below an active region to prevent thinning of the gate oxide and to prevent electrical properties of the device. It is about a technique to improve.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell siz)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices in terms of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices. Separation is a technique for determining memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : Local Oxidation of Silicon, 이하에서 LOCOS라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅 현상으로 기가(Giga DRAM)급 소지자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS) process method has a limitation in that it is applied to Giga DRAM holders due to a problem of thinning a device isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1㎛에 접근하면 트렌치 소자분리 공정도 적용하기가 여려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1㎛.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1은 종래기술에 따른 반도체소자의 제조방법을 나타낸 단면도이다.1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.
종래기술에 따른 듀얼(dual) 트렌치 소자분리막 형성방법은 필드가 넓은 부분에는 LOCOS 구조로 소자분리 산화막(102)을 형성하고, 게이트산화막(104)과 다결정실리콘층(105)을 미리 증착한 후, 필드가 좁은 부분에 트렌치를 이용한 소자분리막을 형성한다.In the method of forming a dual trench isolation layer according to the prior art, after forming the isolation oxide layer 102 in a LOCOS structure in a wide field, depositing the gate oxide layer 104 and the polysilicon layer 105 in advance, An isolation layer using a trench is formed in a narrow field.
상기와 같이 필드가 좁은 부분에 트렌치 소자분리막을 형성하는 경우에는 상기 트렌치를 매립하는 절연물(106)을 채워넣고, 다시 제거하는 공정에서 LOCOS 방법으로 형성된 소자분리 산화막(102) 때문에 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함) 방법을 사용하지 못하고 습식식각방법으로 전면식각하기 때문에 평탄도가 좋지 못하다.In the case of forming the trench isolation layer in a narrow field as described above, chemical mechanical polishing is performed due to the isolation oxide layer 102 formed by the LOCOS method in the process of filling the insulating material 106 filling the trench and removing the trench. Mechanical polishing (hereinafter referred to as CMP) method is not used and the flatness is not good because it is etched by wet etching.
따라서, 후속공정인 워드라인 마스크공정에 영향을 미치게 된다.Therefore, the word line mask process, which is a subsequent process, is affected.
또한, 상기 트렌치에 매립한 절연물의 증착균일도가 우수하지 못해서 증착이 적게된 부분에서는 상기 전면식각공정시 많은 양의 필드산화막이 식각되어서 상기 트렌치의 모서리부분의 필드산화막이 활성영역보다 밑으로 내려가는 문제점이 발생하게 된다. ( 도 1)In addition, in the case where the deposition uniformity of the insulation buried in the trench is not excellent, a large amount of field oxide film is etched during the entire surface etching process so that the field oxide film in the corner portion of the trench is lower than the active region. This will occur. (Figure 1)
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치 모서리부근의 절연막이 활성영역보다 밑으로 내려가는 현상을 방지하여 게이트 산화막의 씨닝현상을 억제하고 활성영역의 모서리 부근에서의 전기장이 집중되어 발생하는 전기적 특성 열화를 방지하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the insulating film near the corner of the trench is prevented from falling below the active region, thereby suppressing the thinning phenomenon of the gate oxide and generating an electric field near the corner of the active region. It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents deterioration of electrical characteristics.
도 1은 종래기술의 실시예에 따른 반도체소자의 제조방법을 나타낸 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the embodiment of the prior art.
도 2내지 도11은 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11,101 : 반도체기판 102 : 소자분리산화막11,101: semiconductor substrate 102: device isolation oxide film
13,104 : 게이트 산화막 15,105 : 다결정실리콘13,104 gate oxide film 15,105 polycrystalline silicon
17 : 패드산화막 19 : 질화막17: pad oxide film 19: nitride film
21 : 트렌치 23 : 제2열산화막21: trench 23: second thermal oxide film
25,106 : 절연물 27 : 텅스텐 실리사이드25,106: Insulator 27: Tungsten silicide
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은 반도체기판 상부에 게이트 산화막 및 다결정실리콘층을 형성하는 공정과 상기 다결정실리콘층 상부에 패드산화막 및 질화막을 형성하는 공정과 상기 질화막, 패드산화막, 다결정실리콘, 게이트 산화막 및 일정 두께의 반도체기판을 식각하여 트렌치를 형성하는 공정과 상기 트렌치 표면에 열산화막을 형성하는 공정과 상기 트렌치를 매립하는 절연물을 상기 질화막 상부까지 증착하는 공정과 상기 절연물을 상기 질화막이 노출될 때까지 화학적 기계적 연마하는 공정과 상기 질화막을 습식식각공정으로 제거하는 공정과 상기 패드산화막을 제거하는 공정과 상기 구조 상부에 텅스텐실리사이드를 형성하는공정과 워드라인 마스크를 이용한 식각공정으로 워드라인을 형성한느 공정을 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object is a step of forming a gate oxide film and a polysilicon layer on a semiconductor substrate and a step of forming a pad oxide film and a nitride film on the polycrystalline silicon layer and the nitride film, pad Forming a trench by etching an oxide film, a polycrystalline silicon, a gate oxide film, and a semiconductor substrate having a predetermined thickness, forming a thermal oxide film on the trench surface, and depositing an insulating material filling the trench up to the nitride film; Chemical mechanical polishing until the nitride film is exposed; removing the nitride film by wet etching; removing the pad oxide film; forming tungsten silicide on the structure; and etching using a word line mask. Balls forming word lines by process It characterized in that it comprises a.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2내지 도11은 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성공정을 도시한 단면도이다.2 to 11 are cross-sectional views illustrating a device isolation insulating film forming process of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 게이트 열산화막(13)을 형성한다. 이때, 상기 게이트 열산화막(13)은 30 ~ 100Å두께로 형성한다.First, a gate thermal oxide layer 13 is formed on the semiconductor substrate 11. In this case, the gate thermal oxide film 13 is formed to a thickness of 30 ~ 100Å.
그리고, 상기 게이트 열산화막(13) 상부에 다결정실리콘층(15)을 형성한다.A polysilicon layer 15 is formed on the gate thermal oxide layer 13.
이때, 상기 다결정실리콘층(15)은 500 ~ 1500Å정도의 두께로 형성한다. (도 2)At this time, the polysilicon layer 15 is formed to a thickness of about 500 ~ 1500Å. (Figure 2)
다음 상기 다결정실리콘층(15) 상부에 패드산화막(17)을 50 ~ 200Å의 두께로 형성한다.Next, a pad oxide film 17 is formed on the polysilicon layer 15 to a thickness of 50 to 200 Å.
그 다음, 상기 패드산화막(17) 상부에 질화막(19)을 500 ~ 2000Å정도 두께로 형성한다. (도 3)Next, a nitride film 19 is formed on the pad oxide film 17 to a thickness of about 500 to about 2000 kPa. (Figure 3)
이어서, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 질화막(19), 패드산화막(17), 다결정실리콘층(15), 게이트 열산화막(13) 및 반도체기판(11)을 식각하여 트렌치(21)를 형성한다.Subsequently, the nitride layer 19, the pad oxide layer 17, the polysilicon layer 15, the gate thermal oxide layer 13, and the semiconductor substrate 11 are etched by an etching process using an isolation mask (not shown). 21).
이때, 상기 반도체기판(11)은 1500 ~ 4000Å정도 깊이로 식각하여 트렌치(21)를 형성한다. (도 4)At this time, the semiconductor substrate 11 is etched to a depth of about 1500 ~ 4000Å to form a trench 21. (Figure 4)
그리고, 상기 트렌치(21) 표면에 제1열산화막(도시안됨)을 형성하기 위한 제1차 산화공정을 실시한다.In addition, a first oxidation process is performed to form a first thermal oxide film (not shown) on the surface of the trench 21.
이때, 상기 제1열산화막(도시안됨)은 50 ~ 200Å정도의 두께로 형성한다.In this case, the first thermal oxide film (not shown) is formed to a thickness of about 50 ~ 200Å.
그리고, 상기 제1열산화막(도시안됨)을 습식식각으로 제거한다.The first thermal oxide layer (not shown) is removed by wet etching.
이때, 제1차 산화공정과 이로 인해 형성된 제1열산화막(도시안됨)의 제거공정은 상기 트렌치(21)형성공정시 발생된 트렌치(21) 표면의 결함을 제거한다.At this time, the primary oxidation process and the removal process of the first thermal oxide film (not shown) formed thereby removes defects on the surface of the trench 21 generated during the trench 21 formation process.
그리고, 제2차 산화공정으로 트렌치(21) 측벽에 제2열산화막(23)을 50 ~ 200Å정도 두께로 형성한다. (도 5)In the second oxidation process, the second thermal oxide film 23 is formed on the sidewall of the trench 21 to a thickness of about 50 to about 200 microseconds. (Figure 5)
다음, 상기 전체표면에 화학기상증착(chemical vapor deposition, 이하 CVD라 함)방법을 사용하여 상기 트렌치에 절연물(25)을 형성한다.Next, an insulator 25 is formed in the trench using a chemical vapor deposition (CVD) method on the entire surface.
이때, 상기 절연물(25)은 상기 질화막(19)을 덮을 정도로 증착한다. (도 6)In this case, the insulator 25 is deposited to cover the nitride film 19. (Figure 6)
그 다음, 상기 절연물(25)은 CMP 공정을 사용하여 상기 질화막(19)이 드러날 때까지 제거한다.(도 7)The insulator 25 is then removed until the nitride film 19 is exposed using a CMP process (FIG. 7).
다음, 상기 질화막(19)을 제거한다. (도 8)Next, the nitride film 19 is removed. (Figure 8)
이어서 상기 패드산화막(17)을 제거한다. (도 9)Subsequently, the pad oxide layer 17 is removed. (Figure 9)
다음 상기 구조 전표면 상부에 텅스텐 실리사이드(27)를 증착한다.Next, tungsten silicide 27 is deposited on the entire structure surface.
이때 상기 텅스텐 실리사이드(27)는 500 ~ 1500Å정도 증착한다. (도 10)At this time, the tungsten silicide 27 is deposited about 500 ~ 1500Å. (Figure 10)
그 다음, 상기 텅스텐 실리사이드(27) 상부에 감광막(도시안됨)을 도포한다.Next, a photoresist (not shown) is applied on the tungsten silicide 27.
그리고, 상기 감광막을 워드라인 마스크(도시안됨)로 사용하여 노광시킨 후 현상하여 감광막 패턴을 형성한다.The photoresist film is exposed using a word line mask (not shown) and then developed to form a photoresist pattern.
그 후, 상기 감광막 패턴을 식각마스크로 사용하여 상기 텅스텐 실리사이드(27), 다결정실리콘층(15) 및 게이트 산화막(13)을 식각하여 워드라인을 형성한다. (도 11)Thereafter, the tungsten silicide 27, the polysilicon layer 15, and the gate oxide layer 13 are etched using the photoresist pattern as an etching mask to form a word line. (Figure 11)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은 워드라인으로 형성되는 다결정실리콘 및 게이트 산화막을 먼저 형성한 다음에 트렌치를 이용한 소자분리막을 형성함으로써 희생산화공정 및 게이트 공정을 하지 않아도 되므로 세정공정중 필드산화막의 손실을 방지할 수 있고, 트렌치의 모서리부근에서의 절연막이 활성영역보다 밑으로 내려가는 것을 방지하여 상기 모서리부근에서의 전기장 집중에 의한 누설전류를 억제하며 게이트 산화막의 씨닝현상을 막아 전기적 특성 열화를 방지하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a polysilicon and a gate oxide film formed of a word line are first formed, and then a device isolation film using a trench is formed, thereby eliminating the need for sacrificial oxidation and gate processes. It is possible to prevent the loss of the field oxide film during the process, to prevent the insulating film near the corners of the trench from falling below the active region, to suppress the leakage current due to the electric field concentration near the corners, and to prevent the thinning of the gate oxide film. There is an advantage of preventing the deterioration of electrical characteristics.
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