KR19990004501A - FIR filter with asymmetric frequency response - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

FIR filter with asymmetric frequency response

2. The technical problem to be solved by the invention

Reduced chip size by reducing the use of multipliers

3. Summary of Solution to Invention

Control to perform a filter function for 1.5 clock periods of the first clock (clk) by using the first clock (clk), which is the data clock of the filter, and the second clock (clk2) having twice the speed of the first clock. A control signal generator 100 for generating a signal; It is connected to the control signal output terminal of the control signal generator 100, time-divisionally inputs the data applied to the filter according to the control signal applied from the control signal generator 100, and time-divisions the operation of the multiplier. It is composed of a filter calculation unit 200 for performing a filter function.

4. Important uses of the invention

Communication signal field and image signal processing field

Description

FIR filter with asymmetric frequency response

The present invention relates to a FIR filter for outputting a 90 ° phase shift of an input image and other signal phases, and in particular, a multiplier corresponding to a quarter of the number of filter taps. Since the filter is constructed using only (MULTIPLIER), it is to simplify the circuit and reduce the size of the chip.

As is well known, the basic structure of all filters is determined by the coefficient values of the taps extracted by each algorithm (ALGORITHM) and the number of taps. Therefore, when the coefficient value of the tap and the number of taps are determined, an FIR filter having an asymmetric structure can be implemented.

Equation [1] below shows the relationship between the number of taps and the tap coefficient of a filter.

K = (M + 1) / 2, when M is odd

When K = M / 2, M is even... … … … … … … … … … … … … … [One]

Here, M represents the number of taps, and K represents the number of tap coefficients.

For example, in the case of an FIR filter with an asymmetric frequency response with 31 taps, the number of tap coefficients is (31 + 1) / 2 = 16, which can be obtained by entering the filter.

However, the conventional FIR filter as described above has a problem in that a multiplier having the same number as the number of taps is required because the calculation corresponds to the number of taps, so that the size of the filter should be increased in proportion to the number of taps.

In other words, the factor that most dictates the size of the chip constituting the integrated circuit is a multiplier. Since the number of the multiplier increases in proportion to the number of taps, there is a problem that the size of the chip cannot be easily reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional problems as described above. Particularly, after generating a predetermined control signal using a data clock of a filter and a clock twice as fast as the data clock, the control signal is generated. Since the data applied to the multiplier is time-selected and applied to the multiplier to perform a multiplication operation, the FIR filter can be configured using a multiplier corresponding to 1/4 of the multiplier constituting the conventional FIR filter. In addition, the present invention provides an FIR filter having an asymmetric frequency response that can reduce chip size, reduce production costs, and reduce manufacturing processes.

In order to achieve the above object, the FIR filter having the asymmetric frequency response characteristic of the present invention uses a first clock which is a data clock of the filter and a second clock having twice the speed of the first clock. A control signal generator for generating a control signal for performing a filter function for a 1.5 clock period; A filter operation unit connected to the control signal output terminal of the control signal generator, time-division-inputs data applied to the filter according to a control signal applied from the control signal generator, and performs a filter function by time-dividing the operation of the multiplier. It is configured to include a feature of the technical configuration.

In addition, the control signal generator,

A 1D flip flop (DELAY FLIP FLOP);

2D flip-flop;

A 3D flip-flop;

A 4D flip-flop;

A first inverter (INVERTER);

A second inverter;

Consisting of a third inverter,

A first clock, which is a data clock of a filter, is connected to a data input terminal of the first D flip-flop, a second clock having a double speed of the first clock is connected to input terminals of the second and third inverters, The output terminal of the first D flip flop is connected to the data input terminal of the second D flop flop, the output terminal of the second D flip flop is connected to the data input terminal of the third D flop flop, An output terminal is connected to the data input terminal of the 4D flop flop, an output terminal of the second inverter is connected to a clock application terminal of the 1D flip flop and the 3D flip flop, and the second clock is connected to the 2D It is connected to the clock application terminal of the flip-flop, and the output value of the first inverter is used as the first input control signal which is a control signal for the multiplier input of the data to be filtered, and the output value of the third inverter is used for the data to be filtered. multiplication It is used as a second input control signal which is a control signal for input, and the output value of the 1D flip-flop is used as a first time division control signal for time division and storing a multiplier's calculation result in a predetermined storage location. The output value of the 2D flip-flop is used as a second time division control signal for time division and storing the multiplier's calculation result in a predetermined storage location, and the output value of the 3D flip-flop is used as the output result of the multiplier. And a third time division control signal for time division and storing, and an output value of the 4D flip-flop as a fourth time division control signal for time division and storing a multiplier's calculation result in a predetermined storage location. Features of the jacket.

The filter operation unit may include a shift register unit configured of a plurality of shift registers to shift data to be filtered by a first clock; A multiplexer (MULTIPLEXER) connected to the signal output terminal of the shift register unit and operated by a control signal for controlling a multiplier input of the data to be filtered to select and output data applied from the shift register unit; 1 multiplexer section; A tap coefficient generator for generating tap coefficients of a filter; a multiplier portion connected to signal outputs of the first multiplexer portion and the tap coefficient generator, and multiplying the signals applied by the first multiplexer portion and the tap coefficient generator; A first D flip-flop unit comprising a plurality of D flip-flops and connected to a signal output terminal of the multiplier unit to store an output value of the multiplier unit by a second clock and an inverted signal of the second clock; A second multiplexer comprising a plurality of multiplexers connected to the signal output terminal of the first D flip-flop unit and operated by a control signal for controlling a multiplier input of the data to be filtered, thereby selecting and outputting data applied from the shift register unit. A first adder unit connected to a signal output terminal of the second multiplexer unit and configured with a plurality of adders arranged in a plurality of stages to add a value applied from the second multiplexer unit; an output terminal of the first adder unit; A second D flip-flop unit comprising: a plurality of D flip-flops connected to the second time flip-flop unit for time division and storing the multiplication operation result output from the first adder by a predetermined control signal; Technical features of the technical construction comprising: a second adder unit connected to the signal output terminal of the 2D flip-flop unit and including a plurality of adders arranged in a plurality of stages, and which adds a value applied from the 2D flip-flop unit; It is done.

The FIR filter having the asymmetric frequency response characteristic of the present invention, in particular, generates a predetermined control signal using the first clock and the second clock, and then time-partitions the data applied to the multiplier using the control signal. By selecting and applying to the multiplier to perform a multiplication operation, it is possible to configure the FIR filter using a multiplier corresponding to a quarter of the multiplier constituting the conventional FIR filter, which is the size of the circuit elements and chips Can be reduced.

1 is a block diagram showing the configuration of a FIR filter having an asymmetric frequency response of the present invention;

2 is a block diagram showing a configuration of a control signal converter of an FIR filter having an asymmetric frequency response of the present invention;

3 is a view showing the configuration of the filter operation unit of the FIR filter having an asymmetric frequency response of the present invention;

4 is a timing diagram showing each signal used in the embodiment of the FIR filter having the asymmetric frequency response of the present invention;

5 is a circuit diagram showing the configuration of the tap coefficient generator in the FIR filter having an asymmetric frequency response of the present invention.

Explanation of symbols for the main parts of the drawings

100: control signal generator 200: filter operation unit

101: 1D flip flop 102: 2D flip flop

103: 3D flip flop 104: 4D flip flop

105: first inverter 106: second inverter

107: third inverter 200: filter operation unit

201: shift leather part 202: first multiplexer part

203: Tap coefficient generator 204: First multiplier

205: 1st flip-flop part 206: 2nd multiplexer part

207: first multiplier 208: second 2D flip flop

209: Second addition donor

Hereinafter, with reference to the accompanying drawings for an embodiment according to the technical idea of the FIR filter having an asymmetric frequency response characteristic of the present invention configured as described above in detail as follows.

Example

First, as shown in Figs. 1 and 2, the first clock clk, which is the data clock of the filter, is connected to the data input terminal Dl and the input terminal of the first inverter 105 of the first D flip-flop 101. And a second clock clk2 that finds a double speed of the first clock clk to an input terminal of the second inverter 106 and the third inverter 107, and the first D flip-flop 101. Is connected to the data input terminal D2 of the 2D flop flop 102 and the output terminal of the 2D flip flop 102 is connected to the data input table D3 of the 3D flop flop 102. The output terminal of the 3D flip-flop 103 is connected to the data input terminal D4 of the 4D flop flop 104, and the output terminal of the second inverter 106 is the first D flip-flop 101. ) And the clock application terminals cp1 and cp3 of the 3D flip-flop 103, and the second clock force clk2 to the clock application terminal cp2 of the second D flip-flop 102. 100), the first person The output of the first input control signal mux_sel0 and the output of the third inverter 107 as the second input control signal mux_sel1, and the output of the first D flip-flop 101 An output is used as a first time division control signal dff_enl, an output of the second D flip-flop 102 is used as a second time division control signal dff_en2, and an output of the third D flip flop 103 is used as a third. The control signal generator 100 is configured by using the time division control signal dff_en3 and using the output of the fourth D flip-flop 101 as the fourth time division control signal dff_en4.

In addition, as shown in FIG. 3, the shift register unit 201 is connected so that data to be filtered is input by the first clock c1k, and a first multiplexer is connected to a signal output terminal of the shift register unit 210. The unit 202 is connected to operate by the first input control signal mux_del0 and the second input control signal mux_del1, and connected to the first input control signal mux_del0 and the second input control signal mtlx_del1. The tap coefficient generator 203 is connected to operate the multiplier 204 between the signal output terminal of the first multiplexer 201 and the tap coefficient generator 203 and the first D flip-flop unit 205. And a second multiplexer unit 206 connected between the first D flip-flop unit 205 and the first multiplier unit 207 to operate the second clock clk2 and the first input control signal mux_sel1. And a second D flip-flop unit 208 operating on the first time division control signal dff_en1 to the fourth time division control signal dff_en4. The second addition to the base 209 is connected in turn to an output of the first addition the base 207 constitute a filter calculation unit 200. The

Here, the shift register of the shift example register unit 201 is an N-bit 8-tap shift register, the multiplexer of the first multiplexer unit 202 is a (4 × 1) multiplexer, and the tap coefficient generator 203 ) Is an odd / even tap coefficient generator, the multiplier of the multiplier unit 204 is an (N × N) multiplier, and the D flip-flop of the first D flip-flop unit 205 is a 2 (N + M) bit D flip And the multiplexer of the second multiplexer portion 206 is a (2 × 1) multiplexer, and the D flip-flop of the 3D flip-flop portion 208 is a [2 (N + M) +2] bit D flip-flop. to be.

5 shows the configuration of the tap coefficient generator 203. The operation of four (4 x 1) multiplexers using the first input control signal mux_sel0 and the second input control signal mux_sel1 as the selection terminals is shown in FIG. It is to control the.

Hereinafter, the operation of the present embodiment configured as described above will be described in detail.

First, the operation of the control signal generator 100 generating the first and second input control signals mux_de10 and mux_del0 and the first, second, third and fourth time division control signals dff_en1, dff_en2, dff_en3, and dff-en3 is performed. The explanation is as follows.

After applying the first clock (clk) to the first D-flop flop 101, the falling edge (NEGATIVE EDGE) by using the second clock clk2 with the same clock speed twice as the input of the second inverter 106 When clocked at CLODKING, as shown in FIG. 4, the first time division control signal dff_en1 delayed 1/4 of the first clock clk is generated, and the second D flip-flop 102 is similarly operated. The second time division control signal dff_en2, the third time division control signal dff_en3, and the fourth time division control signal dff_en4 are sequentially generated by the third 3D flip flop 103 and the fourth D flip flop. .

Hereinafter, the operation of the filter operator 200 will be described.

First, as the first clock clk proceeds, the data stored in the shift register 201 is a signal value of a 2-bit first input control signal mux_sel0 and a second input control signal mux_sel2. Accordingly, the shift register 201 and the tap coefficient generator 203 select one piece of corresponding data and apply the data to the multiplier 204. Then, the multiplier 204 stores the multiplied value in the first D flip-flop unit 205. When the second clock clk2 rises, the multiplier unit 204 stores the multiplied value in the odd-numbered D flip-flop A. At the time, each is stored in the even-numbered D flip-flop (B).

Meanwhile, the data stored in the first D flip-flop unit 205 is performed by the second multiplexer unit 206 and the first adder 207 under the control of the first input control signal mux_sel0. .

In this case, the addition operation result adds only the 1/4 tap number. Therefore, in order to perform the addition operation by performing the same processing on the remaining 3/4 tap number, the 1/4 addition result value must be stored. The third and fourth time division control signals dff_enl, dff_en2, dff_en3, and dff_en3 are applied.

On the other hand, after the above-described process is repeated four times to complete the addition operation for all the taps, this value is set to the second D flip-flop 208.

Subsequently, when the value stored in the second D flip-flop 208 is added through the second adder 209, a value Qout [N · 0] whose phase is shifted by 90 ° with respect to the original signal is obtained. It becomes possible. The round-off block, which is an unexplained block in the drawing, shows a function of rounding when a value of 1 bit located directly below the desired number of bits is 1.

Therefore, the filter operation can be performed using the multiplier of 1/4 of the number of taps.

As described above, the FIR filter having the asymmetric frequency response of the present invention, in particular, generates a predetermined control signal using the first clock and the second clock, and then is applied to the multiplier using the control signal. By multiplying the data and applying it to a multiplier to perform a multiplication operation, the FIR filter can be configured using a multiplier corresponding to a quarter of the multiplier constituting the conventional FIR filter. And there is an effect that can reduce the size of the chip.

Claims (3)

A control signal generator for generating a control signal for performing a filter function during the 1.5 clock period of the first clock by using the first clock, which is the data clock of the pulter, and the second clock having twice the speed of the first clock; ; A filter operation unit connected to a control signal output terminal of the control signal generator, time-division-inputs data applied to the filter according to a control signal applied from the control signal generator, and performs a filter function by time-dividing the operation of the multiplier. FIR filter having an asymmetric frequency response characteristic, characterized in that configured to include. 2. The apparatus of claim 1, wherein the control signal generator comprises: a first flip flop; 2D flip-flop; A 3D flip-flop; A 4D flip-flop; A first inverter; A second inverter; A first clock comprising a third inverter, the first clock being the data clock of the filter connected to the data input terminal of the first flip-flop, and a second clock having twice the speed of the first clock being connected to the second inverter and the third An input terminal of the inverter, an output terminal of the first D-flop flop to a data input terminal of the second D-flop flop, and an output terminal of the second D-flop flop to a data input terminal of the third D-flop flop The output terminal of the 3D flip-flop is connected to the data input terminal of the 4D flop flop, and the output terminal of the second inverter is connected to the clock application terminal of the 1D flip-flop and the 3D flip-flop. The second clock force is connected to the clock application terminal of the second D flip-flop, and the output value of the first inverter is used as a first input control signal which is a control signal for inputting a multiplier of the data to be filtered, and the third inverter The output of It is used as a second input control signal which is a control signal for inputting a multiplier of data to be filtered, and the first time division control signal for time-dividing and storing the output result of the first D flip-flop into a predetermined storage location. Using the output value of the second D flip-flop as a second time division control signal for time division and storing the multiplier's calculation result in a predetermined storage location, and using the output value of the third D flip flop Used as a third time division control signal for time division and storage at a predetermined storage location, and an output value of the 4D flip-flop is used as a fourth time division control signal for time division and storing a multiplier's calculation result at a predetermined storage location. FIR filter with asymmetric frequency response. The apparatus of claim 1, wherein the filter operation unit comprises: a shift register unit configured to include a plurality of shift registers to shift data to be filtered by a first clock; and a plurality of multiplexers connected to a signal output terminal of the shift register unit; A first multiplexer unit operated by a control signal for controlling a multiplier input of data to be filtered to select and output data applied from the shift register unit; A tap coefficient generator for generating tap coefficients of the filter; A multiplier unit connected to the signal output terminals of the first multiplexer unit and the tap coefficient generator, and multiplying a signal applied by the first multiplexer unit and the tap coefficient generator; A first D flip-flop unit comprising a plurality of D flip-flops and connected to a signal output terminal of the multiplier unit to store an output value of the multiplier unit by a second clock and an inverted signal of the second clock; A second multiplexer unit which is connected to a signal output terminal of the flip-flop unit and is operated by a control signal that controls a multiplier input of data to be filtered, and selects and outputs data applied from the shift register unit; ; A first adder unit connected to a signal output terminal of the second multiplexer unit and configured to add a plurality of adders to add a value applied from the second multiplexer unit; a first adder unit connected to an output terminal of the first adder unit; A second D flip-flop unit comprising a plurality of D flip-flops and time-dividing and storing a multiplication result output from the first adder by a predetermined control signal; An asymmetric frequency response connected to the signal output terminal of the 2D flip-flop unit and including a second adder unit arranged in a plurality of stages to add a value applied from the 2D flip-flop unit. FIR filter with characteristics.