KR19990004397A - Metal wiring formation method of semiconductor device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs

The present invention relates to a method for forming metal wiring of a semiconductor device.

2. Technical problem to be solved by the invention

This is to solve the problem that the contact resistance is increased by the impurities generated by the reaction of the fluorine component of the etching gas with the diffuse reflection film when forming the via hole for the metal wiring.

3. Summary of Solution to Invention

In the subsequent heat treatment process after the via hole is formed, nitrogen is flowed and the temperature of the chamber is increased to degas the fluorine ions, thereby preventing the increase of the contact resistance.

Description

Metal wiring formation method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.

In general, CF ₄ , CHF ₃ , argon (Ar), etc. are used as a dry etching gas when forming via holes for metal wiring. In this case, the fluorine component (F +) reacts with oxide films such as spin on glass (SOG) and intermetal oxide (IMO) to form holes. For complete opening of the via holes, etching is typically performed with a target of 1.4 to 1.8 times the thickness of the oxide film. At this time, titanium and fluorine ions, which are diffuse reflection films on the open via hole portions of the first metal layer, react with each other to generate impurities of TiF ₃ . Due to the generation of TiF ₃ there is a problem that the contact resistance is increased during the deposition of the second metal layer.

Accordingly, the present invention provides a method for forming a metal wiring of a semiconductor device capable of preventing an increase in contact resistance by flowing nitrogen and degassing fluorine ions in a subsequent heat treatment process after via holes are formed. There is a purpose.

According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method comprising: sequentially forming a titanium / titanium nitride film, a first metal layer, and a diffuse reflection film on a semiconductor substrate, and then patterning the selected region; Forming an oxide planarization layer on the structure, forming a via hole by etching the oxide planarization layer using a photoresist film, removing the photoresist film, and then performing a heat treatment process; Characterized in that the step of forming a metal layer.

The accompanying drawings are cross-sectional views of the elements shown for explaining the metal wiring formation method according to the present invention.

Explanation of symbols for the main parts of the drawings

1 semiconductor substrate 2 Ti / TiN film

3: first metal layer 4: diffuse reflection film

5a: IMO 1 5b: SOG

5c: IMO 2 5: oxide film planarization layer

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The accompanying drawings are cross-sectional views of the devices shown for explaining the metal wiring formation method according to the present invention. The titanium / titanium nitride (Ti / TiN) film 2, the first metal layer 2, and the diffuse reflection film 4 are sequentially formed on the semiconductor substrate 1, and then the selected region is patterned. At this time, titanium (Ti) is used as the diffuse reflection film (4). Thereafter, the oxide film planarization layer 5 is formed on the entire structure. The oxide film planarization layer 5 is composed of three layers of IMO 1 (5a), SOG 5b, and IMO 2 (5c). Thereafter, an etching process is performed to form a via hole, and then the photoresist film is removed. At this time, as an etching gas, CF ₄ , CHF _3, etc. are used, and the photoresist is removed using oxygen (O ₂ ) gas from an ATC (After Treatment Chamber) or DSQ (Decoupled Source Quartz), which is a photoresist removal module. At this time, the temperature of the chamber is set to 200 to 280 ° C. to prevent photosensitive film burning. After removing the photoresist, nitrogen gas is added to 100 to 300 sccm, and the chamber temperature is increased to 350 to 500 ° C. or higher to degas the fluorine in a high temperature nitrogen atmosphere. Accordingly, it is possible to prevent the generation of TiF ₃ , which is an impurity due to the combination of the fluorine and the diffuse reflection film, and to prevent an increase in contact resistance during deposition of the second metal layer.

In this way, the generation of impurities can be prevented for all via holes for the metal wiring and the increase in contact resistance can be prevented.

As described above, according to the present invention, by the high temperature heat treatment process using nitrogen gas, it is possible to prevent the generation of impurities due to the combination of the etching gas and the diffuse reflection film, thereby reducing the contact resistance between the metal layers and improving the yield of the device. That has an excellent effect.

Claims (3)

Sequentially forming a titanium / titanium nitride film, a first metal layer and a diffuse reflection film on the semiconductor substrate, patterning the selected region, forming an oxide planarization layer on the entire structure, and forming a photoresist film on the oxide planarization layer. Forming a via hole by etching, performing a heat treatment process after removing the photosensitive film, and forming a second metal layer after the heat treatment process. The method of claim 1, wherein the heat treatment step is performed by adding nitrogen gas at 100 to 300 sccm. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the heat treatment step is performed at a temperature of 350 to 500 deg.