KR19990003934A - Asynchronous test apparatus and method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Chip testing.

2. Technical problem to be solved by the invention

By using an external interrupt generated by the tester instead of using the match mode, the tester can reduce the unnecessary time required for the test and the tester can select the output time of the chip's self-testing result. To provide a device and method.

3. Summary of the Solution of the Invention

The asynchronous test that outputs the calculation result by processing the service routine of this interrupt after generating the external interrupt by the external tester after keeping the result constant rather than immediately outputting the result of the self test inside the chip. To provide a device and method.

4. Important uses of the invention

Available for all chips performing asynchronous self test.

Description

Asynchronous test apparatus and method.

The present invention relates to a chip test, and can be applied to a chip performing a self test using an asynchronous protocol.

Asynchronous self-test sends a test result to the tester when the test result comes out so as to determine whether the chip is good or bad. Because it is asynchronous, the tester cannot know when the data line of the test result becomes active and there is a problem that the tester always needs to check.

1 is a conventional test flowchart using a match mode, in which a test includes a first step in which a chip performs a self-test routine, a second step in performing a match mode, a third step of outputting a chip's self-testing result, and a tester It consists of a fourth step which is a result determination step by. In the second step of performing the match mode, the system clock is stopped, and if the tester checks whether the data line of the chip's self-testing result is active, if the tester is active, proceeds with the system clock and outputs the result data to the third step. In the case of inactive, the test routine is performed again while the system clock is executed, and then the match mode test is performed from the beginning. In the match mode, the tester always checks the data line within a predetermined time to determine the output time of the data according to a predetermined rule such as a start bit. However, in the test using the conventional match mode, it is difficult to know in advance the exact time at which the self-testing result of the chip is output. In addition, the process of stopping the system clock is inserted in the middle, which wastes unnecessary time for testing. It also complicates the program that controls the test and makes parallel test implementation difficult.

The present invention has been made to solve the above problems, by using an external interrupt generated by the tester without using the match mode, to reduce the unnecessary time consumed in the test, the output time of the chip self-testing result Its purpose is to provide an asynchronous test apparatus and method that can be implemented by parallel testers by the tester.

1 is a conventional test flow chart,

2 is a test flowchart of the present invention;

3 is a test configuration diagram of the present invention,

4 is a parallel test configuration diagram according to the present invention.

In accordance with another aspect of the present invention, a test apparatus for a chip includes: an external tester means for testing, a start signal and a clock signal received from the external tester means, and a signal and a self-testing result indicating that the self-testing of the chip is finished. And a test logic means for outputting the control logic means for outputting the self-testing result of the test logic means by the test logic means inside the chip to be tested and the interrupt request of the external tester means.

In addition, in an apparatus for parallel testing of a plurality of chips, an external tester means for testing, receiving a start signal and a clock signal from the external tester means, the signal indicating that the self-test of each chip is finished and the result of the self-testing An internal test logic means for each of the plurality of chips to be output and a control logic means for outputting the self-testing results of the logic test logic means by an interrupt request of the external tester means in parallel. It includes an asynchronous test device for testing.

In the asynchronous test method, a first step in which a chip to be tested performs a self-test routine, a second step in processing an external interrupt requested by the external tester means, and the tester is output from the second step. And a third step of determining a self test result of the chip.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

This interrupt service does not output the self-testing result inside the chip to be tested immediately and maintains a certain value, and generates an external interrupt by the tester after sufficient time to complete the self-test of the chip when judged by the external tester. Output the self-testing result while processing the routine. If self-testing is not complete, externally requested interrupts are ignored and the chip continues the self-test.

2 is a test flowchart according to the present invention, in which a chip performs a self test routine, a second step of processing an external interrupt requested by a tester, and a tester outputs a result of a self test of the chip output from the second step. The third step is to determine.

The second step of processing the external interrupt requested by the tester may include: activating the external interrupt, determining whether the chip self-test routine is completed, and if the self-test routine is not completed, the first step again. When the execution of the self test routine is completed, the process is performed by performing a service of the active external interrupt and outputting a result of performing the interrupt.

3 is a test configuration diagram of the present invention, which receives a start signal START and a clock signal CK from an external tester 10 and an external tester for a test, and indicates a FIN signal and a self-testing result indicating that the testing is completed ( and a control logic 30 outputting a self-testing result of the test logic 20 by an interrupt request of an external tester and a test logic 20 inside the chip to be tested. In addition, the control logic 30 includes an AND gate 31 for performing an AND operation on the interrupt request signal input from an external tester, the system clock signal, and an interrupt enable signal input from the test logic inside the chip, and the test logic inside the chip. A test result latch 32 for receiving and latching a self-testing result as an input and outputting the result according to a system clock, and a three-phase buffer 33 for outputting the self-testing result value output from the latch according to the output of the AND gate to an external tester. It is composed of

When the self test is completed in the test logic 20 of the chip to be tested and the test result is available, the interrupt enable signal, which is an input of the control logic 30, is activated by the FIN signal. At the same time, the chip self-testing result is stored in the test result latch 32. At this time, when the interrupt request signal REQ is received from the external tester 10, ACK, which is a result signal of the AND gate 31, is enabled, and the value of the test result latch 32 is changed to the three-phase buffer 33 by the ACK signal. Is output through the chip and the chip's self-testing result is transmitted to the external tester 10.

The control logic 30 may be built in the chip, or may be configured by adding it to the outside as shown in FIG. It can also be implemented in software to modify external interrupt service routines. In other words, when the chip's self-test operation is completed, the interrupt is enabled and the service routine outputs the self-test operation result when requested from the outside. Should be distinguished.

4 is a parallel test configuration diagram according to the present invention, in which a test configuration for one chip of FIG. 3 is extended to a plurality of chips. Each test logic, each test result latch, and each three-phase buffer for a plurality of chips, each of the self-testing outputs for the plurality of chips by using an AND gate to the external tester to test Multiple chips can be tested in parallel.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention made as described above does not need to stop the system clock to confirm the test results by eliminating the use of match mode, thereby reducing the unnecessary test time. In addition, the overall test flow can be simplified, and the control of the test can be simplified, so that parallel test can be easily implemented, thereby greatly improving the test yield.

Claims (8)

A test apparatus for a chip, comprising: an external tester means for testing, a start signal and a clock signal received from the external tester means, and a signal indicating that the self test of the chip is completed and outputting a signal and a self-testing result to be tested. And control logic means for outputting a self-testing result of the test logic means in response to an interrupt request of the test logic means and the external tester means. 2. The control circuit according to claim 1, wherein the control logic means comprises: logic means for logically multiplying an interrupt request signal and a clock signal input from the external tester means and an interrupt enable signal input from the test logic means inside the chip, and the test inside the chip. Test result storage means for receiving and latching the self-testing result of the logic means as an input and outputting it according to a clock, and a three-phase buffering means for outputting the self-testing result value output from the storage means to the external tester according to the output of the logic means. Asynchronous test apparatus comprising a. 3. The asynchronous test apparatus of claim 2, wherein the interrupt enable signal is activated when self-testing is available in the test logic means inside the chip to be tested and the self-testing result is available. An apparatus for parallel testing of a plurality of chips, the apparatus comprising: an external tester means for testing, a start signal and a clock signal are input from the external tester means, and a signal indicating that the self-testing of each chip is finished and outputting a self-testing result Parallel test of a plurality of chips comprising an internal test logic means of each of the plurality of chips to be tested and a control logic means for outputting the self-testing results of the plurality of logic test logic means by the interrupt request of the external tester means Asynchronous test device for 5. The apparatus of claim 4, wherein the control logic means comprises: first logic means for receiving and multiplying a plurality of interrupt enable signals output from internal test logic means of each of the plurality of chips; A second logic means for logically multiplying the enable signal, a clock signal, and an interrupt request signal output from the external tester means, and respective self-testing results output from internal test logic means of each of the plurality of chips as inputs. Each self-test output from the plurality of test result storage means in response to the output values of the plurality of test result storage means and the second logic means, respectively, after receiving and latching each of the plurality of interrupt enable signals. A plurality of output the result value to the external tester Of the three-phase asynchronous buffering means of the test apparatus for the parallel testing of a plurality of chips comprising a. An asynchronous test method, comprising: a first step of a chip to be tested performing a self-test routine, a second step of processing an external interrupt requested by the external tester means, and a tester outputting the chip from the second step And a third step of determining a self test result. 7. The method of claim 6, wherein the second step comprises the steps of: activating the external interrupt, determining whether the execution of the self test routine of the chip is completed, and if the execution of the self test routine is not completed, the first step. Is continued to perform routine execution, and when the self-test routine execution is completed, performing a service of the active external interrupt and outputting a result of performing the service of the external interrupt. Way. The method according to claim 6, wherein an external interrupt is generated by an external tester without directly outputting the self-testing result of the chip to be tested, and the self-testing result of the chip is output to the external tester while processing the interrupt service routine. Asynchronous test method for determining good / bad of chips.