JPS6037998B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device for an electronic computer.

More specifically, the present invention relates to a semiconductor memory device using a semiconductor memory element capable of performing page mode. Conventionally, a package containing a semiconductor memory element of a semiconductor memory device used in an electronic computer has the same number of address input pins as the number of address information, and uses an all-address method in which all address information is input once per operation cycle. Met.
However, as semiconductor memory devices become more highly integrated, the number of address input pins increases because the number of address information per package increases, which tends to increase the size of the package and prevent high-density packaging. To solve this problem, we decided to divide the address information into two parts, the row address and the column address, use the same address input pin to input different times, and make the number of address input pins smaller than the number of address information. Semiconductor memory devices using a packaged address multiplex system have begun to be produced. In this address multiplex type semiconductor memory element, two row addresses and two column addresses are generated within one operation cycle.
In addition to the normal mode in which the row address is input in separate steps, if the row address matches in the previous operation cycle and the next operation cycle, the input of the row address is omitted in the next operation cycle, and the input time of the o row address is There are semiconductor memory devices that have two page modes in which only column addresses are input. This page mode omits row address input, so access time is shorter than normal mode.
It has the advantage of shortening cycle time. Therefore, it is possible to improve the throughput of a semiconductor memory device by operating it in page mode of a semiconductor memory device using a semiconductor memory element capable of page mode using the address multiplex method. A possible method is to receive a page mode designation signal from an arithmetic unit that is an information generating device. However, if the semiconductor memory element is an element that performs dynamic operations, there is a refresh interrupt, and in this case, the page mode must be interrupted to execute the refresh operation, and it is difficult to perform these controls using an arithmetic unit. Have difficulty. The present invention has been made in order to solve the problems of the prior art as described above, and is a semiconductor memory device that uses a semiconductor memory element that requires a refresh operation without receiving a signal specifying page mode from an arithmetic unit. Its purpose is to control page mode operations in storage devices. The feature of the present invention is that address information is divided into two, a first address information group (row address) and a second address information group (column address), and these address information groups are connected to the same address input pin. In a semiconductor memory device using an address multiplex method in which input is input to a semiconductor memory element with a phase shift, in order to determine the page mode within the semiconductor memory device, the first address information group of the previously executed cycle is A circuit that specifies page mode operation by holding this information until the reception control time of the cycle and comparing it with the first information group of the next cycle, and generating the page mode designation signal when a refresh request is detected. The point is that a circuit is provided to stop the operation. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a semiconductor memory device showing one embodiment of the present invention. The semiconductor memory device 2 includes an address register 3, a refresh generation circuit 4, address selection circuits 5 and 50, an operation mode discrimination circuit 6, an acceptance control circuit 7, a timing circuit 8, a semiconductor memory element 9, and a memory register 10.
When an operation request is made from the arithmetic device 1 to the semiconductor memory device 2, the address information 11 is sent to the address register 3, the operation request signal 12 is sent to the reception control circuit 7, and a decision is made as to whether to perform a write operation or a proposal operation. An R/W signal 14 giving an instruction is sent to the timing circuit 8, and write information 13 is sent to the memory register 10 in the case of a write operation. The semiconductor memory device 2 receives the operation request signal 12 from the arithmetic device 1 and receives the aft signal 21 indicating that the operation is being executed from the reception control circuit 7 and the read information 22 from the memory register 10. Send to 1. An operation request signal 12 is input to the address register 3 and is used as a trigger signal for setting address information 11. Of the set address information, the address register 3 transmits the column address 31 to the address selection circuit 50, and the row address 32 to the address selection circuit 5 and operation mode determination circuit 6, respectively. Refresh generation circuit 4
Then, the refresh request signal 42 is generated and the reception control circuit 7
Then, a refresh address 41 is generated and transmitted to the address selection circuit 5, respectively. The reception control circuit 7 receives the refresh request signal 42, the operation request signal 12, and the timing signal 85 indicating the time when the next operation reception can be started, and controls which request signal is accepted first, and outputs an operation designation indicating the acceptance state. generates the signal 71a and selects the address selection circuit 5.
, the operation mode discrimination circuit 6, and the timing circuit 8, respectively. Further, an operation designation signal 71b indicating the timing generation start time is sent to the timing circuit 8. Also, operation request signal 1
If 2 is accepted, an accept signal 21 is sent to the arithmetic unit 1. The address selection circuit 5 includes a row address 32,
A refresh address 41 and an operation designation signal 71a are input, and the address designated by the operation designation signal 71a is selected and output as a row address 51, and transmitted to the address selection circuit 50. The row address 32, operation designation signal 71a, and timing signal 84 are input to the operation mode determination circuit 6, which determines whether or not to perform page mode operation, outputs a page mode signal 61, and transmits it to the timing circuit 8. In the timing circuit 8, the page mode signal 61
, operation designation signals 71a, b, and R/W signal 14 are input, and the timing for the proposal operation and write operation is generated in the normal operation mode or page mode, and the timing for the refresh operation is generated. As signals, a rast signal 81, a dregs signal 82, and various other timing signals 83 to 87 are output. The last signal 81 is input to the semiconductor memory element 9 and is used as a trigger signal to set row address information of the address information 52 in the semiconductor memory element 9. The cass signal 82 is also used as a trigger signal to set column address information of the address information 52 in the semiconductor storage element 9. The timing signal 83 is a chip select signal, write signal, etc. that specifies the operation mode of the semiconductor memory element 9, and is generated in accordance with the specifications of the semiconductor memory element 9. The timing signal 84 is input to the operation mode determination circuit 6 and is used as a strobe signal to determine whether the address information 11 in the previous cycle and the next cycle match. The timing signal 85 is input to the reception control circuit 7 and is used as a BUSY signal indicating the end of the operation currently being executed and the start of reception of the next operation.
The timing signal 86 is inputted to the memory register 10' and controls the setting, resetting, and sending time of the write information 13, 101 and the discussion information 91, 22. The timing signal 87 is the address selection circuit 5M.
This is input and used as a control signal for switching and outputting the column address 31 and row address 51. Address selection circuit 501 receives column address 31, row address 51, and timing signal 87, outputs row address and column address according to timing signal 87, creates address information 52, and transmits it to semiconductor memory element 9. The address information 52, the last signal, the dreg signal 82, the timing signal 83, and the write information 101 are input to the semiconductor memory element 9, and the operation specified by the timing signal 83 is performed at the address of the semiconductor memory element specified by the address information 52. to be executed. In the case of readout operation, readout information 91
is output and input to memory register 0'. The memory register 10' receives write information 13 from the arithmetic unit 1 and also transmits logic output information 22 to the arithmetic unit 1.
The memory register 1 - 0 also receives draft information 91 from the semiconductor memory element 9 and transmits write information 101 to the semiconductor memory element 9 . Next, a detailed diagram of the operation mode discrimination circuit 6 is shown in FIG.

The row address 321, which is one of the row addresses 32 transmitted from the address register 3, is input as is to one input terminal of the exclusive OR gate 621, and is also input to the inverter 601, the delay element 611, and the inverter 902.
The signal is input to the other input terminal of the exclusive OR gate 621 through the gate. The above circuit is provided for all bits of the row address 32. The output signals of these exclusive OR gates 621 to 62n are input to the input terminal of a NAND gate 631. This nand gate 6
An operation designation signal 71a is input to the input terminal 31.
The output signal of the NAND gate 631 is input to the trigger input terminal T of an edge trigger flip-flop (hereinafter abbreviated as edge trigger FF) 651 and is also input to the input terminal of the inverter 605, and the output signal of the inverter 605 is input to the input terminal of the NAND gate 632. is input. Another timing signal 84 and a reset page signal 663 are input to the input terminal of the NAND gate 632. The output signal of this NAND gate 632 is input to the S input terminal of the edge trigger FF 651. A GNR signal 662, a reset page signal 663, and an operation designation signal 71a are input to the input terminal of the NOR gate 641, and the output signal is sent to the inverter 6.
The output signal of the inverter 606 is input to the R input terminal of the edge IJ FF 651. The D input terminal of the edge trigger FF651 is grounded.
An L level indicating "0" is given.Edge trigger F
A page mode signal 61 is output from the 1 output terminal of F651 and sent to the timing circuit 8. FIG. 4 is a timing chart showing a schematic operation of the semiconductor memory device 2 shown in FIG. 1, which is an embodiment of the present invention.

Operation request signal 1 from operation unit 1 at time Ut, t2, W
2 is sent to the admission control circuit 7 of the semiconductor storage device 2, and a case where a refresh request signal 42 is sent from the IJ fresh generation circuit 4 in the semiconductor storage device 2 to the admission control circuit 7 will be shown as an example. At this time, it is assumed that the row address 32 of the address information 11 is the same in the cycle from time t to t3. First, when the operation request signal 12 is sent to the reception control circuit 7 at time L', since the refresh request signal 42 has not been sent at this time, the operation request signal 1
2 is accepted, the operation designation signal 71a is raised, and is transmitted to the address selection circuit 5, the operation mode determination circuit 6, and the timing circuit 8.

Address selection circuit 5 selects row address 32 since the operation designation signal 71a has been transmitted, and selects row address 5.
The address selection circuit 5 sends the data as 1. The operation mode determination circuit 6 uses a timing signal 8 to determine whether the row address 32 of the cycle in which the operation designation signal 71a is "1" matches the previous cycle and the next cycle.
Check at the time of 4. In this case, the row address 41 before time t is "0" and the time t is "1", so there is a mismatch, and the page mode signal 61 is "0", which is sent to the timing circuit 8. . Since the page mode signal 61 is "0", the timing circuit 8 generates timing for an operation mode that requires a row address and a column address. That is, the timing signal 87 generates two signals, a signal a for selecting a row address and a signal b for selecting a column address, with the phase relationship shown in FIG. 4, and is transmitted to the address selection circuit 5. In the address selection circuit 50, the row address 61 is passed by the timing signal 87a, and the column address 31 is passed by the timing signal 87b.
and transmits them to the semiconductor memory element 9 as address information 52, respectively. Further, the timing circuit 8 sends the rast signal 81 and the dregs signal 82 to the rising semiconductor memory element 9 with the phases shown in FIG. These signals are used to capture address information 52 sent to semiconductor memory element 9. Next, a case will be described in which the operation request signal 12 whose o address 32 is the same as that of the previous cycle is transmitted at time t2 on the falling side of the last signal 81 of the previous cycle starting from L.

First, in the reception control circuit 7, the refresh request signal 42 is “
0'', the operation designation signal 71a is raised and sent to the address selection circuit 5, operation mode discrimination circuit 6, and timing circuit 8 in the same way as the time. In the address selection circuit 5, the row address 32 is used to designate the operation. It is selected by the signal 71a and transmitted to the address selection circuit 5 as the row address 51.In the timing circuit 8, when the operation designation signal 71b rises, the last signal 81 of the previous cycle falls, and it is confirmed that the last signal 81 of the previous cycle does not exist. to generate a timing signal 84 and send it to the operation mode discrimination circuit 6.The operation mode discrimination circuit 6
Now, with respect to the row address 32 of the cycle in which the operation designation signal 71a is "1", it is checked based on the time of the timing signal 84 whether the previous cycle and the next cycle match. In this case, the row address at time t and the row address 32 at time ratio 2 are "1" and have not changed, so it is determined that they match, and the page mode signal 61 is raised.
The signal is sent to the timing circuit 8. The timing circuit 8 prohibits resetting of the last signal 81 which has been set to "1" since the previous cycle, and resets the page mode timing signal 87.
occurs. Since the previous cycle's dregs signal does not inhibit reset, it is pulled down as soon as the cycle ends. The page mode timing signal 87 is raised at an early phase and sent to the address selection circuit 50, as shown in FIG. Only this column address 31 is selected and sent to the semiconductor memory element 9 as address information 52. That is, the cycle at time is shorter than the cycle at time and is executed in cycles. In addition, the timing circuit 8 holds the RAS signal 81 in the "1" state and raises the RAS signal 82 to drive the semiconductor memory element 9.
send to The semiconductor memory element 9 operates on the address specified by the row address specified in the previous cycle and the column address of the address information 52 selected by the currently transmitted dummy signal 82. The operation from time t3 is at time t
The operation is the same as from 2. Next, a case where the IJ fresh request signal 42 is sent to the reception control circuit 7 at a certain time will be explained.

At this time, the paste fresh address 41 is set to "0".
When the refresh request signal 42 is accepted, the operation designation signal 71a is lowered to "0", and this is transmitted to the timing circuit 8 to instruct generation of refresh cycle timing. At this time, the timing generation start time is the operation designation signal 7 transmitted on the line connecting the reception control circuit 7 and the timing circuit 8, similar to the operation designation signal 71a.
1b. A timing circuit 8 generates timing for a refresh cycle. In other words, a timing signal 87a for selecting only the row address is sent to the address selection circuit 501, and the address selection circuit 5 selects the one selected by the operation designation signal 71a or the fresh address 41 sent to the address selection circuit 501 as the row address 51. It is sent to the semiconductor memory element 9 as information 52. Also, in the timing circuit 8, the last cycle's last signal 8
1. After the dregs signal 82 falls, only the rast signal rises,
The process returns to the semiconductor memory element 9 and causes the refresh operation to be executed. Next, the operation of the operation mode discriminating circuit 6 shown in FIG. 2 will be explained using FIG. 3.

Times T2 to T4, T5 to T7, T8 to T, and 2 indicate the case where the row addresses 3 2 1 to 32n do not change.
Also, times T and o are refresh cycles. Time T
7 is a cycle when the page mode time of the semiconductor memory element 9 exceeds the specified value. First, the time span is assumed to be the first operation after the semiconductor memory device 2 is powered on, and the row addresses 321/32n at this time match the initial values. Exclusive or Gate 621~62n
Since the output of is at H level and the operation designation signal 71a is also at H level, the output of NAND gate 631 is at L level, which is inverted by inverter 605, becomes H level, and is applied to the input terminal of NAND gate 632. A timing signal 84 is input to the other input terminal of the NAND gate 632, and this signal becomes H level when the previous cycle was a normal operation and the last signal was not "0". This time, the condition is not satisfied, so it is rated L level. The reset page signal 663 is also connected to the input terminal of the NAND gate 632, and is normally at the H level, but becomes the L level when the page mode signal 61 exceeds the maximum specification for the page mode allowable time of the semiconductor memory element 9. So, this time it's H level. For this reason, an H level signal is output from the NAND gate 632 and applied to the S' input terminal of the edge trigger FF 651, so the state of the edge trigger FF 651 does not change. Note that the GNR signal 662 is connected to one of the R inputs of this edge trigger FF by the NOR gate 6.
41, it is input through the inverter 606, and when the semiconductor storage device 2 is powered on, the GNR signal 662 goes to L level and is reset, so the edge trigger F
One output of F651 is at L level. When the next operation request starts at time T2, since the row addresses 321 to 32n are different between L and T, an H level signal is output from the NAND gate 631, so the edge trigger FF 651 is not set and the page mode is set. It won't be. At time T3, row addresses 321 to 32n are the same as at time T2, so exclusive or gates 621 to 62n
Since the output of NAND gate 631 is at H level and the operation designation signal 71a is also at H level, the output of NAND gate 631 is at L level, which is inverted by inverter 605 and the H level is applied to the input of NAND gate 632. At this time, since the previous cycle was a normal operation and the last signal 81 has not been reset, the evening timing signal 84 becomes an H level signal and is applied to the input of the NAND gate 632. Therefore, an H level signal is output from the NAND gate 632 to set the edge trigger FF 651, and the page mode signal 61 becomes H level to designate page mode. Jihai UT4
At this time, as at time L, the page mode signal 61 is held at the H level. In time UT5, row address 321-3
Since 2n is different from time L, the outputs of the exclusive or gates 621 to 62n go to L level, and the output of NAND gate 631 goes to H level and is added to the T input of the edge trigger FF, thereby changing the H level signal of the D input. When set, the page mode signal 61 becomes L level. At time L, the page mode signal 61 becomes H level with the same operation as at time T3. During the following hours, from 6 to T7, row address 32
Assume that a page operation is executed with 1 to 32n unchanged.

Since the page mode signal 61 exceeds the maximum specification of the allowable page mode time of the semiconductor memory element 9 at the time width 7, when the reset page signal 663 goes to L level, the NAND gate 63
The output of 2 does not go to L level, and the edge trigger FF651
The S' input is not applied, but is applied to the R input, and the page mode signal 61 becomes L level. At time T8, the same operation as at time T2 is performed. Time t is the same as time T3. Time plate. When the refresh request signal 42 is transmitted, the o addresses 321 to 32n are the same as time T9 and the outputs of the exclusive OR gates 621 to 62n become H level, but the operation designation signal 71 becomes L level in the refresh cycle. level, so the output of NAND gate 631 is H.
level, which is added to the T input of the edge trigger FF 651 and sets the page mode signal 61 to the L level. Time T,. Now then, time for the pig. and row addresses 321 to 32n
match, and since the operation designation signal 71a is not a refresh cycle but a normal operation cycle, it becomes H level.
The output of the NAND gate 631 becomes L level, and an H level signal obtained by inverting this by the inverter 605 is applied to the NAND gate 632. At this time, since the previous cycle was a refresh cycle, the timing signal 84 is at H level. Therefore, the output of the NAND gate 632 does not go to the L level, the edge trigger FF 651 is not set, and the page mode signal 61 is kept at the L level. At time T, 2, the same operation as at time t is performed. As described above, according to the present invention, a semiconductor memory device using a semiconductor memory element that requires a refresh operation can be operated in page mode.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a semiconductor memory device showing one embodiment of the present invention. FIG. 2 shows an operation mode discrimination circuit in a semiconductor memory device showing one embodiment of the present invention, and FIG. 3 is a timing chart showing the operation of the operation mode discrimination circuit. FIG. 4 shows a timing chart showing the operation of the semiconductor memory device shown in FIG. DESCRIPTION OF SYMBOLS 1... Arithmetic device, 2... Semiconductor storage device, 3... Address register, 4... Refresh generation circuit, 5, 50... Address selection circuit, 6.
・・Operation mode discrimination circuit, 7・・Reception control circuit, 8・
...Timing circuit, 9...Semiconductor memory element, 10.
...Memory register, 31...Input RAM address, 32,5
1...Row address, 61...Page mode signal. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 A semiconductor memory element that divides address information into two groups, a first address information group and a second address information group, and uses the same address input pin to perform a refresh operation on these address information groups with different phases. In an address multiplex type semiconductor memory device that inputs
a holding circuit that holds the first address information group of the previous operating cycle until the next operating cycle; and a holding circuit that holds the first address information group of the current operating cycle and the first address information group of the previous operating cycle held by the holding circuit. If the comparison circuit matches the comparison circuit that compares the address information group with the address information group, the input of the first address information group to the semiconductor memory element in the current operation cycle is omitted, and only the second address information group is transferred to the semiconductor memory. A circuit that generates a signal specifying a page mode to be input to an element, a circuit that generates a refresh request, and a circuit that stops generating the page mode specifying signal when a refresh request from the refresh request generating circuit is detected in the current operation cycle. A semiconductor memory device comprising: