KR19990003698A - Transmission signal generator of line length encoder - Google Patents

Abstract

In the present specification, an apparatus for generating a transmission signal in a line length encoder is disclosed.

Such an apparatus includes a multiplexer 410 for selecting odd DCT coefficients or even DCT coefficients according to a system clock; A zero coefficient detector 420 for detecting that the DCT coefficient output by the multiplexer is zero; A level counter 430 for counting non-zero coefficients at the output of the zero coefficient detector according to the second clock; And a comparator 440 for generating a transmission signal by comparing the count value output by the level counter with a predetermined reference value.

In the transmission signal generating apparatus of the present invention configured as described above, when three or more (run, level) are generated when a pair of pixels are encoded by one system clock to generate (run, level), two ( By sending run and level, the transmission speed can be improved.

Description

A write signal generator for run length coder

The present invention relates to a run length coder (RUN LENGTH CODER) for removing statistical redundancy of image data during compression encoding of image data. More specifically, Discrete Cosine Transform (hereinafter referred to as DCT) And a line length coder for quantizing DCT coefficient values into a two-dimensional symbol consisting of a number of coefficients having a value of '0' and a coefficient value other than '0' immediately following.

In general, since the modern society is also called an information society, the amount of information to be processed is increasing day by day, and in order to effectively use the existing transmission band, data to be transmitted must be compressed. In particular, in the case of digital video signals, since the amount of information is very large, it is essential to compress the video data in order to more efficiently store, retrieve, and transmit information.

For this reason, many compression techniques for image data have been developed, and this image data compression technique reduces the amount of data required to display an image by removing spatial redundancy, temporal redundancy, and statistical redundancy of the image signal.

Such image data compression techniques include intraframe encoding to remove spatial redundancy present in still images (in the same frame), and interframe elimination for removing temporal redundancy present in video (between consecutive frames). Can be divided into (interframe) coding.

Intra-frame coding for removing spatial redundancy includes discrete cosine transform coding (DCT) and quantization, which are a type of transform coding, and an example of inter-frame coding for removing the temporal redundancy is temporal. For example, motion estimation / compensation coding may be performed by estimating and compensating for motion between two adjacent screens.

The DCT and quantized DCT coefficient values are entropy-encoded to remove statistical redundancy. That is, the entropy coding refers to a lossless coding algorithm for minimizing the bit rate by using statistical characteristics since the frequency of occurrence of quantized pixels is distributed differently.

Such entropy coding techniques include Run Length Coding (RLC), Variable Length Coding (VLC) using Huffman Coding, and Bit Plane Coding (BPC). However, line length coding and variable length coding are widely used.

Here, line length coding (RLC) is mainly used to increase the compression efficiency of transform coding such as Discrete Cosine Transform Coding (DCT). In general, when looking at the DCT coefficients generated by the DCT conversion of the video signal, it can be seen that most of the energy is concentrated in the low frequency coefficient and the high frequency coefficients are nearly zero. Accordingly, when the quantized DCT coefficients are zig-zag scanned and sorted from low frequency to high frequency, a relatively long '0' one-dimensional data string is created. RLC creates a two-dimensional symbol of (run, level) consisting of the number of '0's continuing in the data sequence created above and the non-zero coefficient values immediately following it.

The length coding is mainly used to increase the compression efficiency of transform coding such as Discrete Cosine Coding (DCT). DCT coefficients are generally concentrated at low energy, and high frequency components are almost '0'. Zig-zag scan is used to create a one-dimensional column of '0' data as long as possible, followed by a number of '0's and a non-zero count value immediately following it. It is to create a composed two-dimensional symbol.

In addition, the variable length coding is a technique of allocating a small bit to a symbol that is frequently generated according to a probability distribution of a symbol to be encoded, and assigning a large number of bits to a symbol having a low frequency of occurrence, thereby minimizing the bit generation rate as a whole. There are many kinds of such variable length coding, but Huffman coding which is easy to implement is now widely used.

1 is a block diagram schematically showing the configuration of a general video encoder, and is used in many standardized encoders such as H.261, MPEG-1, and MPEG-2. That is, the discrete cosine transforming unit (DCT) 11 outputs a discrete cosine transform coefficient (DCT coefficient) by performing discrete cosine transforming of the inter-frame difference image into a block of 81 * 8 pixels, for example, to remove the correlation between pixels. The quantizer 12 quantizes and outputs the discrete cosine transform coefficients (DCT coefficients) of the interframe difference image output from the discrete cosine transforming unit 11 to a predetermined quantization step size.

The quantized DCT coefficients quantized by the quantizer 12 are converted into a one-dimensional data stream through a zig-zag scanning process, input to a line length encoder 14, and the line length encoder 14 is a zig-zag scanned DCT coefficient. Is coded into the variable length encoder 15, and the variable length encoder 15 variable length codes the data length-encoded by the line length encoder 14 using a Huffman table and then buffers the data. Will not be printed).

In this case, when the input data is an Intra DC coefficient, the line length encoder 14 outputs a DC size and a DC difference, and the remaining coefficients are immediately followed by the number of '0's. Creates and outputs a 2D symbol of (run, level) consisting of consecutive nonzero values. That is, in the case of the Intra DC coefficient, the difference value between the DC coefficients of neighboring blocks is encoded. The DC coefficient is divided into a DC size and a DC difference. If the DC size is '0', only a DC size code is transmitted. If the size of is not '0', then the DC difference value is transmitted by the number of bits of the DC size.

In addition, the remaining coefficients except the Intra DC coefficient are aligned in one dimension mainly through a zigzag scan. Here, zero-run and zero-level coefficients (level values) in which '0' appears consecutively are expressed in two dimensions of (run, level). For example, a zigzag scan can be performed, such as 30, 2, 0, 0, -8. 0, 0, 0, 9 DCT coefficients aligned like 0f0f0f are passed through the line length encoder 14 such that (0, 30), (0, 2), (2, -8), (3, 9) 0f0f0f Is expressed.

In addition, when the zig-zag scanned coefficients continue to end after a position, '0' is added, an end of block (EOB) sign indicating the end of the block is added. In addition, a transmission signal for storing the (run, level) value generated as described above in a first-in first-out buffer (FIFO) should be generated.

As shown in FIG. 2, the transmission signal generator of the conventional line length encoder for processing two pixels in one system clock in the image encoder as described above is an idle signal generator 21, a zero coefficient detector 22, and a controller. 23, the holding section 24, and the transmission signal output section 25.

Referring to FIG. 2, the zero coefficient detection unit 22 receives odd DCT coefficients and even DCT coefficients, and outputs 0 when the coefficient is 0 and 1 when the coefficient is 0 (w1, w2), and the controller 23 performs the zero coefficient. A transmission signal write is generated according to the output of the detector 22, and the holding unit 24 holds the write signal.

The idle signal generator 21 receives the block start signal and the block end signal, generates an idle signal while the block is being processed, disables the transmission signal output unit 25, and then detects the block end signal. The transmission signal output unit 25 is enabled to output the transmission signal hwrite held by the holding unit 24. The (run, level) values generated by the line length encoder are written to a FIFO (not shown) according to the generated transmission signal.

The conventional transmission signal generator operating as described above cannot be output together with an end signal (EOB) which should be output as soon as the (run, level) is generated when it is the last event. You must wait until it occurs before sending.

That is, as shown in FIG. 3, the block start signal is input, and then (run, level) generated because all the (run, level) of the input coefficients are generated and then the transmission signal is generated together with the block end signal. ) Has a problem that the transmission of the delay. For example, after the first two (run, level) pairs are generated, such as 0,1,0,5, 0,0,0, ...... Since the end signal (EOB) has to be transmitted, there is a problem in that the transmission of the run (level) is delayed when the processing of one block is completed. In FIG. 3, (a) is a block start signal, (b) represents a system clock, and (c) and (d) represent a pair of runs and levels. (E) indicates an EOB signal generated at the timing at which the line length coding for one block ends, and (B) indicates a transmission signal.

The present invention has been made to solve the above-mentioned conventional problems, and when two or more (run, level) are generated, two (run, level) generated first are transmitted in advance to reduce the transmission delay. It is an object of the present invention to provide a transmission signal generator for a line length encoder.

The apparatus of the present invention for achieving the above object, at least three (run) by receiving an odd DCT coefficient and an even DCT coefficient in accordance with the system clock in an image encoder designed to process a pair of pixel data in a system clock In the transmission signal generator of a line length encoder which generates a transmission signal and transmits two (run, level) first when the level is generated, selecting an odd DCT coefficient or an even DCT coefficient according to the system clock. Multiplexer; A zero coefficient detector for detecting that the DCT coefficient output by the multiplexer is zero; A level counter for counting nonzero coefficients at the output of the zero coefficient detector according to a second clock; And a comparator for generating a transmission signal by comparing the count value output by the level counter with a predetermined reference value.

1 is a block diagram showing a general video encoder,

2 is a block diagram showing a transmission signal generator of a conventional line length encoder;

3 is a timing diagram showing a timing at which a transmission signal is conventionally generated;

4 is a block diagram showing an apparatus for generating a transmission signal of a line length encoder according to the present invention;

5 is another embodiment of the level counter shown in FIG.

6 is a timing diagram for explaining the operation of the transmission signal generator according to the present invention.

* Explanation of symbols for main parts of the drawings

410: multiplexer 420: zero coefficient detection unit

430: zero counter 432: binary counter

434: summer 436,438: flip-flop

440: comparator

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an image encoder to which the present invention can be applied. The image encoder includes a DCT 11, a quantizer 12, a zigzag scanning unit 13, a line length encoder 14, a variable length encoder ( 15) is included. In the exemplary embodiment of the present invention, the zigzag scanning unit 13 performs zigzag scanning of the quantized DCT coefficients, and the line length encoder 14 receives a pair of pixels sequentially to generate (run, level) pairs and then the variable length encoder Output to (15). In general, the DCT coefficient inputted to the run value generator is a DCT coefficient inputted by a discrete cosine transform in 8x8 block units, quantized by a quantizer, zigzag-scanned, and inputted by 2 pixels in a system clock. Therefore, one block is composed of 64 DCT coefficients, and one block of pixels is processed by 32 system clocks.

4 is a block diagram showing a transmission signal generator according to the present invention. As shown in FIG. 4, the transmission signal generator of the present invention includes a multiplexer 410, a zero coefficient detector 420, a level counter 430, and a comparator 440.

The multiplexer 410 selects and outputs an odd DCT coefficient when the system clock CLK1 is high, and selects and outputs an even DCT coefficient when the system clock CLK1 is high. The zero coefficient detector 420 outputs 0 when the input DCT coefficient is 0, and outputs 1 when the input DCT coefficient is 0.

The level counter 420 counts the number of times a (run, level) pair is generated. The level counter 420 may be implemented as a preset binary counter 432. At this time, since the number of (run, level) pairs generated as a result of the line length encoding is equal to the number of non-zero values of the DCT coefficient, that is, the number of levels, the first clock outputting 1 by the zero coefficient detection unit 420 is the second clock. By counting according to (CLK2), the number of (run, level) pairs can be counted. Therefore, the count value output by the level counter 420 is equal to the number of line length coded (run, level) pairs when the length length coding of the DCT coefficient of the corresponding block is performed sequentially. The second clock CLK2 is a clock in which the system clock CLK1 is divided into two (ie, a clock twice as fast as the system clock).

The preset binary counter 432 implementing the level counter 430 has a count value cleared to 0 by a block start signal, and counts 1 output by the zero coefficient detector 420 according to the second clock CLK2. Calculate the number of levels. When a preset signal is input, 1 is preset.

The comparator 440 compares the count value output by the level counter 430 with a preset 3, outputs a transmission signal when the count value is 3, and provides a preset signal to the level counter 430.

Therefore, when the number of (run, level) that is generated when the DCT coefficients are sequentially encoded by the line length is three, a transmission signal (light signal) is generated, and the two (run, level) pairs generated first are written to an unshown FIFO. This can reduce the transmission delay.

FIG. 5 is another embodiment of the level counter shown in FIG. 4. As shown in FIG. 5, the level counter 430 for counting the number of (runs, levels) generated as a result of the line length encoding may be implemented by a summer 434 and a deflip-flop 436 and 438. When 1 is input from the zero coefficient detection unit 434, the sum of the output of the first deflip-flop 438 is output to the comparator 440. At this time, since the first deflip-flop 438 is cleared to 0, the summer 434 outputs 1 + 0 = 1, and this output (ie, 1) is again the first deflip-flop 438. Are stored in. Subsequently, when '1' is input from the zero coefficient detector 420 to the next clock, the summer 434 outputs 1 + 1 = 2 (10 ₂ ). In this case, 2 is stored in the first flip-flop 438, and when 1 is input from the zero coefficient detector 420 to the next clock, the summer outputs 2 + 1 = 3. The comparator 440 outputs a low signal, and when the output of the summer 434 becomes 3, the comparator 440 outputs a high signal to generate a transmission signal. Accordingly, the first deflip-flop 438 is cleared to 0, and the second The deflip-flop 436 outputs 1 to the summer 434. When the transmission signal is generated, two out of three (run, level) are transmitted to the FIFO, and one (run, level) remains, so that the comparator 440 outputs the transmission signal, 434 sums the value 1 output from the second deflip-flop 436 and the value output from the zero coefficient detection unit 420, and the output is stored in the first deflip-flop 438. The summer 434 adds the output of the first deflip-flop 438 to the output of the zero coefficient detector 420 until is generated.

Next, the operation of the present invention configured as described above will be described in detail with reference to the timing diagram shown in FIG.

In the embodiment of the present invention, the line length coder is inputted with 0, 0, 0, L1, 0, L2, 0, 0, L3, L4, L5, L6, 0 .... (3, L1). The line lengths are encoded by (1, L2), (2, L3), (0, L4), (0, L5), (0, L6). In FIG. 6, (a) shows the system clock CLK1, (b) shows the second clock CLK2 divided into two system clocks, and (c) shows the output of the multiplexer (410 in FIG. 4). Indicates. In FIG. 6C, the output of the multiplexer indicates odd DCT coefficients when the system clock CLK1 is high and even DCT coefficients when the system clock CLK1 is high. 6 (d) shows a low value when the DCT coefficient input as an output of the zero coefficient detection unit 420 is 0, and a high value when the DCT coefficient is 0. As shown in (e) of FIG. 6, the count value of the level counter 430 counts 1 output from the zero coefficient detector 420 according to the second clock CLK2. do.

When the count value of the level counter 430 becomes 3, the comparator 440 outputs the transmission signal high and provides the preset signal to the level counter 430. Accordingly, the count value of the level counter is preset to 1 It can be seen that.

As described above, when the transmission signal generator of the line length encoder according to the present invention generates (run, level) by encoding a pair of pixels in one system clock, three or more (run, level) are generated. Therefore, the transmission speed can be improved by transmitting two (run, level) generated first.

Claims (3)

In an image encoder designed to process a pair of pixel data in one system clock, an odd DCT coefficient and an even DCT coefficient are input according to the system clock, and when at least three (run, level) are generated, a transmission signal is generated. A transmission signal generator of a line length encoder configured to transmit two (run, level), comprising: a multiplexer (410) for selecting odd DCT coefficients or even DCT coefficients according to the system clock; A zero coefficient detector 420 for detecting that the DCT coefficient output by the multiplexer 410 is zero; A level counter 430 for counting non-zero coefficients at the output of the zero coefficient detector according to a second clock; And a comparator (440) for generating a transmission signal by comparing the count value output by the level counter (430) with a predetermined reference value. The apparatus of claim 1, wherein the level counter (430) is implemented as a preset binary counter (432). The zero coefficient detecting unit of claim 1, wherein the level counter 430 is configured to temporarily store a first cleared flop 438 that is cleared and summed according to a transmission signal, and an output of the first deflected flop. A length consisting of a summer 434 for summing with the output of 420 and a second deflip-flop 436 for providing 1 to the summer 434 at the first clock after the transmission signal is generated. Transmission signal generator of encoder.