KR100251309B1 - End of block signal generator for run length coder - Google Patents

Abstract

PURPOSE: An apparatus for generating an end signal of a run length coder is provided to output an EOB(End of Block) signal after adding (0,0) if an odd number of (run, level) is generated in one block, thereby easily fitting timing in a variable length coder. CONSTITUTION: An odd/even detecting part(310) detects whether the number of (run, level) generated by run length-coding DCT(Discrete Cosine Transform) coefficients of one block is an odd number or an even number. An end timing detecting part(320) detects run length coding ending timing to the DCT coefficients of one block. The second multiplexor(330) provides a predetermined logic value or the output of the odd/even detecting part(310) according to the output of the end timing detecting part(320). The third multiplexor(332) outputs the second run or 0 generated at a run value generating part(340) according to the output of the second multiplexor(330). The fourth multiplexor(334) outputs the second level or 0 generated at a level value generating part(350) according to the output of the second multiplexor(330).

Description

End signal generator of line length encoder

The present invention relates to a run length coder (RUN LENGTH CODER) for removing statistical redundancy of image data during compression encoding of image data. More specifically, Discrete Cosine Transform (hereinafter referred to as DCT) And a line length coder for quantizing DCT coefficient values into a two-dimensional symbol consisting of a number of coefficients having a value of '0' and a coefficient value other than '0' immediately following.

In general, since the modern society is also called an information society, the amount of information to be processed is increasing day by day, and in order to effectively use the existing transmission band, data to be transmitted must be compressed. In particular, in the case of digital video signals, since the amount of information is very large, it is essential to compress the video data in order to more efficiently store, retrieve, and transmit information.

For this reason, many compression techniques for image data have been developed, and this image data compression technique reduces the amount of data required to display an image by removing spatial redundancy, temporal redundancy, and statistical redundancy of the image signal.

Such image data compression techniques include intraframe encoding to remove spatial redundancy present in still images (in the same frame), and interframe elimination for removing temporal redundancy present in video (between consecutive frames). Can be divided into (interframe) coding.

Intra-frame coding for removing spatial redundancy includes discrete cosine transform coding (DCT) and quantization, which are a type of transform coding, and an example of inter-frame coding for removing the temporal redundancy is temporal. For example, motion estimation / compensation coding may be performed by estimating and compensating for motion between two adjacent screens.

The DCT and quantized DCT coefficient values are entropy-encoded to remove statistical redundancy. That is, the entropy coding refers to a lossless coding algorithm for minimizing the bit rate by using statistical characteristics since the frequency of occurrence of quantized pixels is distributed differently.

Such entropy coding techniques include Run Length Coding (RLC), Variable Length Coding (VLC) using Huffman Coding, and Bit Plane Coding (BPC). However, line length coding and variable length coding are widely used.

Here, line length coding (RLC) is mainly used to increase the compression efficiency of transform coding such as Discrete Cosine Transform Coding (DCT). In general, when looking at the DCT coefficients generated by the DCT conversion of the video signal, it can be seen that most of the energy is concentrated in the low frequency coefficient and the high frequency coefficients are nearly zero. Accordingly, when the quantized DCT coefficients are zig-zag scanned and sorted from low frequency to high frequency, a relatively long '0' one-dimensional data string is created. RLC creates a two-dimensional symbol of (run, level) consisting of the number of '0's continuing in the data sequence created above and the non-zero coefficient values immediately following it.

The length coding is mainly used to increase the compression efficiency of transform coding such as Discrete Cosine Coding (DCT). DCT coefficients are generally concentrated at low energy, and high frequency components are almost '0'. Zig-zag scan is used to create a one-dimensional column of '0' data as long as possible, followed by a number of '0's and a non-zero count value immediately following it. It is to create a composed two-dimensional symbol.

In addition, the variable length coding is a technique of allocating a small bit to a symbol that is frequently generated according to a probability distribution of a symbol to be encoded, and assigning a large number of bits to a symbol having a low frequency of occurrence, thereby minimizing the bit generation rate as a whole. There are many kinds of such variable length coding, but Huffman coding which is easy to implement is now widely used.

1 is a block diagram schematically showing the configuration of a general video encoder, and is used in many standardized encoders such as H.261, MPEG-1, and MPEG-2. That is, the discrete cosine transforming unit (DCT) 11 performs discrete cosine transforming of the inter-frame difference image into a block of 8 ?? 8 pixels, for example, to remove the correlation between the pixels. The quantizer 12 quantizes and outputs the discrete cosine transform coefficients (DCT coefficients) of the interframe difference image output from the discrete cosine transform unit 11 to a predetermined quantization step size.

The quantized DCT coefficients quantized by the quantizer 12 are converted into a one-dimensional data stream through a zig-zag scanning process, input to a line length encoder 14, and the line length encoder 14 is a zig-zag scanned DCT coefficient. Is coded into the variable length encoder 15, and the variable length encoder 15 variable length codes the data length-encoded by the line length encoder 14 using a Huffman table and then buffers the data. Will not be printed).

In this case, when the input data is an Intra DC coefficient, the line length encoder 14 outputs a DC size and a DC difference, and the remaining coefficients are immediately followed by the number of '0's. Creates and outputs a 2D symbol of (run, level) consisting of consecutive nonzero values. That is, in the case of the Intra DC coefficient, the difference value between the DC coefficients of neighboring blocks is encoded. The DC coefficient is divided into a DC size and a DC difference. If the DC size is '0', only a DC size code is transmitted. If the size of is not '0', then the DC difference value is transmitted by the number of bits of the DC size.

In addition, the remaining coefficients except the Intra DC coefficient are aligned in one dimension mainly through a zigzag scan. Here, zero-runs and zero-level coefficients of zero levels are expressed in two dimensions (run and level). For example, a zigzag scan can be performed, such as 30, 2, 0, 0, -8. DCT coefficients arranged as 0, 0, 0, 9 ?? are obtained by (0, 30), (0, 2), (2, -8), (3, 9) ?????? It is expressed as

In addition, when the zig-zag scanned coefficients continue to end after a position, '0' is added, an end of block (EOB) sign indicating the end of the block is added. In addition, a transmission signal for storing the (run, level) value generated as described above in a first-in first-out buffer (FIFO) should be generated.

As shown in FIG. 2, the conventional end signal generator in the image encoder generates an end (EOB) signal when the counter 22 counts the system clock according to the block start signal and the counter counts 64 (or 32). It consists of the end signal generator 24.

However, such a conventional end signal generator processes two pixels in one system clock and outputs two (run, level), and an odd (run, level) is generated when an odd number of (run, level) occurs. There is a problem in that the timing of processing the end signal in the variable length encoder is changed by adding an EOB without distinguishing a case where this occurs. That is, when (run, level) ends in an odd number, it is preferable to match timing with an even number by ending (0, 0) after the last (run, level) and then adding an EOB.

Accordingly, the present invention has been made to solve the above-described problems, and when the line length coding for the corresponding block ends with an odd number of (run, level) in processing two pixels in one system clock. It is an object of the present invention to provide an end signal generator that is configured to generate an end signal after adding a predetermined (run, level).

The apparatus of the present invention for achieving the above object, in the image encoder designed to perform discrete cosine transform in a block unit formed by a predetermined number of pixels, and to process a pair of DCT coefficients obtained as a result of the discrete cosine conversion in a system clock pair An apparatus in which a run value generator provides a first run and a second run by receiving an odd DCT coefficient and an even DCT coefficient according to a system clock, and the level value generator provides a first level and a second level. An odd / even detection unit for detecting whether the number of (run, level) generated by the length-length encoding of the DCT coefficients is odd or even; An end timing detector for detecting a line length encoding end timing of the one block of DCT coefficients; A second multiplexer for providing a predetermined logic value or an output of the odd / even detection unit according to the output of the termination timing detection unit; A third multiplexer for outputting a second run or zero generated by the run value generator in accordance with the output of the second multiplexer; And a fourth multiplexer for outputting a second level or zero generated by the level generator according to the output of the second multiplexer.

1 is a block diagram showing a general video encoder,

2 is a block diagram showing an end signal generator of a conventional line length encoder;

3 is a block diagram showing an end signal generator of the line length encoder according to the present invention.

* Explanation of symbols for main parts of the drawings

310: odd / even detection unit 312: first multiplexer

314: zero coefficient detection unit 318: flip-flop

316: summer 320: end timing detector

322: counter 324: comparator

330: second multiplexer 332: third multiplexer

334: fourth multiplexer 340: run value generator

342: First run output unit 344: Second run output unit

350: level generator 352: first level output

354: second level output unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an image encoder to which the present invention can be applied. The image encoder includes a DCT 11, a quantizer 12, a zigzag scanning unit 13, a line length encoder 14, a variable length encoder ( 15) is included. In the exemplary embodiment of the present invention, the zigzag scanning unit 13 performs zigzag scanning of the quantized DCT coefficients, and the line length encoder 14 receives a pair of pixels sequentially to generate (run, level) pairs and then the variable length encoder Output to (15).

In the embodiment of the present invention, the DCT coefficient input to the line length encoder 14 is quantized by the quantizer 12 after the input pixel is discrete cosine transformed in 8x8 block units, and is zigzag scanned and 2 pixels in one system clock. Input DCT coefficient. Therefore, one block is composed of 64 DCT coefficients, and one block of pixels is processed by 32 system clocks.

3 is a block diagram showing an end signal generator according to the present invention. As shown in FIG. 3, the end signal generator of the present invention includes a hole / pair detector 310, an end timing detector 320, and a multiplexer 330. The first multiplexer 312, the zero coefficient detector 314, the adder 316, and the flip-flop 318 are included. The end timing detector 320 includes a counter 322 and a comparator 324. In addition, the first run output unit 342 and the second run output unit 344 are connected to the run value generator 340, and the second run output unit 344 is configured to select a second run or zero. The three multiplexer 332 is connected, and the first level output unit 352 and the second level output unit 354 are connected to the level value generator 350. Is connected to a fourth multiplexer 334 for selecting a second level or zero.

That is, the first run generated by the run value generator 340 is output as it is through the first run output unit 342, but the second run is connected to the second run output unit 344 by the third multiplexer 332. The first level generated by the level value generator 350 is output through the first level output unit 352 as it is, but the second level is connected to the second level output unit 354 by a fourth multiplex. It is output through the book 334. Therefore, when the length length encoding for the block is completed, the third and fourth multiplexers are counted if the number of (run, levels) generated by the length coding of the block is odd. (0,0) is output through (332,334), and the second run and the second level are output as they are (if not at the end or even at the end).

Referring to FIG. 3, the first multiplexer 312 receives an odd DCT coefficient or an even DCT coefficient according to the first clock CLK1. In the exemplary embodiment of the present invention, when the first clock CLK1 is high, an odd DCT coefficient is input and processed. When the first clock CLK1 is low, an even DCT coefficient is input and processed.

The zero coefficient detection unit 314 is implemented as a logic circuit to determine whether the odd DCT coefficient or even DCT coefficient output by the first multiplexer 312 is zero, and outputs "0" if zero, and zero Otherwise, print "1". At this time, since the first multiplexer 312 outputs odd DCT coefficients during the high of the first clock CLK1 and even DCT coefficients during the low of the first clock CLK1, the zero coefficient detector 314 outputs 2 during the first clock CLK1. It should be possible to check one input DCT coefficient one by one.

The summer 316 is a 1-bit summer that outputs 0 or 1, and adds " 1 " output from the zero coefficient detection unit 314 to the output of the deflip-flop 318. The reason why the count of the zero coefficient detector 314 is counted is that the number of (run, level) generated by the line length coding is equal to the number of non-zero DCT coefficients. The deflip-flop 318 stores the value output from the 1-bit summer 316 and feeds it back to the summer 316. Therefore, the 1-bit summer 316 outputs "1" if the number of 1s (that is, the number of [run, level]) output by the zero coefficient detector 314 outputs "1" for odd number and "0" for even number. do.

The counter 322 clears the count value in the block start signal and counts a predetermined number according to the system clock, and the comparator 324 converts the count value output by the counter 322 to a predetermined value (for example, one system clock). The line length of the block is compared with 64 corresponding to the DCT coefficient of one block when processing 1 pixel and 32 corresponding to the number of DCT coefficients of one block when processing 2 pixels per system clock. "1" is output at the timing when encoding ends.

The second multiplexer 330 outputs a fixed value "0" when 0 is input from the comparator 324, and selects and outputs an output of the summer 316 when 1 is input at the end point. In this case, the summer 316 outputs 1 when the (run, level) of the corresponding block is odd and 0 when the even block is even.

The third and fourth multiplexers 332 and 334 connected to the second run output unit 344 and the second level output unit 354 output the second run when the value of the second multiplexer 330 outputs zero. The outputs of the negative and second level output units 344 and 354 are selected and output, respectively, and if "1", "0" is selected and output respectively. Therefore, if an odd number of (run, level) occurs in the line length encoder, (0,0) is output after the last (run, level).

As described above, the end signal generator of the line length encoder according to the present invention uses a clock that is twice as fast as the system clock to process the pixel data inputted in pairs to one system clock. If an odd number of (run, level) is generated at, then (0,0) is added, and then an EOB signal is output, which makes it possible to easily hide timing in a variable length encoder.

Claims (3)

Discrete cosine transform is performed in units of blocks formed by a predetermined number of pixels, and an image encoder designed to process the DCT coefficients obtained as a result of the discrete cosine pair by one system clock is inputted with an odd DCT coefficient and an even DCT coefficient according to the system clock. In the apparatus in which the run value generator 340 provides the first run and the second run, and the level value generator 350 provides the first level and the second level, An odd / even detection unit (310) for detecting whether the number of (run, level) generated by the length-length coding of the DCT coefficients of the block is odd or even; An end timing detector 320 for detecting a line length encoding end timing of the DCT coefficients of the one block; A second multiplexer 330 which provides a predetermined logic value or an output of the odd / even detector according to the output of the end timing detector; A third multiplexer 332 for outputting a second run or zero generated by the run value generator according to the output of the second multiplexer; And And a fourth multiplexer (334) for outputting a second level or zero generated by the level generator in accordance with the output of the second multiplexer. The method of claim 1, wherein the odd / even detection unit 310 comprises: a first multiplexer 312 for selecting and outputting an odd DCT coefficient or an even DCT coefficient according to a system clock; A zero coefficient detection unit for determining whether the DCT coefficient output by the first multiplexer is zero and outputting a predetermined value; An adder 316 for summing outputs of the zero coefficient detector; And a deflip-flop (318) for temporarily storing the output of said summer and feeding it back to said summer. 2. The apparatus of claim 1, wherein the end timing detector (320) clears the count value according to the block start signal and counts a system clock; And a comparator (324) for comparing the output of said counter with a predetermined value.

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