KR100195726B1 - A circuit for initially driving run-length decoder - Google Patents

Abstract

The present invention relates to an initial driving circuit for a line length decoder, comprising: a first AND gate (30) for ANDing a read enable signal (RE) and a frame synchronization signal (Frame-sync); An initial read request signal for generating and outputting an initial read request signal fir-rrq for receiving the signal output from the first AND gate 30 and the system reset signal sys-rst to output the data of the first-in first-out buffer. A generating unit 40; An active signal generator for receiving a signal output from the first AND gate 30 and a frame end signal or the system reset signal sys_rst and outputting an active signal for performing line length decoding; It is configured to include 50, and can initially drive the line length decoder when the power is turned on.

Description

Line length decoder initial drive circuit

1 is a schematic block diagram of a general video encoder.

2 is a schematic block diagram of a general video decoder.

3 is a schematic block diagram of a general string length decoder.

4 is a circuit diagram of a line length decoder initial driving circuit according to the present invention.

5 is a timing diagram of a string length decoder initial driving circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

1: discrete cosine transform unit 2: quantizer

3: line length encoder 4: variable length encoder

5 variable length decoder 6 line length decoder

7: reverse scanning unit 8: inverse quantizer

9: inverse discrete cosine transform unit 10: variable length decoder

15: First-in, first-out buffer 20: Line length decoder

30: first end gate 40: initial lead request signal generator

42: first oragate 44: first D-flip flop

46: second AND gate 50: active signal generator

52: second oragate 54: second D-flip flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for initially driving a string length decoder, and more particularly, to a string length decoder initial drive circuit for driving a string length decoder when a power is turned on.

In general, since modern society is also called an information society, since the amount of information to be processed is increasing day by day, data must be compressed to effectively use the existing transmission band.

In particular, in the case of digital video signals, since the amount of information is very large, it is necessary to compress the video data in order to more efficiently store, retrieve, and transmit the information.

For this reason, many compression techniques for image data have been developed. To summarize the compression of image data, the amount of data required to display an image is reduced by eliminating spatial, temporal redundancy, and statistical redundancy.

The image data compressor method can be classified into loss coding and lossless coding according to whether information is lost. Intra-frame coding and temporal redundancy present in video to remove spatial redundancy present in still images It can be divided into interframe encoding to remove.

Intra-frame encoding for removing spatial redundancy includes discrete cosine transform coding (DCT) and quantization, which are a type of transform encoding, and an example of inter-frame encoding for removing the temporal redundancy is two temporally adjacent screens. Motion estimation / compensation coding to remove temporal amplification by estimating and compensating the motion of the liver.

In addition, by performing entropy coding on coefficient values that have undergone the discrete cosine coding (DCT) and quantization, statistical redundancy is removed.

That is, the entropy coding refers to a lossless coding algorithm for minimizing the bit rate by using a statistical property that a frequency of occurrence of quantized pixels is distributed differently and their entropy is smaller than B, and a code smaller than Bbpp exists. .

Such entropy coding techniques include Variable Length Coding (VLC), Run Length Coding (RLC), and Bit Plane Coding (BPC) using Huffman coding. However, variable length coding and line length coding are most widely used.

The variable length coding is a technique of minimizing the bit generation rate by allocating small bits to symbols that are frequently generated according to the probability distribution of the symbols to be encoded, and assigning many bits to symbols with low occurrences.

There are many kinds of such variable length coding, but Huffman coding that is easy to implement is most widely used.

In addition, the line length coding is mainly used to increase the compression efficiency of transform coding such as Discrete Cosine Coding (DCT). The transformed DCT coefficients are generally concentrated at low energy frequencies and high frequency components are almost zero. Zig-zag scans are made as long as possible, resulting in a one-dimensional column of zero-dimensional data as long as possible, followed by a two-dimensional symbol consisting of the number of consecutive zeros and non-zero coefficients immediately following it. will be.

FIG. 1 is a block diagram schematically illustrating the structure of a general video encoder, and is used in many standardized encoders such as H.261, MPEG-1, and MPEG-2.

In other words, the discrete cosine transforming unit (DCT) 1 outputs a discrete cosine transform coefficient by performing discrete cosine transforming of the inter-frame difference image into a block of 8x8 pixels, for example, to remove the correlation between pixels. In (2), the discrete cosine transform coefficients of the inter-frame difference image output from the discrete cosine transforming unit 1 are quantized and output at a predetermined quantization interval.

The DCT coefficients quantized by the quantizer 2 are converted into a one-dimensional data string through a zig-zag scanning process, input to a line length encoder 3, and the line length encoder 3 is subjected to a zig-zag scanning process. Makes the output data stream two-dimensional (run, level) consisting of the number of consecutive zeros and non-zero coefficient values immediately following it.

The length coded data in the length coder 3 is variable length coded by the Huffman table in the variable length coder 4 and then output to a video buffer (not shown).

At this time, the DC coefficient and the AC coefficient among the DCT coefficients are distinguished and encoded in another method. Usually, the DC value of each block is highly correlated with the DC value of the neighboring block. Therefore, the difference between the DC value of the previous block is obtained and the difference value is encoded. Encode the difference between and. The DC difference values thus obtained are encoded by one-dimensional variable length coding.

That is, the DC coefficient is variable length coded by dividing the DC size (dct-dc-size) and the DC difference (dct-dc-differential), but if the DC size (dct-dc-size) is 0, the DC size (dct Only the code of -dc-size is transmitted, and if it is not 0, then the DC difference (dct-dc-differential) is transmitted by the number of bits of the DC size (dct-dc-size).

In addition, AC reorders the coefficients for more efficient data compression by taking advantage of the fact that the AC coefficient near the DC coefficient is not zero in the DCT region and that the zero is more likely to be away from the DC. Align in one dimension via zig-zag scan. Here, zero-run and zero-level coefficients are expressed in two dimensions (run, level).

For example, with a zig-zag scan, the aligned DCT coefficients, such as 30,2,0,0, -8,0,0,0,9 ..., are passed through the line length encoder 6 (0, 30), (0.2), (2, -8), (3,9) ...

And, if the zig-zag scanned coefficients continue to end after some position, add an end of block (EOB) sign indicating the end of the block.

In this way, the line length coded data is variable length coded by the Huffman table.

In addition, when there is no coefficient to be transmitted in inter coding, this is called a skipped macroblock. Information data indicating how many skipped macroblock blocks are continued, and information data indicating whether blocks belonging to each macroblock are coded are also coded. It is transmitted to the decoder through the video buffer (not shown).

On the other hand, the video data transmitted through the compression process as described above is restored to the original data in the video decoder, such a video decoder is to implement the video encoder in reverse.

That is, FIG. 2 is a schematic block diagram of a general video decoder, comprising: a variable length decoder 5 for performing variable length decoding on encoded data on data; A line length decoder 6 for performing a line length decoder on the image data output from the variable length decoder 5; An inverse scanning unit 7 which scans the data output from the line length decoder 6 in reverse and outputs an 8x8 frequency coefficient block; An inverse quantizer 8 for performing inverse quantization on the 8x8 frequency coefficient block output from the inverse scanning unit 7 and outputting the inverse quantizer; The inverse discrete cosine transform unit 9 outputs an 8x8 minimum block by performing DCT inverse with respect to the 8x8 frequency coefficient block output from the inverse quantizer 8.

In the video decoder as described above, the variable length decoder 5 extracts the variable length coded DCT coefficients from the coded bit stream and outputs the result to the line length decoder 6 that performs variable length coding inversely. (6) performs line length decoding on the data output from the variable length decoder 5 and outputs it to the inverse scanning section 7. FIG.

In addition, the inverse scanning unit 7 converts the one-dimensional DCT coefficients output from the line length decoder 6 into two dimensions again according to the scanning method.

As described above, the DCT coefficients output in two dimensions are inversely quantized by the inverse quantizer 8 to be restored to the actual DCT coefficients, and then inverse discrete cosine transformed by the inverse discrete cosine transform unit 9 to perform 8 × 8 pixel blocks. Will be output as

At this time, the data input to the line length decoder 6 basically has a run and a level, where the run represents the length of zero and the level follows the zero after the run length. Value.

Meanwhile, the string length decoder operating as described above will be described in more detail with reference to FIG.

When the power is turned on, the variable length decoder 10 starts to write data to the first-in first-out buffer 15, and when a sufficient amount of data is accumulated in the first-in first-out buffer 15, a read enable signal (read enable: RE) is input to the line length decoder 20.

When the line length decoder 20 receives the lead enable signal RE, the line length decoder 20 waits for a frame synchronization signal Frame-sync. Decode the input data lengthwise.

In this case, the line length decoder 20 outputs a read request signal (read request: rrg) to the first-in, first-out buffer 15 to receive data from the first-in, first-out buffer 15.

When the frame end signal (Frame-end) is input to the line length decoder 20, the line length decoding is stopped and the standby mode waits for the next frame synchronization signal (Frame-end).

That is, the line length decoder 20 receives a frame synchronous signal (Frame-sync.) To start frame processing every frame and performs frame processing, while ending the frame currently being processed. Frame-end) is input to end the frame processing.

An object of the present invention is to provide an initial driving circuit for driving a string length decoder when the power is turned on.

In accordance with an aspect of the present invention, a line length decoder initial driving circuit includes: a first AND gate outputting AND of a read enable signal and a frame synchronization signal; An initial read request signal generator configured to receive an output signal of the first AND gate and a system reset signal to generate and output an initial read request signal for outputting data of a first-in first-out buffer; And an active signal generation unit configured to output an active signal for performing line length decoding upon receiving the signal output from the first end gate 30 and the frame end signal or the system reset signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 is a circuit diagram of an initial driving circuit of a line length decoder according to the present invention, and includes: a first AND gate 30 that ANDs and outputs a read enable signal RE and a frame synchronization signal Frame-sync. Wow; An initial read request signal for generating and outputting an initial read request signal fir-rrq for receiving the signal output from the first AND gate 30 and the system reset signal sys-rst to output the data of the first-in first-out buffer. A generating unit 40; Generation of an active signal for outputting an active signal for performing line length decoding by receiving the signal output from the first AND gate 30 and the frame end signal or the system reset signal sys_rst. It is comprised including the part 50.

The initial lead signal generation unit 40 includes: a first orifice 42 for ORing and outputting a system reset signal sys-rst and a feedback signal; A first D-flip flop that latches the signal output from the orifice (42), feeds it back to the first orifice (42), and outputs it; The AND signal output from the first D-flip flop 44 and the signal output from the first AND gate 30 are ANDed and input as a reset signal of the D-flip flop 44. The second AND gate 46 outputs the initial read request signal fir-rrq.

In addition, the active signal generator 50 performs a logical OR between the signal output from the first AND gate 30 and the feedback signal, and outputs the second OA gate 52 and the frame end signal (Frame-end). ) And a system reset signal (sys -rst) are input as a reset signal, while the signal output from the second orifice 52 is latched and fed back to the second orifice 52 and an active signal is active. And a second D flip-flop 54 which is output to

The operation and effects of the initial length of the string length decoder initial driving circuit according to the present invention configured as described above will be described in detail with reference to FIGS. 3 and 4.

When the power is turned on, the variable length decoder 10 starts to write data to the first-in first-out buffer 15, and when a sufficient amount of data is accumulated in the first-in first-out buffer 15, a read enable signal (read enable: RE) is printed.

The read enable signal RE and the frame synchronization signal Frame-sync. Output as described above are ANDed at the first AND gate 30 to generate the second AND of the initial read request signal generator 30. It is input to the gate 46 and the second or gate 52 of the active signal generator 50.

On the other hand, the first oar gate 42 of the initial read request signal generator 30 feeds back the system reset signal sys-rst of the active high input when the power is turned on and the first D-flip flop 44. The OR signal is ORed and output to the first D flip-flop 44, and the first D flip-flop 44 latches and outputs the signal input from the oragate 42.

In addition, the second AND gate 46 performs an AND operation on the signal output from the first D-flip flop 44 and the signal output from the first AND gate 30 to perform an initial read request signal fir. -rrq).

At this time, the initial read request signal (fir-rrq) is that the first D- flip-flop 44 is input as a reset signal.

The initial read request signal fir-rrq generated as described above is output to the first-in, first-out buffer 15 so that the line length decoder 20 receives data from the first-in, first-out buffer 15.

In this case, the initial read request signal fir-rrq is generated only once after the power is turned on. After that, the line length decoder 20 outputs a read request signal (read request: rrg) from the first-in, first-out buffer 15. To receive data from the first-in, first-out buffer 15.

On the other hand, the second OA gate 52 of the active signal generator 50 ORs the signal output from the first AND gate 30 and the signal fed back from the second D-flip flop 54. Outputs to a second D flip-flop 24, and the second D flip-flop 54 latches the signal output from the second O-gate 52 to reduce the active signal active. )

In this case, the second D flip-flop 54 receives a frame end signal (Frame-end) and a system reset signal (sys-rst) as a reset signal.

The line length decoder 20 receives the active signal active, decodes the frame length when the active signal is high, and enters the standby mode when the low signal is low.

In the above, the frame synchronizing signal (Frame-syn.), The frame end signal (Frame-end) and the system reset signal (sys-rst) are input from separate control means.

Referring to the timing diagram of FIG. 5, the operation of the initial length of the string length decoder initial driving circuit operating as described above will be described as follows.

FIG. 5A is a timing diagram of a system reset signal sys-rst of an active high input after power is turned on, and FIG. 5B is a signal output from the first D flip-flop 44 Fig. 5 (c) is a timing diagram of the read enable signal RE input from the variable length decoder 10, and Fig. 5d is a frame input to separate control means. FIG. 5E is a timing diagram of a frame end signal input from a separate control means, and FIG. 5F is a timing diagram of a synchronization signal Frame-sync. Is a timing diagram of an initial read request signal fir-rrq output from an initial driving circuit of a line length decoder, and FIG. 5 (g) illustrates an active signal output from an initial driving circuit of a line length decoder according to the present invention. Timing diagram.

That is, when the power is turned on, the system reset path (sys-rst) becomes high, and the output signal of the first D flip-flop 44 has a continuous high level.

At this time, when the initial read request signal fir-rrq of the active high output from the second AND gate 46 is input as the reset signal of the first D-flip flop 44, the first D-flip flop 44 is generated. ) Output is low level.

At this time, the output of the first D-flip-flop 44 is converted at the falling edge of the initial read request signal fir-rrq.

The signal output from the first D-flip-flop 44 is a read enable signal RE input from the variable length decoder 10 and a frame sync signal input to a separate control means. Is ANDed at the AND signal and the second AND gate 46, and the initial read request signal fit-rrq is output.

That is, since the initial read request signal fir-rrq is generated by the first frame synchronizing signal (Frame-syn.) Input after the power is turned on, the initial read request signal fir-rrq is generated only once after the power is turned on. Is generated.

In addition, the output signal of the second D-flip-flop 54 is composed of the read enable signal RE input from the variable length decoder 10 and the frame synchronization signal Frame-sync. When the AND signal is high, the line length decoder 20 is operated by inputting an active signal to the line length decoder 20 at a continuous high level.

In this case, the second D flip-flop 54 receives a frame end signal (Frame-end) and a system reset signal (sys-rst) input from a separate control means as a reset signal. -end) outputs a low level signal until the next frame synchronization signal (Frame-sysc.) is input, and thus the line length decoder 20 until the next frame synchronization signal (Frame-sysc.) is input. To stop the operation.

As described above, according to the present invention, the string length decoder can be initially driven when the power is turned on.

Claims (5)

A first AND gate 30 which ANDs the read enable signal RE and the frame synchronization signal Frame-sync. An initial read request signal for generating and outputting an initial read request signal fir-rrq for receiving the signal output from the first AND gate 30 and the system reset signal sys-rst to output the data of the first-in first-out buffer. A generating unit 40; An active signal generator for receiving a signal output from the first AND gate 30 and a frame end signal or the system reset signal sys_rst and outputting an active signal for performing line length decoding; An initial driving circuit for a strip length decoder, comprising: a 50; 2. The system of claim 1, wherein the initial lead signal generator (40) comprises: a first orifice (42) for ORing and outputting a system reset signal (sys-rst) and a feedback signal; The first D-flip flop 44 and the output from the D-flip flop 44 which latch and output the signal output from the oragate 42 to feed back to the first oracle 42. And a second AND gate 46 configured to AND the signal and the signal output from the first AND gate 30 to output an initial read request signal fir-rrq. Decoder initial drive circuit. The initial length circuit of claim 2, wherein the first D-flip-flop (44) receives the initial read request signal (fir-rrq) as a reset signal. 2. The second oA gate 52 of claim 1, wherein the active signal generator 50 outputs a logic OR between the signal output from the first AND gate 30 and the feedback signal. And a second D flip-flop 54 which latches the signal output from the second orifice 52 and feeds it back to the second orifice 52 and outputs an active signal. Line length decoder initial drive circuit. 5. The initial length circuit of claim 4, wherein the second D-flip flop 54 receives a frame end signal and a system reset signal sys-rst as reset signals. .