KR19990003491A - Method of manufacturing thin film transistor of semiconductor device - Google Patents
Method of manufacturing thin film transistor of semiconductor device Download PDFInfo
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- KR19990003491A KR19990003491A KR1019970027372A KR19970027372A KR19990003491A KR 19990003491 A KR19990003491 A KR 19990003491A KR 1019970027372 A KR1019970027372 A KR 1019970027372A KR 19970027372 A KR19970027372 A KR 19970027372A KR 19990003491 A KR19990003491 A KR 19990003491A
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- thin film
- gas
- gate oxide
- film transistor
- oxide film
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- 239000010409 thin film Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000010408 film Substances 0.000 claims abstract description 31
- 238000004140 cleaning Methods 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 2
- 239000012159 carrier gas Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 239000012495 reaction gas Substances 0.000 claims 1
- 230000003068 static effect Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Abstract
1.청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs
본 발명은 반도체 소자의 박막 트랜지스터 제조방법에 관한 것으로 특히, SRAM (Static Random Access Memory) 혹은 LCD 와 같은 소자의 박막트랜지스터의 채널로 이용되는 채널폴리실리콘 박막 형성전 게이트 산화막 세정방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor of a semiconductor device, and more particularly, to a method of cleaning a gate oxide film before forming a channel polysilicon thin film used as a channel of a thin film transistor of a device such as an SRAM (Static Random Access Memory) or an LCD.
2.발명이 해결하려고 하는 기술적 과제2. Technical problem that the invention tries to solve
채널 폴리실리콘 박막 형성전에 행하는 게이트 산화막 세정공정을 습식 세정법을 적용함에 따라 게이트 산화막의 두께 균일도가 저하되는 것을 방지하고자 한다.It is intended to prevent the thickness uniformity of the gate oxide film from being lowered by applying the wet cleaning method to the gate oxide film cleaning step performed before the channel polysilicon thin film is formed.
3.발명의 해결방법의 요지3. Summary of the solution of the invention
UV/Cl2혼합가스 및 HF/CH3OH 혼합가스를 이용하여 2차례 세정 공정을 실시하여 게이트 산화막의 두께 균일도를 향상시킨다.The cleaning process is performed twice using the UV / Cl 2 mixed gas and the HF / CH 3 OH mixed gas to improve the thickness uniformity of the gate oxide film.
4.발명의 중요한 용도4. Important uses of the invention
반도체 소자의 박막 트랜지스터 제조에 적용된다.Applied in manufacturing thin film transistors of semiconductor devices.
Description
본 발명은 반도체 소자의 박막 트랜지스터 제조방법에 관한 것으로, 특히 SRAM (Static Random Access Memory) 혹은 LCD 와 같은 소자의 박막트랜지스터의 채널로 이용되는 채널폴리실리콘 박막 형성전 세정방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor of a semiconductor device, and more particularly, to a cleaning method before forming a channel polysilicon thin film used as a channel of a thin film transistor of a device such as an SRAM (Static Random Access Memory) or an LCD.
일반적으로 SRAM(Static Random Access Memory)의 집적도가 높아짐에 따라 셀의 면적이 작아지므로, 이에 따라 전류의 소모가 적고 데이터 유지의 안정도가 높으며, 고속동작과 낮은 소모전류의 특성을 갖는 박막 트랜지스터의 적용이 요구된다. 그런데 박막 트랜지스터의 채널은 단결정 실리콘에서 형성되는 것이 아니고 다결정 실리콘에서 형성되기 때문에 다결정 실리콘 내에서 트랜지스터의 채널 폴리내에는 여러개의 결정을 가지는 다결정 실리콘 박막을 가지게 된다. 그런데 다결정 실리콘박막 내에 존재하는 결정 경계면(Grain Boundary)은 결정간의 계면전위 장벽으로 작용하여, 케리어(Carrier)의 이동도를 저하시키고 계면에 케리어들을 트래핑(Trapping)시켜, 이들 트랩(Trap)된 케리어들에 의한 열방사 현상, 전계방사에 의한 누설전류가 발생하여 특성을 저하시킨다. 따라서 상기의 단점을 보완하기 위하여 다결정 시리콘의 결정을 조대화시켜 단결정에 가깝게 하면 좋은 특성의 박막트랜지스터를 제조할 수가 있다.In general, as the area of SRAM (Static Random Access Memory) increases, the area of the cell decreases. Therefore, a thin film transistor having low current consumption, high data retention stability, and high-speed operation and low power consumption is applied. Is required. However, since the channel of the thin film transistor is not formed of single crystal silicon, but is formed of polycrystalline silicon, the polycrystalline silicon thin film having a plurality of crystals is included in the channel poly of the transistor in the polycrystalline silicon. However, the grain boundary present in the polycrystalline silicon thin film acts as an interfacial potential barrier between the crystals, thereby reducing the mobility of the carrier and trapping carriers at the interface, thereby trapping the carriers. Thermal radiation caused by these fields and leakage currents caused by the field radiation are generated to deteriorate characteristics. Therefore, in order to make up for the above drawbacks, it is possible to produce thin film transistors having good characteristics by coarsening the crystals of polycrystalline silicon to bring them closer to the single crystal.
한편으로 게이트 산화막은 박막트랜지스터 특성상 화학 기상증착방법으로 산화막을 형성시켜야 한다. 상기 화학 기상증착 방법으로 형성된 산화막은 일반적인 열 산화막에 비하여 그 특성이 저하되고, 게이트 산화막 형성후 후속의 채널 풀리실리콘박막 형성시키기 위하여 콘택 마스크 및 식각공정으로 이어져 게이트 산화막 상부가 크게 오염된다. 따라서, 후속 박막트랜지스터 채널 폴리실리콘 박막 형성 전에 게이트 산화막의 세정공정이 필수적이다. 현재는 이와같은 게이트 세정작업을 습식 세정방법으로 진행한다. 상기 습식 세정방법은 스택(Stack)구조적인 측면과, 습식 화학 세정(Wet Chemical Cleaning) 특성상 식각비에 따른 웨이퍼의 게이트 산화막 두께 균일도 특성이 크게 저하된다. 그 결과 소자의 중심에서 끝 부분의 단차가 약 100Å의 두께 차이가 발생되어 박막트랜지스터 특성 균일도가 크게 저하되어 소자의 신뢰성 및 양산성 면에서 특성 저하를 초래하는 문제점이 발생한다.On the other hand, the gate oxide film should be formed by the chemical vapor deposition method due to the characteristics of the thin film transistor. The oxide film formed by the chemical vapor deposition method is deteriorated compared to a general thermal oxide film, and after the gate oxide film is formed, a subsequent contact mask and an etching process are formed to form a channel pulley silicon thin film, and the top of the gate oxide film is greatly contaminated. Therefore, the cleaning process of the gate oxide film is essential before the formation of the subsequent thin film transistor channel polysilicon thin film. At present, such gate cleaning is performed by a wet cleaning method. In the wet cleaning method, the gate oxide film thickness uniformity characteristic of the wafer due to the etching ratio is greatly reduced due to the stack structure and the wet chemical cleaning characteristics. As a result, a thickness difference of about 100 μs occurs at the end of the device, and the uniformity of the thin film transistor characteristics is greatly reduced, resulting in a problem of deterioration in reliability and mass productivity of the device.
따라서, 본 발명은 게이트 산화막의 세정방법을 개선하여 박막 트랜지스터의 게이트 산화막 두께의 균일도 특성을 향상시켜 소자의 신뢰성 향상 및 양산성을 향상시키는데 그 목적이 있다.Therefore, an object of the present invention is to improve the uniformity characteristic of the thickness of the gate oxide film of the thin film transistor by improving the cleaning method of the gate oxide film, thereby improving the reliability and mass productivity of the device.
상기한 목적을 달성하기 위한 본 발명은 하부구조상에 박막 트랜지스터의 게이트 전극을 형성하는 단계와, 상기 게이트 전극 전체 상부면에 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막 일부분을 식각하여 상기 하부 구조의 일부가 노출되도록 콘택 홀을 형성하는 단계와, 금속 불순물이 제거되도록 UV/Cl2혼합가스를 이용한 1차 세정 공정을 실시하는 단계와, 자연산화막이 제거되도록 HF/CH3OH 혼합가스를 이용하여 2차 세정 공정을 실시하는 단계와, 전체 상부면에 채널 폴리실리콘 박막을 형성하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate electrode of a thin film transistor on a lower structure, forming a gate oxide layer on an entire upper surface of the gate electrode, and etching a portion of the gate oxide layer to form a gate electrode. Forming a contact hole to expose a portion, performing a primary cleaning process using a UV / Cl 2 mixed gas to remove metal impurities, and using HF / CH 3 OH mixed gas to remove a natural oxide film. And performing a secondary cleaning process and forming a channel polysilicon thin film on the entire upper surface.
도 1a 및 도 1b는 본 발명에 따른 반도체 소자의 박막 트랜지스터 제조방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of manufacturing a thin film transistor of a semiconductor device according to the present invention.
도 2a 및 도 2b는 본 발명에 따른 웨이퍼의 균일도를 설명하기 위한 도표.2A and 2B are diagrams for explaining the uniformity of the wafer according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 트랜지스터1: silicon substrate 2: transistor
3 : 접합부 4 : 하부배선3: junction part 4: lower wiring
5 : 게이트 전극 6 : 게이트 산화막5 gate electrode 6 gate oxide film
7 : 콘택 홀 8 : 비정질 실리콘 박막7: contact hole 8: amorphous silicon thin film
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a를 참조하면, 트랜지스터(2)와 같은 소자가 형성된 실리콘 기판(1)이 제공된다. 접합부(3)에 접속되는 하부 배선(4)을 형성한 후 전체 상부면에 절연막을 형성한다. 그 후 박막 트랜지스터 게이트 전극(5)을 형성한 후 전체 상부면에 박막 트랜지스터 게이트 산화막(6)을 형성한다. 이때 상기 박막 트랜지스터 게이트 산화막(6)은 SiH4/N2O 및 SiH2Cl2/N2O 혼합가스 중 어느 하나를 이용하여 600 내지 900℃ 의 온도범위에서 200 내지 600Å의 두께로 형성한다. 또한 박막 트랜지스터 게이트 산화막(6)은 저압 화학 기상증착방법으로 형성한다. 그 후 상기 게이트 산화막(6) 일부분을 식각하여 하부 배선(4)이 노출 되도록 콘택 홀(7)을 형성한 후 UV/Cl2를 이용한 1 차 세정 공정을 실시하면 상기의 패터닝 공정시 발생된 유기물을 완전히 제거된다. 그 다음 HF/CH3OH 가스를 이용한 2 차 세정공정으로 게이트 산화막 표면의 자연 산화막을 제거하며, 인시투(Insitu)방식 세정 공정을 실시한다. 이때의 공정온도는 40 내지 80℃이며, HF 가스 주입비는 150 내지 200 SCCM, CH3OH 가스 주입 비는 30 내지 50 SCCM 로 하고, CH3OH 소오스(Source)는 N2를 케리어(Carrier) 가스로 이용한다. 상기 게이트 산화막 세정시 공정 압력은 100 내지 250 torr 에서 실시한다.Referring to FIG. 1A, a silicon substrate 1 is provided on which elements such as transistors 2 are formed. After forming the lower wiring 4 connected to the junction part 3, an insulating film is formed in the whole upper surface. Thereafter, the thin film transistor gate electrode 5 is formed, and then the thin film transistor gate oxide film 6 is formed on the entire upper surface. At this time, the thin film transistor gate oxide film 6 is formed to a thickness of 200 to 600 kPa in a temperature range of 600 to 900 ℃ using any one of SiH 4 / N 2 O and SiH 2 Cl 2 / N 2 O mixed gas. The thin film transistor gate oxide film 6 is formed by a low pressure chemical vapor deposition method. After that, a part of the gate oxide layer 6 is etched to form a contact hole 7 so that the lower interconnection 4 is exposed, and then a primary cleaning process using UV / Cl 2 is performed to generate organic materials during the patterning process. Is completely removed. Next, a natural oxide film on the surface of the gate oxide film is removed by a secondary cleaning process using HF / CH 3 OH gas, and an insitu cleaning process is performed. The process temperature at this time is 40 to 80 ℃, HF gas injection ratio is 150 to 200 SCCM, CH 3 OH gas injection ratio is 30 to 50 SCCM, CH 3 OH source (Source) is N 2 Carrier (Carrier) Use as gas. The process pressure during the gate oxide film cleaning is performed at 100 to 250 torr.
도 1b를 참조하면, 상기 박막 트랜지스트의 게이트 산화막(6) 상부에 480 내지 550℃의 온도범위와, 1 torr 이하의 압력, SiH4및 Si2H6가스를 이용하여 비정질실리콘 박막(8)을 형성한다. 그 후 상기 비정질 실리콘 박막(8)을 진공 또는 불활성기체 분위기 하에서 600 내지 700℃의 온도로 30분 내지 10시간 동안 열공정을 실시한다. 이때 상기 열공정으로 인하여 실리콘 씨드(Seed)를 중심으로해서 상기 비정질 실리콘박막(8)은 다결정실리콘 박막으로 고상성장하여 그 크기가 아주 균일하고 매우 조밀한 채널 폴리실리콘 박막이 형성된다. 이때 고상성장을 위한 열처리공정을 상기 열공정 온도까지 온도를 상승시켜 인-시투 튜브(In-Situ Tube) 이용하는 방법과 또한 또다른 공정튜브를 이용하여 형성시키는 방법 등 여러 공정방법으로 고상성장법에 의한 채널 폴리실리콘 박막을 형성 시킬 수 있다.Referring to FIG. 1B, an amorphous silicon thin film 8 is formed by using a temperature range of 480 to 550 ° C., a pressure of 1 torr or less, and SiH 4 and Si 2 H 6 gas on the gate oxide layer 6 of the thin film transistor. To form. Thereafter, the amorphous silicon thin film 8 is thermally treated at a temperature of 600 to 700 ° C. for 30 minutes to 10 hours in a vacuum or inert gas atmosphere. At this time, due to the thermal process, the amorphous silicon thin film 8 is solid-grown with a polysilicon thin film around the silicon seed to form a very uniform and very dense channel polysilicon thin film in size. At this time, the heat treatment process for the solid phase growth is raised to the heat process temperature by using the in-situ tube (In-Situ Tube), and also by using a different process method, such as a method for forming the solid state growth method By the channel polysilicon thin film can be formed.
도 2a는 게이트 산화막의 표면의 자연 산화막이 제거된 두께를 도시한 도표로 20Å 이하로 제어되어 아주 우수한 균일도 특성을 나타내는 것을 알수 있다.FIG. 2A is a diagram showing the thickness of the natural oxide film removed from the surface of the gate oxide film, which is controlled to 20 kPa or less, showing that excellent uniformity characteristics are shown.
도 2b는 상기와 같은 2차 세정공정을 실시한 후 웨이퍼상에서 측정한 콘택 엥글(Contact Angle)을 도시한 도표로, 콘택 엥글 dl 70°이상이면 표면에 자연 산화막이 완전히 제거된 것을 나타낸다. 또한 2 차 세정공정에 의하여 표면의 산화막은 완전히 제거되고 균일도 특성도 아주 우수한 것을 보여주고 있다.FIG. 2B is a diagram illustrating contact angles measured on a wafer after performing the above-described secondary cleaning process. When the contact angle dl is 70 ° or more, the natural oxide film is completely removed from the surface. In addition, it is shown that the oxide film on the surface is completely removed by the secondary cleaning process and the uniformity characteristic is very excellent.
상술한 바와같이 본 발명의 1 차 세정 공정으로 금속 불순물을 제거하고 그 후 2 차 세정 공정으로 박막 트랜지스터 게이트 산화막 표면을 세정하면 현재 문제되고있는 채널역활을 하는 다결정 실리콘 박막 형성전 세정공정시 제거되는 산화막의 두께를 20Å 이하로하여 웨이퍼 내 두께의 균일도를 최소한으로 제어하여 현재 문제되고 있는 박막트랜지스터 게이트산화막의 두께 특성을 향상시켜 소자의 신뢰성 향상 및 양산성을 향상시키는 효과가 있다.As described above, if the metal impurities are removed by the first cleaning process of the present invention and then the surface of the thin film transistor gate oxide film is cleaned by the second cleaning process, it is removed during the cleaning process before forming the polycrystalline silicon thin film, which serves as a currently problematic channel. By controlling the thickness of the oxide film to be less than 20 GPa, the uniformity of the thickness in the wafer is controlled to the minimum, thereby improving the thickness characteristics of the thin film transistor gate oxide film, which is currently a problem, thereby improving the reliability and mass productivity of the device.
또한, 그랜인 사이즈가 조밀하고 크며 균일한 다결정 실리콘 박막을 얻을수 있어, SRAM 소자 또는 LCD 와 같은 박막트랜지스터의 채널로 이용할 경우 소자의 셀(Cell) 및 다이(Die) 들의 결정 계면 사이의 밀도 감소 및 균일도를 개선시킨다. 따라서, 소자의 계면전위장벽이 낮아져 케리어의 이동도를 증가시키고, 열방사 현상을 저하시켜 계면에서의 소모전류가 줄어들어 On/Off 전류비를 크게 향상 시킨다. 그 결과 웨이퍼내에서 셀 및 다이와 다이의 특성 차이를 크게 개선 시켜 소자의 신뢰성 및 양산성을 크게 향상시킬수 있는 효과가 있다.In addition, it is possible to obtain a polycrystalline silicon thin film of dense, large, and uniform grain size. Improves uniformity. Therefore, the interfacial potential barrier of the device is lowered to increase the mobility of the carrier, and the thermal radiation phenomenon is reduced to reduce the current consumption at the interface, thereby greatly improving the on / off current ratio. As a result, the difference in the characteristics of the cell, the die, and the die in the wafer can be greatly improved, thereby improving the reliability and mass production of the device.
Claims (11)
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