KR19990002273A - Semiconductor Device Etching Method - Google Patents

Semiconductor Device Etching Method Download PDF

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KR19990002273A
KR19990002273A KR1019970025834A KR19970025834A KR19990002273A KR 19990002273 A KR19990002273 A KR 19990002273A KR 1019970025834 A KR1019970025834 A KR 1019970025834A KR 19970025834 A KR19970025834 A KR 19970025834A KR 19990002273 A KR19990002273 A KR 19990002273A
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etching
oxide film
polysilicon layer
semiconductor device
photoresist
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KR100236078B1 (en
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이지혜
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문정환
엘지반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline

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Abstract

본 발명은 반도체소자 제조공정중 산화막 또는 질화막과 폴리실리콘층을 동시에 식각하여 공정을 보다 간략화하는데 적당한 반도체소자 식각방법에 관한 것으로서 기판상에 절연층을 개재하여 폴리실리콘층을 형성하는 공정과, 상기 폴리실리콘층상에 산화막을 증착한 후 산화막상에 포토레지스트를 도포하는 공정과, 상기 포토레지스트를 패터닝한 후 Ar, CHF3, O2가스에 N2가스를 첨가하여 상기 산화막과 폴리실리콘층과의 저선택성을 이용한 식각공정으로 상기 산화막과 폴리실리콘층을 동시에 식각하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a semiconductor device etching method suitable for simplifying the process by etching the oxide or nitride film and the polysilicon layer at the same time during the semiconductor device manufacturing process, the process of forming a polysilicon layer via an insulating layer on the substrate; Depositing an oxide film on the polysilicon layer and then applying a photoresist on the oxide film, and after patterning the photoresist, adding N 2 gas to Ar, CHF 3 , O 2 gas to form an oxide film with the polysilicon layer. The etching process using the low selectivity is characterized in that it comprises a step of etching the oxide film and the polysilicon layer at the same time.

Description

반도체소자 식각방법Semiconductor Device Etching Method

본 발명은 반도체소자에 관한 것으로, 특히 저선택성을 이용한 동시식각을 통해 공정을 간략화시키는데 적당한 반도체소자의 식각방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a method of etching a semiconductor device suitable for simplifying the process through the simultaneous etching using low selectivity.

일반적으로 식각이란 감광막현상 공정이 끝난 후 감광막 밑에 성장 혹은 증착시킨 박막들을 공정목적에 따라 선택적으로 제거하는 공정으로서 감광막에 의해 덮여져 있는 부분은 식각작업중 보호를 받아 남아 있게 되며 노출된 박막은 식각되어 없어지게 된다.In general, etching is a process of selectively removing thin films grown or deposited under the photoresist layer after the photoresist process is completed, depending on the purpose of the process. It will disappear.

또한 식각은 습식식각과 건식식각으로 나눌 수 있으며 감광막 제거공정도 포함된다.Etching can also be divided into wet etching and dry etching, and includes photoresist removal.

습식식각이란 식각하고자 하는 박막과 화학적으로 반응하여 용해시킬 수 있는 화학용액을 사용하여 식각하는 방법을 말하며, 박막의 종류의 특성에 따라 사용하는 화학용액이나 조성비가 각기 다르게 된다.Wet etching refers to a method of etching using a chemical solution capable of chemically reacting and dissolving the thin film to be etched. The chemical solution or composition ratio used varies depending on the characteristics of the thin film.

산화막은 크게 성장산화막과 증착산화막으로 나눌 수 있으며 방법이나 분위기에 따라서 더욱 세분화되기도 한다.The oxide film can be roughly divided into a growth oxide film and a deposition oxide film, and may be further subdivided according to a method or an atmosphere.

그러나 어느 종류의 산화막이든 그 원리는 같다. 즉, 산화막이 불산에 용해되는 성질을 이용한 것으로 고온에서 성장시킨 산화막은 불산이 해리되어 수소이온과 불소이온으로 분리되게 되며 이렇게 분리된 불소이온이 산화막과 반응하여 식각이 이루어지게 된다.However, the principle is the same for any kind of oxide film. In other words, the oxide film is dissolved in hydrofluoric acid, and the oxide film grown at high temperature dissociates hydrofluoric acid and is separated into hydrogen ions and fluorine ions.

하지만 식각이 계속 진행됨에 따라 불소이온은 소모가 되며 용액자체가 물에 의해 희석되면서 용액내의 수소이온 농도는 증가하게 된다.However, as the etching continues, fluorine ions are consumed and the concentration of hydrogen ions in the solution increases as the solution is diluted with water.

이러한 결과로 산화막의 식각속도는 공정을 행할 때마다 변하게 된다.As a result, the etching rate of the oxide film changes each time the process is performed.

이는 공정상 매우 불안정한 상태로 재현성있는 균일한 결과를 얻고자 하는 공정목적에 장애가 된다.This is an obstacle to the process purpose to obtain a uniform and reproducible result in a very unstable state of the process.

이와같은 문제 즉, 수소이온 농도나 식각속도의 변화를 제거하여 일률적인 결과를 얻기 위하여 새로운 용액이 첨가되는데 이 경우에는 불화암모니움(NH4F)을 첨가하므로서 안정화 시킬 수 있다.To solve this problem, a new solution is added to remove the change in hydrogen ion concentration or etching rate to obtain uniform results. In this case, it can be stabilized by adding ammonium fluoride (NH 4 F).

불화암모니움은 암모니움 이온과 불소이온으로 해리되며 이때의 불소이온이 식각반응에 참여하게 되는 것이다.Ammonium fluoride dissociates into ammonium ions and fluorine ions, and the fluoride ions participate in the etching reaction.

다시말하면 식각반응에 소모되어 없어지는 불소이온을 충당하는 역할을 하며, 용액내의 수소 이온농도를 일정하게 해줌으로서 식각속도를 균일하게 유지할 수 있도록 한다.In other words, it serves to cover the fluorine ions that are consumed in the etching reaction and to maintain the etching rate uniformly by keeping the concentration of hydrogen ions in the solution constant.

반면에 암노니움 이온은 식각반응에 미치는 영향이 없으므로 공정목적을 만족시킨다.Amnonium ions, on the other hand, have no effect on the etching reaction, thus satisfying the process objectives.

다결정실리콘이나 금속층에서의 원리는 산화제를 사용하여 이들 박막을 산화시킨 후 산화된 박막을 식각하게 되는데 두 박막 모두 질산을 산화제로 사용한다.The principle in polycrystalline silicon or metal layers is to oxidize these thin films using an oxidant and then etch the oxidized thin films, both of which use nitric acid as the oxidant.

다결정실리콘이 산화되면 산화막으로 변하게 되며 이를 불산으로 식각하게 된다.When the polysilicon is oxidized, it is converted into an oxide film and etched with hydrofluoric acid.

이때 요오드를 산화반응의 촉매로 이용하기 위하여 초산에 용해시켜 사용하기도 한다.In this case, iodine may be dissolved in acetic acid to be used as a catalyst for oxidation reaction.

또한 금속층은 주로 알루미늄을 사용하는데 이를 산화시키면 산화알루미늄이 되고 이는 인산에 용해되기 때문에 식각이 진행된다.In addition, the metal layer mainly uses aluminum, which is oxidized to aluminum oxide, which is dissolved in phosphoric acid, so that etching proceeds.

이들 두 박막의 식각용액에 초산이나 물이 첨가되는데 이것이 수소 이온농도를 조절하는 완충역할을 하거나 단순히 희석제로 쓰인다.Acetic acid or water is added to the etching solutions of these two thin films, which act as a buffer to control hydrogen ion concentration or simply as a diluent.

그러나 습식식각에서는 등방형식각이 이루어지게 되는데 그 이유는 화학반응이 수직으로 일어날 뿐 아니라 수평으로 반응하기 때문이다.However, wet etching results in isotropic angles because chemical reactions occur horizontally as well as vertically.

이런 결과로 감광막에 의해 보호되어야 할 박막의 끝부분이 원형으로 식각되어 없어지는 언더컷 현상이 일어난다.As a result, an undercut phenomenon occurs in which the end portion of the thin film to be protected by the photoresist is etched in a circle.

이것은 습식식각의 가장 큰 단점으로 회로의 선폭이 좁은 집적회로로 소자 제조공정에 이용하기 어렵다는 제약을 받는다.This is the biggest disadvantage of wet etching, which is limited to integrated circuits with narrow line widths, making them difficult to use in device manufacturing processes.

이러한 이유에서 건식식각이 이루어지고 있다.For this reason, dry etching is performed.

건식식각이란, 특정한 가스를 두 전극사이에 넣고 강한 전장을 형성시키면 전기적인 충격에 의하여 가스가 이온화된다.In dry etching, when a specific gas is inserted between two electrodes to form a strong electric field, the gas is ionized by an electric shock.

이 때의 이온화된 가스는 반응성이 매우 강하기 때문에 식각기로 사용된다.The ionized gas at this time is used as an etcher because it is very reactive.

이러한 식각기는 식각할 박막의 원자들과 반응하여 휘발성 화합물을 생성하면서 식각이 진행된다.The etchant reacts with atoms of the thin film to be etched to produce a volatile compound, thereby etching.

이때 생성된 휘발성 화합물은 진공펌프에 의해 밖으로 배출시킴으로서 쉽게 제거할 수 있다.At this time, the generated volatile compounds can be easily removed by discharging it out by a vacuum pump.

앞에서 언급한 것과 같이 습식식각에서는 등방향식각이 이루어지는 반면에 건식식각에서는 등방향 및 비등방향식각의 조절이 어느정도 가능하다.As mentioned above, in the wet etching, the isotropic etching is performed, while in the dry etching, it is possible to adjust the isotropic and the boiling direction etching to some extent.

이러한 조절은 전자의 세기와 식각기의 기능을 강화시켜 효율적으로 응용함으로서 이루어진다.This control is achieved by efficiently applying the strength of the electrons and the function of the etcher.

현재 게이트라인이나 셀 캐패시터 형성시 일반적으로 산화막이나 질화막을 포토레지스트로 마스킹하여 식각한 후 다시 산화막 또는 질화막을 마스크로 하여 폴리실리콘을 식각하고 있다.Currently, when forming a gate line or a cell capacitor, an oxide film or a nitride film is generally masked and etched with a photoresist, and then polysilicon is etched using the oxide film or the nitride film as a mask.

이하, 종래기술에 따른 반도체소자의 식각방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, an etching method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 1c은 종래기술에 따른 반도체소자의 식각방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating an etching method of a semiconductor device according to the prior art.

도 1a에 도시한 바와같이 반도체기판(11)상에 고온저압유전체막(12)을 형성한 후 고온저압유전체막상에 폴리실리콘층(13)을 형성한다.As shown in FIG. 1A, the high temperature low pressure dielectric film 12 is formed on the semiconductor substrate 11, and then the polysilicon layer 13 is formed on the high temperature low pressure dielectric film.

그리고 상기 폴리실리콘층(13)상에 산화막 또는 질화막(14)을 증착하고 산화막 또는 질화막(14)상에 층간절연막으로서 BPSG(Boronphosphrous silicate glass)층(15)를 증착한다.An oxide film or nitride film 14 is deposited on the polysilicon layer 13, and a BPSG (Boronphosphrous silicate glass) layer 15 is deposited on the oxide film or nitride film 14 as an interlayer insulating film.

그리고 상기 BPSG층(15)상에 포토레지스트(도면에 도시되지 않음)를 도포한 후 노광 및 현상공정을 통해 포토레지스트를 패터닝한다.After the photoresist (not shown) is applied on the BPSG layer 15, the photoresist is patterned through an exposure and development process.

이어, 도 1b에 도시한 바와같이 패터닝된 포토레지스트를 마스크로 이용한 식각공정으로 BPSG층(15)과, 산화막 또는 질화막(14)을 선택적으로 제거하여 폴리실리콘층(13)의 표면을 노출시킨다.Subsequently, as illustrated in FIG. 1B, the surface of the polysilicon layer 13 is exposed by selectively removing the BPSG layer 15 and the oxide film or nitride film 14 by an etching process using the patterned photoresist as a mask.

이후, 도 1c에 도시한 바와같이 포토레지스트를 제거한 후 BPSG층(15), 산화막 또는 질화막(14)을 마스크로 이용하여 하부의 폴리실리콘층(13)을 선택적으로 제거한다.Thereafter, as shown in FIG. 1C, after removing the photoresist, the lower polysilicon layer 13 is selectively removed using the BPSG layer 15, the oxide film, or the nitride film 14 as a mask.

이와같이 폴리실리콘층(13)을 패터닝하여 게이트를 형성하거나 또는 셀 캐패시터를 형성하게 된다.In this way, the polysilicon layer 13 is patterned to form a gate or a cell capacitor.

그러나 상기와 같은 종래 반도체소자의 식각방법은 다음과 같은 문제점이 있었다.However, the etching method of the conventional semiconductor device as described above has the following problems.

첫째, 포토레지스트를 마스크로 이용하여 BPSG층, 산화막 또는 질화막과 동시에 폴리실리콘층을 식각하지 못한다.First, the polysilicon layer cannot be etched simultaneously with the BPSG layer, the oxide film or the nitride film using the photoresist as a mask.

따라서 BPSG층, 산화막 또는 질화막을 식각한 후 포토레지스트를 제거하거나 세정공정이 필수적으로 수반된다.Therefore, after etching the BPSG layer, the oxide film or the nitride film, a photoresist is removed or a cleaning process is necessarily accompanied.

둘째, 각각의 BPSG층, 산화막 또는 질화막 또는 폴리실리콘층의 각각에 대한 독립적인 공정조건이나 장비의 사용이 요구된다.Secondly, the use of independent process conditions or equipment for each BPSG layer, oxide film or nitride film or polysilicon layer is required.

셋째, 산화막 또는 질화막을 마스크로 하여 폴리실리콘층을 식각시 발생하는 손실에 대한 추가적인 두께증가가 필요하다.Third, an additional thickness increase is required for the loss caused by etching the polysilicon layer using the oxide film or the nitride film as a mask.

넷째, 폴리머를 제거하기 위한 또다른 마스킹공정이 필요하다.Fourth, another masking process is needed to remove the polymer.

본 발명은 상기한 문제점을 해결하기 위해 안출한 것으로서 절연층과 폴리실리콘층을 포토레지스트를 마스크로 하여 동시에 식각하므로서 공정을 간략화하는데 적당한 반도체소자의 식각방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide an etching method of a semiconductor device suitable for simplifying the process by simultaneously etching the insulating layer and the polysilicon layer using a photoresist as a mask.

도 1a 내지 1c는 종래 반도체소자 식각방법을 설명하기 위한 공정단면도1A to 1C are cross-sectional views illustrating a method of etching a conventional semiconductor device.

도 2a 내지 2b는 본 발명의 반도체소자 식각방법을 설명하기 위한 공정단면도2A through 2B are cross-sectional views illustrating a method of etching semiconductor devices according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

11,21 : 반도체기판12,22 : 고온저압유전체막11,21: semiconductor substrate 12,22: high temperature low pressure dielectric film

13,23 : 폴리실리콘층14,24 : 산화막 또는 질화막13,23 polysilicon layer 14,24 oxide film or nitride film

15,25 : BPSG층26 : 포토레지스트15,25 BPSG layer 26 photoresist

상기의 목적을 달성하기 위한 본 발명의 반도체소자 식각방법은 기판상에 절연층을 개재하여 폴리실리콘층을 형성하는 공정과, 상기 폴리실리콘층상에 산화막을 증착한 후 산화막상에 포토레지스트를 도포하는 공정과, 상기 포토레지스트를 패터닝한 후 Ar, CHF3, O2가스에 N2가스를 첨가하여 상기 산화막과 폴리실리콘층과의 저선택성을 이용한 식각공정으로 상기 산화막과 폴리실리콘층을 동시에 식각하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device etching method of the present invention for achieving the above object is a step of forming a polysilicon layer on the substrate via an insulating layer, and depositing an oxide film on the polysilicon layer and then applying a photoresist on the oxide film Etching the oxide film and the polysilicon layer simultaneously by an etching process using a low selectivity between the oxide film and the polysilicon layer by adding N 2 gas to the Ar, CHF 3 , O 2 gas after patterning the photoresist. It characterized by including a process.

이하, 본 발명의 반도체소자 식각방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of etching semiconductor devices of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 2b는 본 발명의 반도체소자 식각방법을 설명하기 위한 공정단면도이다.2A through 2B are cross-sectional views illustrating a method of etching semiconductor devices according to the present invention.

본 발명의 반도체소자 식각방법은 도 2a에 도시한 바와같이 반도체기판(21)상에 고온저압유전체막(22)을 증착한다.In the semiconductor device etching method of the present invention, as shown in FIG. 2A, a high temperature low pressure dielectric film 22 is deposited on a semiconductor substrate 21.

고온저압유전체막(22)상에 폴리실리콘층(23)을 형성하고 폴리실리콘층(23)상에 산화막 또는 질화막(24)을 증착한다.A polysilicon layer 23 is formed on the high temperature low pressure dielectric film 22 and an oxide film or nitride film 24 is deposited on the polysilicon layer 23.

그리고 상기 산화막 또는 질화막(24)상에 층간절연막으로서 BPSG층(25)을 형성한다.A BPSG layer 25 is formed on the oxide film or nitride film 24 as an interlayer insulating film.

이어, 도 2b에 도시한 바와같이 상기 BPSG층(25)상에 포토레지스트(26)를 도포한 후 노광 및 현상공정으로 상기 포토레지스트(26)를 패터닝한다.Subsequently, as shown in FIG. 2B, the photoresist 26 is applied onto the BPSG layer 25, and then the photoresist 26 is patterned by an exposure and development process.

그리고 패터닝된 포토레지스트(26)를 마스크로 이용하여 상기 BPSG층(25), 산화막 또는 질화막(24) 및 폴리실리콘층(23)을 동시에 식각한다.The BPSG layer 25, the oxide film or the nitride film 24, and the polysilicon layer 23 are simultaneously etched using the patterned photoresist 26 as a mask.

이때 상부전력 하부전력이 독립적으로 컨트롤되는 저압의 고밀도 플라즈마 소오스에서 Ar, CHF3, O2가스에 N2가스를 첨가하여 산화막 또는 질화막과 폴리실리콘층과의 식각선택비을 낮추어서 동일한 공정조건을 유지하여준다.In this case, N 2 gas is added to Ar, CHF 3 , and O 2 gas in a low-pressure high-density plasma source in which the upper power and lower power are independently controlled to lower the etching selectivity of the oxide or nitride film and the polysilicon layer to maintain the same process conditions. give.

기본적으로 산화막 또는 질화막을 식각하기 위해서는 Ar, CHF3, O2가스에 N2가스를 첨가할 경우, N2가스의 스퍼터링효과에 의해서 폴리실리콘층의 결합이 약화된다.Basically, in order to etch the oxide film or the nitride film, when N 2 gas is added to Ar, CHF 3 and O 2 gas, the bonding of the polysilicon layer is weakened by the sputtering effect of the N 2 gas.

또한 CHF3등의 에쳔트를 더욱 효과적으로 분해하여 약해진 폴리실리콘과의 결합을 가능하게 만든다.It also more effectively breaks down the etchant, such as CHF 3 , to allow weak polysilicon bonding.

이때 상기 상부전력은 1000∼2500W이고 하부전력은 500∼2000W의 범위로 한다.At this time, the upper power is in the range of 1000 to 2500W and the lower power is in the range of 500 to 2000W.

그리고 상기 Ar, CHF3, O2가스 대신에 C4F3, C3F8, CH3F, CO, CF4등의 C-F계열의 모든종류의 가스에도 N2가스를 첨가하여 사용할 수 있다.In addition to the Ar, CHF 3 and O 2 gas, N 2 gas may be added to all kinds of CF-based gases such as C 4 F 3 , C 3 F 8 , CH 3 F, CO, and CF 4 .

결과적으로 한 번의 포토공정으로 게이트라인 및 셀 캐패시터 형성에 따른 폴리실리콘층과 산화막 또는 질화막과의 식각선택비를 낮추어 동시에 식각하는 것이다.As a result, the etching selectivity of the polysilicon layer and the oxide film or the nitride film by etching the gate line and the cell capacitor is reduced by one photo process.

이상 상술한 바와같이 본 발명의 반도체소자 식각방법은 다음과 같은 효과가 있다.As described above, the semiconductor device etching method of the present invention has the following effects.

한 번의 포토공정으로 동시식각이 이루어지므로 기존의 포토레지스트 제거 및 세정작업을 생략할 수 있어 공정이 간편하다.Simultaneous etching is performed by one photo process, so the existing photoresist removal and cleaning operations can be omitted, thus simplifying the process.

그리고 동시식각이 이루어지므로 각 식각층에 따른 공정진행조건이나 장비의 변경 등이 불필요하다.And since simultaneous etching is performed, it is not necessary to change the process progress condition or equipment according to each etching layer.

또한 폴리머를 식각하기 위한 추가적인 마스킹공정이 불필요하다.In addition, no additional masking process is required to etch the polymer.

Claims (4)

기판상에 절연층을 개재하여 폴리실리콘층을 형성하는 공정과,Forming a polysilicon layer on the substrate via an insulating layer; 상기 폴리실리콘층상에 산화막을 증착한 후 산화막상에 포토레지스트를 도포하는 공정과,Depositing an oxide film on the polysilicon layer and then applying a photoresist on the oxide film; 상기 포토레지스트를 패터닝한 후 Ar, CHF3, O2가스에 N2가스를 첨가하여 상기 산화막과 폴리실리콘층과의 저선택성을 이용한 식각공정으로 상기 산화막과 폴리실리콘층을 동시에 식각하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체소자 식각방법.Patterning the photoresist, and then adding N 2 gas to Ar, CHF 3 , and O 2 gas to etch the oxide film and the polysilicon layer simultaneously by an etching process using low selectivity of the oxide film and the polysilicon layer. Etching method of a semiconductor device, characterized in that consisting of. 제 1 항에 있어서,The method of claim 1, 산화막과 폴리실리콘층의 동시식각시 사용되는 상부전력은 1000∼2500W이고 하부전력은 500∼2000W의 범위로 하는 것을 특징으로 하는 반도체소자 식각방법.A method of etching a semiconductor device, characterized in that the upper power is used in the simultaneous etching of the oxide film and the polysilicon layer is 1000 to 2500W and the lower power is 500 to 2000W. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘층과 동시에 식각되는 산화막 대신에 질화막을 적용하는 것을 특징으로 하는 반도체소자 식각방법.And a nitride film is applied instead of the oxide film simultaneously etched with the polysilicon layer. 제 1 항에 있어서,The method of claim 1, 상기 Ar, CHF3, O2가스 대신에 C4F3, C3F8, CH3F, CO, CF4등의 C-F계열의 모든종류의 가스에 적용되는 것을 특징으로 하는 반도체소자 식각방법.A method of etching a semiconductor device, characterized in that it is applied to all kinds of gases of CF series such as C 4 F 3 , C 3 F 8 , CH 3 F, CO, CF 4 instead of Ar, CHF 3 , O 2 gas.
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