KR19990000475A - Signature circuit of semiconductor chip - Google Patents

Abstract

The present invention discloses a signature circuit of a semiconductor chip. The MOS transistor and a plurality of diodes are connected in series between an external power supply and an external pin of a semiconductor chip and a signal generated inside the chip is input to the gate. In other words, the use of MOS transistors instead of fuses provides more accurate chip information during signature testing.

Description

Signature Circuit of Semiconductor Chip

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a signature circuit of a semiconductor chip.

The signature circuit in the DRAM is a circuit that indicates the state in which the DRAM is set.

1 is a signature circuit of a semiconductor chip according to the prior art.

Referring to FIG. 1, a signature circuit includes a plurality of MOS transistors Q1, Q2, Q3, Q4, and Q5 connected in series with a gate and a drain connected to an external pin of a semiconductor chip in the form of a diode. A fuse connected to the MOS transistors Q1, Q2, Q3, Q4, and Q5, and an external power connected to the fuse.

Therefore, each of the MOS transistors Q1, Q2, Q3, Q4, and Q5 is a diode having a positive external pin direction and a negative external power direction, and is a current when the voltage applied to the external pin is greater than the external power source. Flows from the external pin to the external power source. In this case, when the fuse is blown, no current flows, and when the fuse is connected, information on the packaged chip may be obtained using a property of flowing current.

For example, if the DRAM is designed to have 2K or 4K refresh mode, the packaging process must decide whether to package 2K refresh mode or 4K refresh mode. To package in 2K refresh mode, disconnect the fuse connected to the external pin, and package the fuse connected to the external pin to package in 4K, and apply a higher voltage than the external power to the external pin after packaging. External pins packaged in mode and no current flow are packaged in 2K refresh mode.

However, if the fuse is cut to 2K in the wafer state and 4K in the package, there is a problem in that an error occurs when the signature circuit is tested without the correct information. In other words, once the fuse is blown in the wafer state, the package must be blown.

Accordingly, the present invention is a signature circuit for solving the above problems.

An object of the present invention is to provide a signature circuit of a semiconductor chip capable of knowing more accurate chip information.

1 is a signature circuit of a semiconductor chip according to the prior art.

2 is a signature circuit of a semiconductor chip according to the present invention.

In order to achieve the above object, the present invention is characterized in that between the external power (External Power) and the external pin (External Pin) of the semiconductor chip, a MOS transistor and a plurality of diodes in which a signal generated inside the chip is input to the gate is connected in series A signature circuit of a semiconductor chip is provided.

The diode is preferably a MOS transistor having a gate and a drain connected thereto.

The signature circuit of the semiconductor chip according to the present invention has an advantage that more accurate chip information can be known at the time of signature test by using a MOS transistor instead of a fuse.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a signature circuit of a semiconductor chip according to the present invention.

Referring to FIG. 2, the signature circuit includes first to fifth MOS transistors Q1, Q2, Q3, Q4, and Q5 connected in series with a gate and a drain connected to an external pin of a semiconductor chip in the form of a diode. ), A sixth MOS transistor Q6 connected to the first to fifth MOS transistors Q1, Q2, Q3, Q4 and Q5, and an external power source connected to a source of the sixth MOS transistor Q6. It is composed. A source of the fifth MOS transistor Q5, which is one end of the first to fifth MOS transistors Q1, Q2, Q3, Q4, and Q5, is connected to the drain of the sixth MOS transistor Q6, and the first to fifth MOS transistors Q6. A drain of the first MOS transistor Q1, which is the other end of the fifth MOS transistors Q1, Q2, Q3, Q4 and Q5, is connected to the external pin.

Therefore, each of the first to fifth MOS transistors Q1, Q2, Q3, Q4, and Q5 is a diode in which the external pin direction is + and the external power direction is-, and the voltage applied to the external pin is the external power source. When greater, current flows and the direction is from the external pin to the external power source.

The sixth MOS transistor Q6 plays a switching role of connecting or disconnecting the external power supply and the external pin according to an internally generated signal. For example, when DRAMs are designed in several modes: × 4, × 8, and × 16, packaging into × 4 generates a signal internally indicating that it is × 4, turning on the signature circuit indicating that it is × 4, and turning on × 8 and Turn off the signature circuit associated with x16.

Therefore, if the fuse is blown to × 4 and the × 4 quantity remains and the × 16 quantity is insufficient, the signature test for packaging the fuse circuits of the signature circuit for × 4 as × 16 does not give the correct information. The present invention uses a MOS transistor and an internally generated signal to enable more accurate signature test.

In the signature circuit, the drain of the sixth MOS transistor Q6 is connected to the external pin, and the source of the sixth MOS transistor Q6 is connected to the first to fifth MOSs as follows. Connected to the drain of the first MOS transistor Q1 at one end of the transistors Q1, Q2, Q3, Q4, Q5, and the first to fifth MOS transistors Q1, Q2, Q3, Q4, Q5 The source of the fifth MOS transistor Q5 at the other end may be connected to the external power source.

The sixth MOS transistor Q6 may be formed between any one of the first to fifth MOS transistors Q1, Q2, Q3, Q4 and Q5.

The present invention is not limited to this, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, the signature circuit of the semiconductor chip according to the present invention has an advantage that more accurate chip information can be known at the time of signature test by using a MOS transistor instead of a fuse.

Claims (5)

A signature circuit of a semiconductor chip, comprising a plurality of diodes connected in series with a MOS transistor in which a signal generated inside the chip is input to a gate between an external power source and an external pin of the semiconductor chip. The method of claim 1, wherein the diode A signature circuit for a semiconductor chip, comprising: a MOS transistor having a gate and a drain connected thereto. The MOS transistor of claim 1, wherein the source of the MOS transistor is connected to the external power supply, one end of the series connected diodes is connected to the drain of the MOS transistor, and the other end of the series connected diodes is connected to the external pin. Signature circuit of a semiconductor chip, characterized in that connected. The MOS transistor of claim 1, wherein a drain of the MOS transistor is connected to the external pin, one end of the series connected diodes is connected to a source of the MOS transistor, and the other end of the series connected diodes is connected to the external power source. Signature circuit of a semiconductor chip, characterized in that connected. The signature circuit of claim 1, wherein the MOS transistor is connected between the diode and the diode.