KR19980085821A - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing cracks that may occur at an edge of a chip.

The method of manufacturing a semiconductor device of the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate defined by a chip region and a scribe lane region, and forming a metal layer on the insulating film for metal adhesion and the insulating film for metal adhesion on the interlayer insulating film. And selectively patterning the metal layer to form a metal layer pattern having a width to be formed in a chip region, and to form a metal layer having a width to be tested on the scribe lane region.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing cracks that may occur at an edge portion of a chip during a feeding process.

In general, processes on wafers require high accuracy, and wafers that deviate from the proper process during processing or those with low yields must be picked out immediately.

Therefore, the wafer is subjected to various tests and evaluations as it passes through the process step.

Such test and evaluation methods create test patterns in the scribe lanes between the chips of the wafer and inspect them after completion of the process, or empty wafers or wafers contained in a wafer holder. The test wafers using pieces were evaluated according to the main process.

Hereinafter, a method of manufacturing a conventional semiconductor device will be described with reference to the accompanying drawings.

FIG. 1 is a plan view of a test pattern in a scribe lane region of a conventional semiconductor device. The test pattern in the scribe lane region 1 of a conventional semiconductor device shows a structure of a metal pad.

First, a first metal layer pattern having a rectangular shape having a predetermined size as a scribe lane region 1 and a chip region 2 adjacent to the scribe lane region 1 above the semiconductor substrate 11 where the chip region 2 and the scribe lane region 1 are defined. 13 is formed, and the second metal layer pattern 16 is in contact with the first metal layer pattern 13 through a contact hole 15 having a smaller size than that of the first metal layer pattern 13.

2A to 2C are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device taken along line II ′ of FIG. 1.

First, as shown in FIG. 2A, the first insulating film 12 is formed on the semiconductor substrate 11 defined by the chip region 2 and the scribe lane region 1. Subsequently, a metal layer is formed on the first insulating layer 12, and then selectively patterned (photolithography process + etching process) to thereby form a chip region 2 adjacent to the scribe lane region 1 including the scribe lane region 1. The first metal layer pattern 13 is formed on the first insulating film 12. In this case, the first insulating layer 12 is formed to insulate the semiconductor device (not shown) formed on the chip region 1 of the semiconductor substrate 11 prior to the metal layer deposition process for the purpose of insulating. As a layer dielectric layer, it is usually formed using BPSG (BoroPhosphor Silicate Glass) having excellent fluidity. Although not shown, the first metal layer pattern 13 is formed in a pattern to be formed in the chip region 1, and is formed in a width to be tested or evaluated in the scribe lane 1 region. Not only (1) but also the chip region 2 is formed to extend a predetermined interval.

As shown in FIG. 2B, the second insulating film 14 is formed on the entire surface of the first insulating film 12 including the first metal layer pattern 13. Subsequently, the photoresist film PR is coated on the second insulating film 14 and then selectively patterned to remove the photoresist film PR on the upper side of the first metal layer pattern 13 by an exposure and development process. Next, the second insulating layer 14 is selectively removed by an etching process using the patterned photoresist layer PR as a mask to form a contact hole 15 exposing an upper surface of the first metal layer pattern 13. At this time, the first insulating film 12 formed under the first metal layer pattern 13 is formed of BPSG. Such BPSG is known to have excellent fluidity but relatively poor adhesion to the metal layer. The second insulating layer 14 is an inter metal dielectric (IMD) layer formed to insulate or protect the first metal layer pattern 13, and is typically formed using TEOS.

As shown in FIG. 2C, the photosensitive film PR is removed. Subsequently, a metal layer is formed on the entire surface of the second insulating film 14 including the contact hole 15, and then selectively patterned to remain only on the contact hole 15 and the second insulating film 14 adjacent to the contact hole 15. The second metal layer pattern 16 is formed to complete a test pattern composed of the first and second metal layer patterns 13 and 16.

Subsequently, although not illustrated, the semiconductor substrate 11 is separated into individual chips after a test or evaluation process is performed on the first and second metal layer patterns 13 and 16 formed in the scribe lane region 1. In order to achieve this, a sawing process based on the scribe lane region 1 and a package process are performed in order.

In the conventional method of manufacturing a semiconductor device, the adhesion between the first insulating film and the first metal layer pattern formed of BPSG in part A of FIG. 2C and the first metal layer pattern during the process of separating the semiconductor substrate defined by the scribe lane region through a sawing process is low. As the first metal layer is separated, the interface between the first insulating film and the second insulating film is exposed, or a crack can be generated to prevent penetration of moisture through the portion, thereby improving reliability and yield of the chip region semiconductor device. There was a problem that could be reduced.

The present invention has been made to solve the problems of the conventional method of manufacturing a semiconductor device as described above to provide a highly reliable semiconductor device manufacturing method by improving the adhesion of the metal layer by forming an insulating film having excellent adhesion at the interface between the BPSG layer and the metal layer. Have a purpose

1 is a plan view of a test pattern in a scribe lane region of a conventional semiconductor device

2A through 2C are cross-sectional views illustrating a manufacturing process of a conventional semiconductor device taken along line II ′ of FIG. 1.

3 is a plan view of a test pattern in the scribe lane region of the semiconductor device of the present invention;

4A to 4C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention taken along line II-II ′ of FIG. 3.

Explanation of symbols for main parts of the drawings

31 semiconductor substrate 32 first insulating film

33 second insulating film 34 first metal layer pattern

35: third insulating film 36: contact hole

37: second metal layer pattern

A method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate defined by a chip region and a scribe lane region, and forming a metal layer on the insulating film for metal adhesion and the insulating film for metal adhesion on the interlayer insulating film. Selectively patterning the metal layer to form a metal layer pattern having a width to be formed in a chip region, and patterning the metal layer to a width to be tested on the scribe lane region.

Such a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.

3 is a plan view of a test pattern in the scribe lane region of the semiconductor device of the present invention.

The test pattern in the scribe lane region 21 of the semiconductor device of the present invention is a scribe lane 21 region and a chip region 22 adjacent to the scribe lane region 21 above the semiconductor substrate 31 in which the scribe lane region 21 is defined. A first metal layer pattern 34 having a quadrangular shape is formed, and a second metal layer pattern contacted with the first metal layer pattern 34 through a contact hole 36 having a smaller size than that of the first metal layer pattern 34 ( 37).

4A to 4C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention taken along line II-II ′ of FIG. 3.

First, as shown in FIG. 4A, the first insulating film 32 and the second insulating film 33 are sequentially formed on the semiconductor substrate 31 defined by the chip region 22 and the scribe lane region 21. Subsequently, a metal layer is formed on the second insulating layer 33, and then the metal layer is selectively patterned (photolithography process + etching process) to form a chip region adjacent to the scribe lane region 21 including the scribe lane region 21. (22) A first metal layer pattern 34 is formed on the first insulating film 32 on the upper side. In this case, the first insulating layer 32 is formed to insulate a semiconductor device (not shown) formed on the chip region 22 of the semiconductor substrate 31 by a prior process prior to the metal layer deposition process. Layer Dielectric) layer. In this case, the first insulating layer 32 was formed using BPSG. The second insulating layer 33 is formed using a material having excellent adhesion with the metal layer to be formed in a subsequent step, and is formed using undoped polysilicon or HLD (High temperature Low pressure Dielectric). In addition, although not shown in the drawing, the first metal layer pattern 34 is formed in a pattern having a size to be formed in the chip region 22 and is formed in a size to be tested or evaluated in the scribe lane 21 region. Typically, not only the scribe lane region 21 but also the edge portion of the chip region 22 is formed to extend a predetermined interval.

As shown in FIG. 4B, a third insulating film 35 is formed on the entire surface of the second insulating film 33 including the first metal layer pattern 34. Subsequently, the photoresist film PR is coated on the third insulating film 35 and then selectively patterned to remove the photoresist film PR on the upper side of the first metal layer pattern 34 by an exposure and development process. Next, the third insulating layer 35 is selectively removed by an etching process using the patterned photoresist film PR as a mask to form a contact hole 36 exposing an upper surface of the first metal layer pattern 34. In this case, the third insulating layer 35 is an inter metal dielectric (IMD) layer formed to insulate or protect the first metal layer pattern 34.

As shown in FIG. 4C, the photosensitive film PR is removed. Subsequently, a metal layer is formed on the entire surface of the third insulating layer 35 including the contact hole 36, and then selectively patterned to remain only on the contact hole 36 and the third insulating layer 35 adjacent to the contact hole 36. The second metal layer pattern 37 is formed to complete a test pattern composed of the first and second metal layer patterns 34 and 37.

Subsequently, although not shown in the drawing, a test or evaluation process is performed on the first and second metal layer patterns 34 and 37 formed in the scribe lane area 21, and then the semiconductor substrate 31 is individually chipped. A sawing process and a package process based on the scribe lane area 21 are performed in order to separate them.

In the method of manufacturing a semiconductor device according to the present invention, a close-up insulating film having excellent adhesion to a metal layer is formed, and then a metal layer is formed. Thus, cracks can be prevented during stress or impact. Since cracks can be prevented to prevent penetration of moisture through the portions, there is an effect of providing a method of manufacturing a semiconductor device having improved reliability and yield.

Claims (2)

Forming an interlayer insulating film on the semiconductor substrate defined by the chip region and the scribe lane region; Forming a metal layer on the metal adhesion layer and the metal adhesion layer on the interlayer insulating layer; Selectively patterning the metal layer to form a metal layer pattern having a width to be formed in a chip region, and patterning the metal layer to a width to be tested on the scribe lane region. The method of claim 1, wherein the insulating film for metal adhesion is formed of undoped polysilicon or HLD.