KR19980084669A - counter - Google Patents

Abstract

A first logic gate for inputting a clock signal and a feedback signal to perform logic operation, a second logic gate for inputting a feedback signal and a reset signal for logic operation, a logic gate for inputting the output of the reset signal and the first logic gate, A third logic gate for inputting the outputs of the third logic gate, the third logic gate, and an inverter for inverting an output of the third logic gate; First and second transfer gates for selectively outputting a fixed signal for maintaining the output value and a high level at all times to output a set signal, and selectively outputting an output value and a fixed signal of the inverter according to an input value set by the user, A set-input terminal configured by third and fourth transfer gates for outputting a set signal and a set signal outputted from the set- Is activated by a signal and the clock signal, the set-is configured to include a flip-flop for outputting a feedback signal to the input stage.

Description

counter

The present invention relates to a counter, and more particularly to a counter that minimizes size and begins inputting a counter (the start of counting) according to an input setting.

Hereinafter, conventional counters will be described with reference to the accompanying drawings.

FIG. 1 shows the internal configuration of a conventional 4-bit counter in digital logic.

As shown in FIG. 1, the conventional counter is composed of a plurality of logic gates and a flip-flop.

Here, the flip-flop uses a J-K flip-flop.

The conventional counter includes first, second, third, and fourth flip-flops 11, 13, 15, and 17, and an input value applied to the four flip-flops by logical operation of the input value and the load signal is set to 1 A first logic unit 19 for determining the input value of the first flip-flop 11 by logic operation of the output value and the count value of the most significant bit among the outputs of the first logic unit 19, A first flip-flop 11, a second flip-flop 13, and a third flip-flop 13. The first flip-flop 11 and the second flip- 3 logic part 23 and the second flip flop 13 and the output value and the count value of the next higher bit among the output of the first logic part 19 and outputs the input value of the third flip- The output of the third logic unit 25, the third flip-flop 15 and the output of the least significant bit of the output of the first logic unit 19, and the count value The fourth consists of a fifth logic unit 27, which determines the input to the flip-flop 17.

Here, a clear signal and a clock signal are applied to each flip-flop, and the count signal and the outputs of the first, second, third, and fourth flip-flops 11, 13, 15, And an AND gate 29 which carries out carry out is further constructed.

In addition, a load signal is applied to the first logic unit 19 to perform a logic operation on the input bit.

The third, fourth and fifth logic units 23, 25 and 27 include NAND gates 23a, 25a and 27a for logically calculating an output value of the front end flip-flop and the count value, And two OR gates 23b, 25b and 27b for inputting a value of a corresponding input bit output from the first logic unit 19 and performing a logical operation.

The operation of the conventional counter configured as described above is as follows.

As shown in FIG. 1, input bits I ₁ , I ₂ , I ₃ , and I ₄ are set by a user to a specific input value, and the first, second, The outputs (A ₁ , A ₂ , A ₃ and A ₄ ) of the third and fourth flip-flops 11, 13, 15 and ₁₇ are determined.

Generally, the counter should change the logic of the counter depending on the application.

That is, the fields used vary depending on how you change the logic of the counter.

To solve this hassle, a counter according to the prior art is focused.

The counter according to the prior art is possible by setting the input value of the counter without changing the logic of the counter even if the application fields are different from each other.

Here, the input value set by the user is a value indicating the time at which the counter counts.

This operation will be described as a simple table.

Here, the symbol X indicates do not care and the symbol ↑ indicates that there is no change in value.

As shown in the table, when the clear signal is 1, the clock signal is unchanged, the load signal is 0, and the count signal is 1, the counter starts counting.

If the clear signal is 1, the clock signal is do not care, the load signal is 0, and the count signal is 0, the counter does not count. That is, no operation is performed.

Of course, as a condition for implementing the above table, the user has to set the input bit, that is, the input value informing the start time of the counter.

Therefore, the fact that the counter starts counting means that the counting operation is started according to the input value set by the user as described above.

In this way, regardless of the application field of the counter, since the user only needs to set the initial value of the counter, it is not necessary to change the logic of the counter.

However, since the number of bits in the conventional counter is proportional to the number of input stages of the third, fourth, and fifth logic units, the number of input stages increases as the number of bits increases. As a result, There was a problem.

It is an object of the present invention to provide a counter suitable for minimizing an area by adding only a simple logic gate regardless of an increase in the number of bits.

1 is a block diagram of an internal configuration of a counter according to the prior art.

2 is a schematic diagram of a counter according to the present invention;

3 is a partial detail view according to the counter of the present invention

4 is a block diagram of a counter according to an embodiment of the present invention.

Figure 5 is a waveform diagram according to one embodiment of Figure 4;

DESCRIPTION OF THE REFERENCE NUMERALS

31: Set-input stage 33: Flip-flop

31a: first logic gate 31b: second logic gate

31c: third logic gate 31d: fourth logic gate

31e: first inverters 31f, 31g: first and second transfer gates

31h and 31i: third and fourth transfer gates

According to an aspect of the present invention, there is provided a counter comprising a first logic gate for inputting a clock signal and a feedback signal to perform logic operation, a second logic gate for inputting a feedback signal and a reset signal to perform logic operation, A third logic gate for receiving the output of the first logic gate and performing a logic operation, a fourth logic gate for receiving the outputs of the second and third logic gates for logic operation, an inverter for inverting the output of the third logic gate, First and second transfer gates for selectively outputting a fixed signal which always maintains a high level and an output value of the fourth logic gate in accordance with an input value set by the inverter, And a third and a fourth transfer gate for selectively outputting a fixed signal and outputting a reset signal, And a flip-flop which is operated by a set signal or a reset signal and a clock signal output from the set-input terminal and outputs a feedback signal to the set-input terminal.

Hereinafter, a counter according to the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a counter according to the present invention.

2, the counter of the present invention includes a set-input 31 for setting a value indicating a counting time of a counter and a flip-flop 33 connected to a set or reset terminal of the set- .

Here, the set-input terminal 31 is fed back with the output value of the flip-flop 33.

A fixed signal UP fixed at a high level and a reset or set signal are applied to the set-input terminal 31 at all times.

The flip-flop 33 operates by inputting one of the reset or set signals selectively output from the set-input terminal 31.

The set-input stage according to the thus configured counter of the present invention will be described in more detail.

3 is a detailed configuration diagram of a set-input terminal according to the present invention.

As shown in FIG. 3, the set-input stage 31 of the present invention is composed of four transfer gates, two OR gates, one NAND and AND gate, and one inverter.

A first logic gate 31a for inputting a clock signal, a signal fed back from the flip-flop, and a reset or set signal to perform logic operation; and a second logic gate 31a for receiving a signal fed back from the flip- A third logic gate 31c for inputting the output of the first logic gate 31a and a reset or set signal for logical operation, A fourth logic gate 31d for inputting the output of the second logic gate 31b and the output of the third logic gate 31c and performing a logic operation on the output of the third logic gate 31c, An inverter 31e and four transmission gates 31f for selectively outputting the output of the fourth logic gate 31d and the output of the first inverter 31e according to the input value set by the user and the fixed signal UP , 31g, 31h, 31i.

Here, the input value set by the user is input to the non-inverting terminal and the inverting terminal is connected to the first transfer gate 31f to which the inverted value of the input value set by the user is inputted, A second transfer gate 31g which is input to the inverting terminal and to which the inverted value of the input value set by the user is input to the inverting terminal; and a second transfer gate 31g, And third and fourth transfer gates 31h and 31i into which one input value is input to the non-inverting terminal and the inverted value of the input value set by the user is input to the inverting terminal.

The inversion of the input value set by the user is performed by the second inverter 31j as shown in Fig.

The operation of the counter according to the present invention will now be described.

First, according to FIG. 2, the set-input terminal 31 for driving the flip-flop 33 sets the start time of the counter by the set input values S ₁ , S ₂ , S ₃ .

The fixed signal of the set-input 31 always maintains a high level, and the flip-flop 33 feeds a high-level signal back to the set-input 31 only when its output is high.

This feedback signal serves as a load signal.

This will be described in more detail with the above-described schematic description in mind.

As shown in FIG. 3, a clock and a feedback signal output a high signal through the first logic gate 31a by a half period of the clock signal.

The signal output from the first logic gate 31a is input to the third logic gate 31c together with the reset signal or the set signal to generate an actual load signal.

The actual load signal, that is, the output signal of the third logic gate 31c is inverted by the first inverter 31e and used as a set signal.

The feedback signal input from the flip-flop 33 and the reset or set signal are output as a high signal of one period of the clock signal through the second logic gate 31b.

Therefore, the signal output from the second logic gate 31b and the signal output from the third logic gate 31c are input to the fourth logic gate 31d.

At this time, the fourth logic gate 31d outputs a low signal equivalent to half a period of the clock signal.

The signal that has passed through the fourth logic gate 31d is used as a reset signal.

Here, S ₁ of the input values set by the user determines whether to use the set signal or the reset signal.

Ten thousand and one, S ₁ In this case, a high signal, in the case where the output value of the first inverter (31e) transmitted to the set value of the flip-flop 33 and the S ₁ is Righteous foil, the fourth flip-flop output of the logic gate (31d) (33 ) As a reset value.

When the output signal of the first inverter 31e is transmitted to the set of the flip-flop 33 as S ₁ is a high signal, a fixed signal that always maintains a high level is transmitted to the reset.

Therefore, the reset does not actually operate but only operates the set.

With this method, the user sets S ₂ and S ₃ .

Here, the process of transferring the output signal of the first inverter 31e and the output signal of the fourth logic gate 31d to the set or reset of the flip-flop 33 is referred to as four transfer gates 31f, 31g, 31h, 31i ).

As described above, when S ₁ is a high signal, the fourth transfer gate 31d is turned on and the output value of the first inverter 31e is transferred to the set through the fourth transfer gate 31d.

If S ₁ is a low signal, the first transfer gate 31a is turned on and the output value of the fourth logic gate 31d is transferred to the reset via the first transfer gate 31a.

In this way, S ₂ and S ₃ can be set to values desired by the user.

Meanwhile, FIG. 4 is a configuration diagram according to an embodiment using the counter of the present invention.

As shown in FIG. 4, according to the embodiment of the present invention, the number of set-inputs is connected to the number of bits.

The embodiment of the present invention exemplifies a 3-bit synchronous counter, and includes a first logic gate 31a for inputting a clock signal, a signal fed back from the flip-flop, and a reset or set signal, A second logic gate 31b for receiving a signal fed back from the flip-flop and the reset or set signal for logical operation, and a second logic gate 31b for inputting the output of the first logic gate 31a and a reset or set signal, A third logic gate 31c for inputting an output of the second logic gate 31b and an output of the third logic gate 31c and performing a logic operation on the output of the third logic gate 31c, 31e and an output of the first inverter 31e according to the input value set by the user and the fixed signal UP, A first set-input for selectively outputting A first flip-flop 41a operated by a set signal or a reset signal output from the first set-input terminal 41 and a clock signal, and a second flip- A second set-input 43 configured to selectively output the output of the first inverter 31e and the output of the fourth logic gate 31d, and a second set- A second flip-flop 43a that operates in response to a reset signal and a clock signal output from the first flip-flop 41a, and a second flip-flop 43a that is formed in parallel with the second set- A third set-input terminal 45 for selectively outputting the output of the fourth logic gate 31d and the set signal or reset signal output from the third set-input terminal 45, And a third flip-flop 45a operated by a clock signal output from the third flip-flop 45a.

The input values S ₁ , S ₂ , and S ₃ are set by the user at the first, second, and third set-inputs 41, 43, and 45, respectively.

And a fifth logic gate 47 for logic operation of the signals output from the non-inverting output terminals of the first, second and third flip-flops 41a, 43a and 45a.

In addition, the most significant bit output Out 1 of the 3-bit output is obtained from the first flip flop 41a, and Out 2 and Out 3 are similarly obtained from the second and third flip flops 43a and 45a.

5 is a waveform diagram according to the 3-bit synchronization counter of FIG.

The reset signal changes from high to low level as shown in Fig. 5, and the fixed signal is always a high signal at this time.

When the value of the input value S ₁ is set to 1, the value of S ₂ is set to 0, and the value of S ₃ is set to 0 by the user, the values of the outputs Out 1, Out 2, and Out 3 are obtained.

In other words, the output value is obtained which is changed as shown in Fig. 5 Setting the value of S _1, S _2, S ₃ to 100.

To be changed here means to count.

As described above, the counter of the present invention has the following effects.

The number of logic gates increases according to the number of bits in the related art. On the other hand, since the present invention uses a set-input stage, only four transfer gates per bit need be added, so that the size can be minimized.

That is, the area can be minimized since only four transfer gates need to be added per bit without increasing the number of inputs or increasing the number of logic gates as the number of bits increases.

Claims (5)

A first logic gate for inputting a clock signal and a feedback signal to perform logic operation, a second logic gate for inputting a feedback signal and a reset signal for logic operation, a logic gate for inputting the output of the reset signal and the first logic gate, A third logic gate for inputting the outputs of the third logic gate, the third logic gate, and an inverter for inverting an output of the third logic gate; First and second transfer gates for selectively outputting a fixed signal for maintaining the output value and a high level at all times to output a set signal, and selectively outputting an output value and a fixed signal of the inverter according to an input value set by the user, A third-input terminal having a third and a fourth transfer gate for outputting a signal, And a flip-flop which is operated by a set signal or a reset signal and a clock signal output from the set-input terminal and outputs a feedback signal to the set-input terminal. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the first transfer gate is applied with an input value set by the user to the inverting terminal, the input value is applied to the non-inverting terminal through the inverter, And an input value passed through the inverter is applied to the inverting terminal. 2. The nonvolatile memory device according to claim 1, wherein the third transfer gate is configured such that an input value set by a user is applied to an inverting terminal and the input value is applied to a non-inverting terminal through an inverter, And the input value is applied to the inverting terminal through the inverter. 2. The counter of claim 1, wherein the flip-flop is an R-S flip-flop. 2. The counter according to claim 1, wherein the first logic gate is an AND gate, the second and third logic gates are an OR gate, and the fourth logic gate is a NAND gate.