KR19980084665A - Semiconductor Memory Device Having Data Output Driver Circuit - Google Patents

Abstract

A semiconductor memory device of the present invention includes a memory cell array having memory cells arranged in a matrix of rows and columns, the memory cell array storing information bits; An input transition detection circuit for detecting a state transition of an address signal or a chip activation signal from the outside and generating a pulse signal; A first voltage boosting circuit for generating a boosted voltage in response to the pulse signal, and outputting a boosted voltage when the data of the memory cell addressed by the address signal is logic '1'; A first delay circuit for receiving, inverting and delaying data of the addressed memory cell; A pull-up control circuit that receives data from the first delay circuit and the boosted voltage and outputs a pull-up signal; A second voltage boosting circuit generating the boosted voltage in response to the pulse signal, and outputting the boosted voltage when the cell data of the addressed memory cell is logic '1'; A second delay circuit for receiving, inverting and delaying the complementary data; A pull-down control circuit that receives the complementary data from the second delay circuit and the boosted voltage from the second voltage boost circuit and outputs a pull-down signal; An output driving circuit for outputting a logic '1' or a logic '0' in response to the pullup / pulldown signal from the pullup / pulldown control circuit.

Description

Semiconductor Memory Device Having Data Output Driver Circuit

The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device having memory cells for storing information bits.

Recently, as the demand for low power consumption of products increases, there is a need for a memory device that operates quickly even at a low power supply. Typically, the impact of the delay on the data output driver circuit at low supply voltage power on the overall product speed is a significant part. Therefore, reducing the delay caused by the data output driver circuit is an important center point for the implementation of the low voltage high speed memory device.

1 is a block diagram showing a configuration of a semiconductor memory device having a data output driving circuit according to the prior art.

Referring to FIG. 1, a semiconductor memory device includes a memory cell array 1, an address buffer circuit 2, a row selecting circuit 3, and a column selection circuit 3. column selecting circuit (4), sense amplifier circuit (5), data output buffer circuit (6), pull-up control circuit (7), pull-down control A pull-down control circuit 8, and an output driving circuit 9.

The array 1 is, as is well known, composed of memory cells arranged in a matrix of rows and columns for storing data. The address buffer 2, which receives an address signal from the outside, converts it into an internal address signal. The row selection circuit 3 receives a row address Ar among internal address signals to select a row of the array 1, and the column selection circuit 4 selects a column address of the internal address signals. address (Ac) is selected to select a column of the array (1). Subsequently, the sense amplifier circuit 5 detects, amplifies and outputs the data stored in the memory cells selected by the row / column selection circuits 3 and 4.

The data output buffer circuit 6 receives the data from the sense amplifier circuit 5 and buffers the data pairs D and ( ) The pull-up control circuit 7 and the pull-down control circuit 8 have data (D) and complementary data ( ) To control the output driving circuit 9 by outputting a pull-up signal DOU and a pull-down signal DOD.

The pull-up control circuit 7 is composed of a pMOSFET MP1 and an nMOSFET MN1. The gate electrode of the pMOSFET MP1 is connected to one output node N1 of the data output buffer circuit 6, and its current path is between the power supply and the one input terminal N2 of the output drive circuit 9. Is formed. The gate electrode of the nMOSFET MN1 is connected to one output node N1 of the buffer circuit 6, and a current path thereof is formed between one input terminal N2 of the output drive circuit 9 and ground. . The pull-down control circuit 8 also consists of a pMOSFET MP2 and an nMOSFET MN2. The gate electrode of the pMOSFET MP2 is connected to the other output node N3 of the data output buffer circuit 6 and its current path is between the power supply and the other input terminal N4 of the output drive circuit 9. Is formed. The gate electrode of the nMOSFET MN2 is connected to the other output node N3 of the buffer circuit 6, and a current path thereof is formed between the other input terminal N4 of the output drive circuit 9 and the ground. .

The output drive circuit 9 is composed of pull-up / pull-down transistors MN3 and MN4 composed of nMOSFETs, inverters IV1, and pMOSFET MP3. The current paths of the transistors MN3 and MN4 are sequentially formed in series between a power supply and ground, and furthermore, an output node N5 is connected to a connection point between them, and their gate electrodes are connected to the pull-up control circuit. (7) and output nodes N2 and N4 of the pull-down control circuit 8, respectively. The pMOSFET MP3 has a current path formed between the power supply and the output node N5 and a gate electrode connected to the output node N2 of the pull-up control circuit 7 via an inverter IV1.

With the output of the pull-up / pull-down control circuits 7 and 8 having the above-described circuit configuration, with the load of the output drive circuit 9 when driving the transistors MP3 and MN5 of the output drive circuit 9. This lowers its driving ability. As a result, there is a problem that the overall device operating speed is lowered.

Accordingly, an object of the present invention is to provide a data output driving circuit of a semiconductor memory device with improved operation speed at low power supply voltage.

1 is a block diagram showing a configuration of a semiconductor memory device having a data output driving circuit according to the prior art;

2 is a block diagram showing a configuration of a semiconductor memory device having a data output driving circuit according to a preferred embodiment of the present invention;

3 is an operation timing diagram according to an output of the input transition detection circuit of FIG. 2 when an address is applied;

4 is an operation timing diagram according to an output of the input transition detection circuit of FIG. 2 when a chip activation signal is applied;

* Explanation of symbols on the main parts of the drawings

1: memory cell array 2: address buffer

3: row select circuit 4: column select circuit

5: sense amplifier 6: data output buffer

7, 150: pull-up control circuit 8, 160: pull-down control circuit

9: output drive circuit 100: input transition detection circuit

110: first voltage boost circuit 120: first delay circuit

130: second voltage boost circuit 140: second delay circuit

According to one aspect of the present invention for achieving the above object, a memory cell array having memory cells arranged in a matrix of rows and columns, and for storing information bits; Detecting means for detecting a state transition of an address signal or chip activation signal from the outside to generate a pulse signal; Row selection means for decoding the address signal to select a row of the array; Column selection means for decoding the address signal to select a column of the array; Sensing amplifying means for detecting and amplifying data stored in a memory cell selected by said selecting means and outputting complementary data of said data; First voltage boosting means for generating a boosted voltage higher than a first voltage level in response to the pulse signal, and outputting the boosted voltage when the data from the sense amplifying means is at the first voltage level; First delay means for receiving, inverting and delaying data from the sense amplifying means; Pull-up control means for receiving data from the first delay means and the boosted voltage and outputting a pull-up signal; Second voltage boosting means for generating the boosted voltage in response to the pulse signal and outputting the boosted voltage when complementary data from the sense amplifying means is at a first voltage level; Second delay means for receiving, inverting and delaying the complementary data; Pull-down control means for receiving the complementary data from the second delay means and the boosted voltage from the second voltage boosting means and outputting a pull-down signal; Output drive means for driving an output node to one of a first voltage level and a second voltage level in response to the pull up / pull down signal from the pull up / pull down control means.

In this embodiment, the first voltage level is a power supply voltage level and the second voltage level is a ground voltage level.

In this embodiment, the voltage level of the pull-up signal is the boosted voltage level from the first voltage boosting means when the data from the first delay means is the ground voltage level, and the ground when the data is the power supply voltage level. Voltage level.

In this embodiment, the voltage level of the pull-down signal is a boosted voltage level from the second voltage boosting means when the data from the second delay means is the ground voltage level, and when the data is the power supply voltage level. The ground voltage level.

By such an apparatus, the output of the control circuits for controlling the transistors of the output driving circuit can be generated at a voltage higher than the power supply voltage.

Reference drawings according to embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

Referring to FIG. 2, the semiconductor memory device having the novel data output driving circuit of the present invention powers the power supply of the control circuits 150 and 160 for driving the output driving circuit 9. Voltage boosting circuits 110 and 130 for boosting to a voltage higher than the voltage and the input signals DD of the control circuits 150 and 160 after the boosted voltage is generated; Delay circuits 120 and 140 for causing D) to be applied to them. Therefore, by improving the driving capability of the data output driving circuit 9, the delay caused thereby can be reduced, and as a result, the overall chip operating speed can be improved.

2 is a block diagram showing a configuration of a semiconductor memory device having a data output driving circuit according to a preferred embodiment of the present invention.

Referring to FIG. 2, a semiconductor memory device according to a preferred embodiment of the present invention may include a memory cell array 1, an address buffer circuit 2, a row select circuit 3, a column select circuit 4, and a sense amplifier circuit ( 5), data output buffer circuit 6, input transient detecting circuit 100, first and second voltage boosting circuits 110 and 130, First and second delay circuits 120 and 140, pull-up control circuit 150, pull-down control circuit 160, and output driving circuit 9. Include. Here, the memory cell array 1, the address buffer circuit 2, the row select circuit 3, the column select circuit 4, the sense amplifier circuit 5, the data output buffer circuit 6, and the output drive circuit ( Since the output driving circuit 9 is the same as that of Fig. 1, description of them is omitted to avoid duplication of explanation.

The input transition detection circuit 100 detects that the address signal A or the chip enable signal OE is transitioned to generate a pulse signal DETP, and the activation period of the pulse signal DETP is It is apparent to those of ordinary skill in the art that it is implemented to be active while ensuring data output operation. The first voltage booster circuit 110 is activated when the pulse signal DETP from the input transition detection circuit 100 is applied, and as a result, generates a booster voltage Vboost higher than the power supply voltage. The circuit 110 then outputs the boosted voltage Vboost when the data D from the data output buffer 6 transitions to a high level (power supply voltage in the preferred embodiment). The first delay circuit 120 is for inverting and delaying the data D from the buffer circuit 6.

The pull-up control circuit 150 is composed of a pMOSFET MP4 and an nMOSFET MN5. The gate electrode of the pMOSFET MP4 is connected to the output node N6 of the first delay circuit 120, the current path of which is connected to the output node N7 of the first voltage boosting circuit 110 and the output driving circuit. It is formed between one input terminal N8 of (9), and its bulk and source terminal are mutually connected. The gate electrode of the nMOSFET MN5 is connected to the output node N6 of the first delay circuit 120, and a current path thereof is connected between one input terminal N8 of the output drive circuit 9 and ground. Is formed.

The second voltage boosting circuit 130 is activated when the pulse signal DETP from the input transition detection circuit 100 is applied, and as a result, generates a boost voltage Vboost higher than the power supply voltage. The circuit 130 then stores the data from the data output buffer 6 ( Outputs the boosted voltage Vboost when?) Transitions to a high level (in the preferred embodiment, the power supply voltage). The second delay circuit 140 stores the data from the buffer circuit 6 ( To reverse and delay).

Pull-down control circuit 160 is composed of pMOSFET MP5 and nMOSFET MN6. The gate electrode of the pMOSFET MP5 is connected to the output node N9 of the second delay circuit 140, the current path of which is connected to the output node N10 of the second voltage boosting circuit 130 and the output driving circuit. It is formed between the other input terminal N11 of (9), and its bulk and source terminal are mutually connected. The gate electrode of the nMOSFET MN6 is connected to the output node N9 of the second delay circuit 140, and its current path is connected between the other input terminal N11 of the output drive circuit 9 and ground. Is formed.

3 is an operation timing diagram according to the output of the input transition detection circuit of FIG. 2 when an address is applied, and FIG. 4 is an operation timing diagram according to the output of the input transition detection circuit of FIG. 2 when a chip activation signal is applied. Operation in accordance with the present invention is described below with reference to FIGS. 2 to 4. In order to avoid duplication of explanation, it will be described with reference to the operation timing diagram according to the address transition of FIG. 3 of the timing diagrams of FIGS. 3 and 4, but FIG. 4 is also operated in the same manner.

As shown in FIG. 3, the input transition detection circuit 100 which detects when the address signal A transitions generates a pulse signal DETP. As is well known, as the address signal transitions, the memory cells of the array 1 are selected by the address buffer 2 and the row / column selection circuits 3 and 4, and through the sense amplifier 5 Data stored in the selected memory cell is detected, amplified and applied to the data output buffer 6. As a result, as shown in Fig. 3, the data pairs D and D from the data output buffer 6 ( It is well known that one of the outputs) is output at a high level (the power supply voltage in the preferred embodiment). Here, data (D) is at a high level, and data ( Suppose) is low level.

Under these conditions, the first voltage boosting circuit 110 generates a boost voltage Vboost higher than the power supply voltage in response to the pulse signal DETP from the input transition detection circuit 100, and the high level data D Outputs the boosted voltage Vboost in response to At the same time, the first delay circuit 120 receives the data D, inverts it, delays it, and outputs the data D. As shown in FIG. In this case, after the boosted voltage Vboost is boosted, the low-level data DD is applied from the first delay circuit 120 to the pull-up control circuit 150. Accordingly, the pMOSFET MP4 of the pull-up control circuit 150 is turned on to output the pull-up signal DOU having the level of the boosted voltage Vboost, and as a result, the pull-up transistor MN7 of the output drive circuit 9 is output. Is turned on and outputs data '1'.

At the same time, low-level data ( Is applied to the second voltage boosting circuit 130, even if activated by the pulse signal DETP from the input transition detection circuit 100, it does not output it. Through the same procedure as described above, the pull-down transistor MN8 of the data output driving circuit 9 is turned off. And, it is obvious to those skilled in the art that the process of outputting data '0' under the opposite conditions is also output according to the same procedure. In a semiconductor memory device having a data output driving circuit according to the present invention, a boosting voltage level of which the gating voltage of the pull-up transistor MN7 of the output driving circuit 9 is higher than the power supply voltage level through the first voltage boosting circuit 110 ( Since it is applied to Vboost, the output node N12 driven by it can be sufficiently driven by the power supply voltage. As a result, by improving the driving capability of the output drive circuit 9, it is possible to reduce the delay and to obtain a fast operation speed.

As described above, by applying the gating voltage of the output driving circuit higher than the power supply voltage, it is possible to prevent the delay caused by this, and as a result, a fast operation speed can be obtained even under a low power supply voltage.

Claims (4)

A memory cell array having memory cells arranged in a matrix of rows and columns, said memory cell array storing information bits; Detecting means for detecting a state transition of an address signal or chip activation signal from the outside to generate a pulse signal; Row selection means for decoding the address signal to select a row of the array; Column selection means for decoding the address signal to select a column of the array; Sensing amplifying means for detecting and amplifying data stored in a memory cell selected by said selecting means and outputting complementary data of said data; First voltage boosting means for generating a boosted voltage higher than a first voltage level in response to the pulse signal, and outputting the boosted voltage when the data from the sense amplifying means is at the first voltage level; First delay means for receiving, inverting and delaying data from the sense amplifying means; Pull-up control means for receiving data from the first delay means and the boosted voltage and outputting a pull-up signal; Second voltage boosting means for generating the boosted voltage in response to the pulse signal and outputting the boosted voltage when complementary data from the sense amplifying means is at a first voltage level; Second delay means for receiving, inverting and delaying the complementary data; Pull-down control means for receiving the complementary data from the second delay means and the boosted voltage from the second voltage boosting means and outputting a pull-down signal; And output driving means for driving an output node to one of a first voltage level and a second voltage level in response to the pull up / pull down signal from the pull up / pull down control means. The method of claim 1, And the first voltage level is a power supply voltage level and the second voltage level is a ground voltage level. The method of claim 1, The voltage level of the pull-up signal is a boosted voltage level from the first voltage boosting means when the data from the first delay means is a ground voltage level, and is a ground voltage level when the data is a power supply voltage level. . The method of claim 3, wherein The voltage level of the pull-down signal is a boosted voltage level from the second voltage boosting means when the data from the second delay means is the ground voltage level and is a ground voltage level when the data is the power supply voltage level. Device.