KR19980084635A - Branch prediction method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Microprocessor.

2. Technical problem to be solved by the invention

In a microprocessor with a BTB where a dual pipeline structure and branch contents are stored and used as a basis for branch prediction, a branch prediction method for performing branch prediction and branch verification when performing a program according to branch prediction is provided.

3. Summary of the Solution of the Invention

The branch prediction method includes branch prediction method that divides the BTB query and the import of the next instruction of the branch instruction into two stages when performing the program according to the branch prediction, and the branch verification method in the WB stage for the verification of both dual pipes. To provide a way.

4. Important uses of the invention

Used in all microprocessor chip designs with branch prediction devices.

Description

Branch prediction method

The present invention relates to a branch prediction method for effective branch prediction and branch verification in a branch prediction structure in a microprocessor, and can be applied to all microprocessors having a branch prediction structure.

When a branch instruction is issued during program execution, the branch prediction that is executed after the branch is predicted and the predicted branch is verified according to the stored program execution records up to the previous time.

Conventionally, since the BTB query and the next instruction of the branch instruction are fetched in one stage during the branch prediction, there is a problem in that processing is impossible when the clock speed is high. In addition, branch verification has a problem in that the branch prediction circuit is complicated and complicated control circuits are required because the X pipe is independently examined at the EX stage and the Y pipe is at the WB stage in the dual pipe structure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in a microprocessor having a dual pipeline structure and a BTB in which branch contents are stored and used as a basis for branch prediction, a fast clock when executing a program according to branch prediction It is an object of the present invention to provide a branch prediction method capable of branch prediction at a speed and efficient branch verification.

1 is a pipelined branch prediction block diagram of the present invention.

2 is a branch prediction method of the present invention.

The present invention for achieving the above object is a dual-pipe microprocessor of the first pipe and the second pipe having a plurality of stages, the first stage to fetch the instructions to be executed in the cache, the first stage to calculate the length of the fetched instructions It consists of two stages, a third stage for decoding the instruction, a fourth stage for calculating the address of the data to be retrieved from the data cache, a fifth stage for performing the instruction, and a sixth stage for writing the result to memory or a register. According to the present invention, a branch prediction method for processing a branch target buffer (BTB) and obtaining a next instruction of a branch instruction is divided into two stages.

In addition, in a dual pipe microprocessor of a first pipe and a second pipe having a plurality of stages, a first stage that obtains instructions to be executed from the cache in advance, a second stage that calculates the length of the fetched instructions, and decodes the instructions. Dual pipe of the first and second pipes, consisting of a third stage, a fourth stage for calculating the address of data to be fetched from the data cache, a fifth stage for executing instructions, a sixth stage for writing the result to memory or a register In a microprocessor with a branch target buffer (BTB) where the line structure and branch contents are stored and used as the basis of branch prediction, whether the operation to predict and execute the next instruction according to the branch prediction is correct or incorrect. Branch prediction, in which the first pipe and the second pipe are both processed by the sixth stage It comprises a method.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

If a branch instruction is issued while the program is running, the branch instruction is stopped only after this branch is executed. In the meantime, the instruction is interrupted while Branch Prediction brings the instruction to prevent such performance degradation. In this case, it refers to an operation of predicting and executing the instruction to be executed after the branch instruction according to the previous program execution record. It has a branch unit to perform this role. This branch stage is equipped with a branch target buffer (BTB), and is closely related to prefetch and instruction fetch. At this time, when the program is executed according to the branch prediction, the instruction to be executed after the branch instruction must be predicted to confirm whether or not the operation to be performed in advance is correct or incorrect. This process is called branch verification.

The present invention provides an apparatus for performing such branch prediction and branch verification. FIG. 1 shows a block diagram of a branch prediction pipelined to an embodiment according to the present invention. 1 is a PF (Prefetch, 100) for prefetching instructions to be executed from a cache, IA (Instruction Addressing, 200) for calculating the length of a fetched instruction, ID (Instruction Decoding, 300) for decoding an instruction, and a data cache. X, Y dual with AG (Address Generation, 400) to calculate the address of the data to be imported, EX (Excution, 500) to execute the instruction, and WB (Write Back, 600) to write the result to memory or register The pipeline structure and branch contents are stored, and are used as a BTB 700 used as a basis for branch prediction, and a branch shifter for storing branch contents for reference during branch verification. The branch shifter may include a first branch shifter 10 for storing an address of an X pipe, an address of a target instruction, a BTB inquiry, and the like in the IA stage, and a second branch in which the contents of the first branch shifter are delayed and stored for one cycle. Third branch shifter 30 in which branch information from the ID stage is stored together with the contents of the shifter 20 and the second branch shifter, and fourth branch in which branch information from the AG stage is stored together with the contents of the third branch shifter. The fifth branch shifter 50 in which the branch information from the EX stage is stored along with the contents of the shifter 40 and the fourth branch shifter, and the branch information from the WB stage is stored. And a sixth branch shifter 60 to change the BTB to the contents of the sixth branch shifter (70) and to prefetch back to the correction address if the branch prediction is incorrect (80). It is composed.

The BTB inquiry necessary for branch prediction in the pipeline progress by stage is performed in the IA stage, and the import of the next instruction of the branch instruction is performed in the ID stage. As described above, when branch prediction is performed by the branch instruction itself address while dividing the BTB inquiry and the import of the next instruction, one cycle of white space occurs. 2 is a conceptual diagram illustrating a branch prediction method according to the present invention, in which a BTB query is performed to an address of an instruction performed in a previous cycle of a cycle in which a branch instruction is performed to remove the generated space, and proceeds in a dual pipe. To avoid problems associated with instruction associations, always perform a BTB query with the address of the instruction executed in the Xpipe. The BTB is retrieved from the IA stage of the previous instruction, which is the instruction executed in the entire cycle of the branch instruction, and attempts to predict the branch instruction. The next cycle thus prefetches the target with the expected target address of the branch. In FIG. 2, the next command is a command to be performed after the branch when the branch does not proceed as described in the BTB. If the prediction is incorrect after the branch verification in WB, the pipeline flushes all pipelines and returns to the state before the branch. This command should be executed after the branch after release. When the branch prediction is wrong in the drawing, the correction is performed after the wrong branch prediction is executed.

Referring to Figure 1 in detail by stage, first, in the PF stage, the instruction to be executed in advance is retrieved from the cache irrespective of the actual program progress, and the branch prediction is performed by the instruction address before the branch instruction to execute the program without additional delay according to the branch. Do it.

The IA stage writes the X pipe address into the index address field, which must indicate index invalidness if the X command is not accepted. The delay stage is not a pipeline stage, but just one cycle of information passed from the IA to compensate for the delay caused by predicting the previous instruction address of the branch instruction. In the ID stage, it checks whether an instruction of an X or Y pipe is a branch and writes it to the branch shifter. It also knows whether the instruction is valid and stores it in the branch shifter. Only the instructions that are accepted as valid by the IA at the time of branch verification and are determined to be valid branches by the ID will perform the BTB change. The AG stage calculates the address of the data to retrieve from the data cache and checks if the target address is correct. The EX stage processes the instruction and checks for branch conditions. In the WB stage, branch processing is performed and branch verification is performed for all cases by referring to the contents of the branch shifter.

This branch verification is performed at the WB stage regardless of the X and Y pipes.The branch verification is performed in the following ways: first, BTB hit / miss, second, branch instruction check, third, branch target fit, fourth, branch prediction (Taken) / not-taken) to verify the contents of the check. First, BTB hits / misses are the basis of branch verification, to see if this branch is expected. A hit has been taken and executed as a branch instruction before this branch instruction. In the second verification, the branch instruction check, if the BTB hit is made by querying the BTB for branch prediction at the IA stage, the instruction coming to the next X pipe or Y pipe must have a branch instruction. If the next branch instruction is not a BTB hit, the contents of the BTB must be invalidated. In the case of a BTB miss, the program is assumed to not branch by default, and the BTB entry is allocated only when a branch is taken during branch verification. The third verification is to replace the internal program counter with the target address value stored in the BTB at the time of the BTB hit and prefetch again, and obtain the actual target address from the AG stage of the branch instruction and compare the branch target with the predicted target address. Is to check if this is correct. If the compared target addresses are different, the contents of the target address field of the BTB should be modified. The fourth and final verification, the Taken / not-taken check, compares the predicted branch prediction with the actual to determine whether to rerun the program based on the result.

When performing branch verification at the WB stage, the next branch instruction in the same cycle is performed at the EX stage. If the verification indicates that correction of the progress is necessary, this implementation should not be performed. In particular, if the command is a command such as memory write, it cannot be recovered, so it must be executed quickly and immediately stop the next execution.

In fact, when the branch is performed on the X pipe, we know whether the hit hits or misses in the EX stage, but we also validate it in the WB stage for design consistency and simple circuit configuration.

To this end, the initial query and branch predictions from the BTB are maintained and verified until the WB stage, which is the verification point. This is done with reference to the branch shifter, which shifts branch predictions and stores them as the pipeline progresses. Refer to the branch shifter to retrieve the cache from the prefetch logic to retrieve branch target instructions and to retrieve instructions from the prefetch queue at the IA stage. In addition, if the prediction is incorrectly prefetched, the branch shifter is referred to.

Since the above branch prediction must be performed under the assumption that all instructions can be found in the cache, it is normal to make the BTB change and inquiry only by the relationship between the previous cycle and the branch cycle.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention made as described above, the branch instruction of a BTB query and a branch instruction when executing a branch program for branch prediction in a microprocessor having a dual pipeline structure and a BTB in which branch contents are stored and used as a basis for branch prediction. The import of is divided into two stages to enable branch prediction at fast clock speeds. In addition, shift registers are set by stage for branch verification, and branch contents are stored and shifted as the pipeline progresses, so that branch verification is performed at the WB stage to enable consistent design of the branch prediction structure, and simplify the control circuit. Compared to the above, it has a better performance improvement.

Claims (6)

In a dual-pipe microprocessor of a first pipe and a second pipe having a plurality of stages, a first stage that prefetches instructions to be executed from the cache, a second stage that calculates the length of the fetched instructions, and a third that decodes the instructions. The stage, the fourth stage of calculating the address of data to be obtained from the data cache, the fifth stage of executing the instruction, the sixth stage of writing the result to memory or a register, and the program according to the branch prediction. A branch prediction method for processing a branch target buffer (BTB) query and obtaining a next instruction of a branch instruction by dividing the second stage and the third stage, respectively. The method of claim 1, When executing the program according to the branch prediction, the branch target buffer (BTB) inquiry and the import of the next instruction are divided into the second stage and the third stage, and the branch prediction is performed by the own address of the branch instruction. The branch prediction method of claim 1, wherein a branch target buffer (BTB) is queried with the address of the instruction executed in the previous cycle of the cycle in which the branch instruction is executed to remove the space of one cycle. The method of claim 2, In order to eliminate the problem caused by the correlation of the instruction proceeding in the dual pipe, the branch target buffer (BTB) lookup is always performed with the address of the instruction executed in the first pipe among the instructions executed in the previous cycle of the cycle in which the branch instruction is executed. Branch prediction method characterized in that. In a dual pipe microprocessor with a branch target buffer (BTB) each having a number of stages, the branch content being stored and used as the basis for branch prediction, A first stage to get the instruction to execute from the cache in advance, a second stage to calculate the length of the fetched instruction, a third stage to decode the instruction, a fourth stage to calculate the address of the data to be retrieved from the data cache, and perform the instruction The fifth stage, and the sixth stage to write the result to memory or register, respectively, and perform branch verification to predict whether the next instruction to be executed according to branch prediction is correct or wrong. A branch prediction method in which both the first pipe and the second pipe are processed in the sixth stage. The method of claim 4, wherein In order to process branch verification in the sixth stage, the branch target buffer (BTB) and the contents of the inquiry in the branch prediction content is maintained until the sixth stage at the time of verification, characterized in that it is used for the verification Branch prediction method. The method of claim 5, A branch prediction method of shifting and storing the branch prediction content as the pipeline progresses by providing a branch shifter for each stage to keep the inquiry contents up to the sixth stage, which is a verification point, for use in the verification. .