JP2000029693A - Instruction cache device and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an instruction cache device storing the instruction block of a non-branch instruction and the instruction block of a branch destination instruction to dedicated first and second instruction caches and surely hitting the branch destination instruction in the second instruction cache and a control method therefor. SOLUTION: This instruction cache device 1 is provided with a first cache 5 for storing the instruction block taken out from an external memory, a second cache 6 for taking out the instruction block of the branch destination instruction from the external memory and storing it, an instruction decoder 10 for discriminating whether the instruction of the first cache 5 or the instruction of the second cache 6 is a branching instruction or the non-branching instruction, an address generation means 11 for generating the branch destination instruction address, and the next address of the next instruction in the case of the non- branch instruction or when the branching by the branch instruction is not established, a branch destination address register 9 for setting the branch destination instruction address of the address generation means 11 and a next address register 7 for setting the next instruction address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction cache device, and more particularly, to an instruction cache having a first cache for storing an instruction block of a subsequent instruction and a second cache for storing an instruction block of a branch destination instruction of a branch instruction. And an instruction cache device for increasing the cache hit rate of branch destination instructions, and a control method therefor.

[0002]

2. Description of the Related Art In the prior art, an instruction block including a branch instruction is stored in one instruction cache.
For this reason, the branch destination instruction of the branch instruction is lost from the instruction cache due to the overwriting of the instruction cache, and the number of miss hits of the instruction cache in fetching the branch destination instruction is increased. Therefore, when a branch destination instruction miss-hits in the instruction cache, it takes time to retrieve the branch destination instruction from the external memory, and thus there is a problem that the processing time is increased. In particular, in a system in which access to an external memory becomes a "bus neck" that determines the upper limit of the processing time, the processing time is significantly increased due to a miss hit of a branch destination instruction. To solve this problem, a conventional example of Japanese Patent Laid-Open No. 58-195
According to Japanese Patent Laid-Open No. 255-255, there is described a technique of prefetching a branch destination instruction of a branch instruction and aligning the instruction sequence. An instruction buffer register for decoding and extracting a branch instruction from the instruction sequence, monitoring a branch establishment condition of the branch instruction, and aligning and storing a branch destination instruction prefetched by a branch destination address in the instruction sequence; Instructions are sequentially fetched from registers and executed. By prefetching the branch destination instruction of the branch instruction from the instruction dedicated cache, instruction execution is speeded up.
However, in this publication, since there is only one instruction-only cache for storing an instruction sequence, there remains a problem that a branch destination instruction disappears from the instruction-only cache due to overwriting of the instruction-only cache with an instruction block.

[0003]

In the conventional instruction-only cache, the branch destination instruction is lost by overwriting the instruction from the cache, so that a cache mishit occurs and the branch destination instruction is transferred from the slow external memory via the bus. Since instructions are taken out, an increase in processing time is unavoidable.

It is an object of the present invention to convert an instruction block stored in a single instruction cache into an exclusive first instruction block and a non-branch instruction instruction block.
By storing in the instruction cache and the second instruction cache, the branch instruction is prevented from being overwritten by the instruction block of the subsequent instruction, and the branch instruction is reliably hit in the instruction cache.

[0005]

According to the present invention, there is provided an instruction cache device having an instruction cache for fetching and storing an instruction in block units from an external memory and fetching a next instruction from the external memory or the instruction cache. A first cache for storing an instruction block fetched from the external memory, a second cache for storing an instruction block of a branch destination instruction of a branch instruction fetched from the external memory, and a fetched cache from the first cache or the external memory An instruction decoder for determining whether an instruction to be taken or an instruction fetched from the second cache is a branch instruction or a non-branch instruction;
Address generation means for generating a branch destination instruction address of the branch instruction and a next instruction address of a branch not taken and a non-branch instruction of the branch instruction; a branch destination address register for setting a branch destination instruction address of the address generation means; A next address register for setting a next instruction address of the address generating means, wherein when the instruction is a branch instruction and the branch is taken, a branch destination instruction is fetched from the second cache.

Further, the first and second caches include:
An entry corresponding to the instruction block includes an instruction address for storing the instruction, an instruction code for storing the instruction at the instruction address, and a valid bit indicating whether the stored instruction is valid or invalid. It is a buffer.

Further, in an instruction cache device having a prefetch buffer and an instruction cache for prefetching and storing instructions in block units from an external memory, and extracting the next instruction from the prefetch buffer or the instruction cache or the external memory, A prefetch buffer for storing an instruction block prefetched from an external memory, a first cache for storing an instruction block stored in parallel with the instruction block storage for the prefetch buffer, or for storing an instruction block retrieved from the external memory; A second cache for storing an instruction block of a branch destination instruction of a branch instruction to be fetched;
An instruction decoder for determining whether an instruction fetched from the prefetch buffer, the first cache, the second cache, or the external memory is a branch instruction or a non-branch instruction; a branch destination instruction address of the branch instruction; Address generation means for generating a prefetch address of a branch instruction not taken and a non-branch instruction; a branch destination address register for setting a branch destination instruction address of the address generation means; and a prefetch for setting a prefetch address of the address generation means. An address register, wherein when the instruction is a branch instruction and the branch is taken, the branch destination instruction is taken out from the second cache.

Further, the prefetch buffer includes an instruction address for storing an instruction, an instruction code for storing an instruction at the instruction address, and a valid bit indicating whether the stored instruction is valid or invalid. It is characterized by comprising a plurality of entries.

Further, the instruction cache device stores the branch destination instruction stored in the first cache in the second cache.
And a transfer bus for transferring the data to the cache.

The operation of the prefetch buffer according to the present invention will be described. When an instruction is directly fetched from the first cache, if a cache miss occurs, processing after decoding is made to wait until the instruction fetch from the external memory is completed. Occurs. In order to prevent this waiting time from occurring, a prefetch buffer is provided. The prefetch buffer prefetches an instruction from the first cache (prefetch) every time an instruction is sent to the decoder and a space becomes available in the prefetch buffer.
Since the prefetch buffer is composed of a plurality of entries, even if a miss occurs in the first cache, instructions can be supplied stably without waiting for processing after decoding.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. Referring to FIG. 1 showing the configuration of the first embodiment of the present invention, an instruction cache device 1 includes a first cache 5 for storing an instruction block of a subsequent instruction and a second cache 5 for storing a branch destination instruction block. A cache 6, a next address register 7 for storing a next instruction address,
A branch destination address register 9 for storing a branch destination instruction address; an instruction fetched from an external memory (not shown) via the instruction bus 13; an instruction fetched from the first cache via the instruction bus 15; or an instruction fetched from the second cache 3 via the instruction bus 14 An instruction decoder 10 for decoding a branch target instruction to be fetched; a non-branch instruction and a next instruction address when a branch instruction is not taken, generated by adding an instruction length to the instruction address; An address generation means 11 for generating an address, an instruction bus 13 for extracting an instruction block to an external memory (not shown), a next address bus 17 for sending the next instruction address to the external memory, and a branch destination instruction address to the external memory. And a branch destination address bus 18 for sending.

Referring to FIG. 2 showing an entry configuration of the first and second caches 5 and 6, an entry 80 of the cache includes an instruction address 81, an instruction code 82, and a valid bit 83 indicating whether the instruction is valid or invalid. And a buffer including an entry for storing each instruction of the instruction block fetched from the external memory.

The operation of the first embodiment will be described with reference to FIGS. 1 and 2 and a flowchart of FIG.
The instruction decoder 10 determines the type of the instruction (Step 22),
If the instruction is a branch instruction (Y in step 23), it is determined whether the branch is taken or not taken (step 24). In parallel with the determination, the address generating means 11 generates a branch destination instruction address when the branch instruction is taken and a next address when the branch instruction is not taken and after the non-branch instruction (steps 231 and 233). ), The branch destination instruction address is set in the branch destination address register 9 and the next address is set in the next address register 7 (steps 232 and 2).
34). When the branch instruction is taken (Y in step 24), the first cache 5 and the second cache 6 are searched with the branch destination address (step 25), and when the branch destination instruction hits the second cache 6, (Y in step 26), the branch destination instruction is fetched from the second cache 6 using the instruction bus 14 (step 28) and passed to the instruction decoder 10.

When the second cache 6 miss-hits (N in step 26) and the first cache 5 misses (N in step 27), the external address is transferred from the branch destination address register 9 through the branch destination address bus 18. The branch destination instruction address is output to the memory, the branch destination instruction is fetched from the external memory, the corresponding instruction block is stored in the second cache 6 (step 291), and passed to the instruction decoder 10 using the instruction bus 13. (Step 29). When the second cache 6 misses (N in step 26) and the first cache 5 hits (Y in step 27), the branch destination instruction is fetched from the first cache 5 and the instruction bus 15 is used. The instruction block is passed to the instruction decoder 10 (step 30), and the instruction block of the branch destination instruction is fetched from the external memory in parallel and stored in the second cache 6 (step 31). Instruction decoder 10
If the instruction is not a branch instruction (N in step 23), and if the instruction is a branch instruction (Y in step 23) and the branch is not taken (N in step 24), the process proceeds to the next instruction fetch, and the first cache 5 is stored. The next instruction is searched by the next instruction address of the next address register 7 (step 33). When the next instruction is hit (Y in step 34), the instruction is fetched from the first cache 5, and the instruction decoder 10 is used by using the instruction bus 15. (Step 35). When the next instruction misses (step 34)
N), the next instruction is fetched from the external memory through the next address bus 17 and stored in the first cache 5 (step 36), and at the same time, the instruction is passed to the instruction decoder using the instruction bus 13.

Next, a second embodiment of the present invention will be described. Referring to FIG. 4 showing the configuration of the second embodiment, the instruction cache device 2 includes a prefetch buffer 8 and instruction buses 12, 1 in the instruction cache device 1 of FIG.
9 and 20 are added, and the next address register 7
A prefetch address register 4 and a prefetch address bus 50 are added instead of the next address bus 17. When the first cache 5 misses, the instruction block fetched from the external memory (not shown)
Is stored in the prefetch buffer 8 via the instruction bus 12 in parallel with the instruction stored in the cache 5, and when the first cache 5 hits, the instruction fetched from the first cache 5 uses the instruction bus 19, It is stored in the prefetch buffer 8. The prefetch buffer 8
This is a register file for prefetching and storing instructions.

The operation of the instruction cache device 2 according to the second embodiment will be described with reference to the flowchart in FIG.
FIG. 4 will be described with reference to FIG. 6 and a flowchart showing the operation of storing an instruction in the prefetch buffer 8. The next instruction is fetched from the prefetch buffer 8 (step 51), output to the instruction decoder 10 using the instruction bus 20, and decoded whether the instruction is a branch instruction or a non-branch instruction (step 52). Is determined (step 53). In parallel with the determination, a branch destination instruction address of the branch instruction is generated (step 531), and a prefetch address for the branch not taken and the non-branch instruction of the branch instruction is generated (step 531).
3) Set the branch destination address register 9 and the prefetch address register 4 respectively (steps 532 and 53)
4). When the instruction is a branch instruction (Y in step 53) and the branch is taken (Y in step 54), the first and second caches 5 and 6 are searched with the branch destination instruction address, and the prefetch buffer 8 Is invalidated (step 55).
When the second cache 6 is hit in the search (step 5
6), using the instruction bus 14 to transfer the branch destination instruction to the second
From the cache 6 and passed to the instruction decoder 10 (step 58). In the search, when the second cache 6 has a mishit (N in step 56) and when the first cache 5 has a mishit (N in step 57), the branch destination is determined using the instruction bus 13 from the external memory. The instruction is fetched and passed to the instruction decoder, and the instruction block of the instruction is stored in the second cache 6.
(Step 591). In the search, when the second cache 6 misses (N in step 56) and the first cache 5 hits (Y in step 57), the first cache 5 uses the instruction bus 15 Then, the branch destination instruction is fetched and sent to the instruction decoder 10 (step 60), and the branch destination instruction is fetched from the external memory in parallel (step 60).
1) and store it in the second cache 6 (step 602).
When the instruction decoder 10 determines that the instruction is a non-branch instruction (N in step 53) or when the branch instruction is not taken (N in step 54), the next instruction is fetched from the prefetch buffer 8 (step 51). . When the next instruction is fetched from the prefetch buffer 8, as shown in FIG. 6, the prefetch buffer 8 always determines whether or not there is a free entry, and when there is a free entry (Y in step 62),
The first cache 5 is searched based on the address of the prefetch register 4 (step 63), and when a hit occurs (Y in step 64), the prefetch destination instruction is fetched from the first cache 5 (step 66), and the instruction bus 19 and store it in the prefetch buffer 8 (step 68).
When the first cache 5 misses in the search (N in step 64), the instruction block of the prefetch instruction is fetched from the external memory via the prefetch address bus 50 (step 65), and the instruction block is stored in the first cache 5 And stored in the prefetch buffer 8 (step 67).

Next, a third embodiment will be described with reference to FIG. The instruction cache device 3 is a modification of the second embodiment of FIG. 4 in which a transfer bus 21 for transferring the next instruction from the first cache 5 to the second cache 6 is added.
Referring to FIG. 5, when the instruction of the instruction decoder 10 is a branch instruction and the branch is taken (Y in step 54), the search of the first and second caches 5 and 6 (step 55) causes the second cache 6 misses (N in step 56) and when the first cache 5 hits (Y in step 57), the first cache 5
Transfer bus 21 from the first cache 5 to the second cache 6
By transferring the branch destination instruction through (step 603) and storing it in the second cache 6 (step 604), the number of instructions fetched from the external memory can be reduced.

[0018]

According to the above description, according to the present invention, when an instruction fetched from an external memory is executed and the instruction is a branch instruction, the instruction block of the branch destination instruction is stored and held in the second cache. Accordingly, it is possible to prevent the branch destination instruction from disappearing from the cache by replacing the instruction block generated in the cache by the instruction execution, and to improve the cache hit rate of the branch destination instruction.

Further, when a branch instruction is taken by instruction execution, a branch destination instruction can be fetched from the second cache. Therefore, fetching of instructions from the external memory is reduced, and the load on the bus is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram exemplifying entries in first and second caches in FIG. 1;

FIG. 3 is a flowchart illustrating a flow of an operation according to the first exemplary embodiment;

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a flowchart after fetching an instruction from a prefetch buffer according to the second embodiment;

FIG. 6 is a flowchart illustrating an operation of storing an instruction in a first cache and a prefetch buffer according to a second embodiment;

FIG. 7 is a diagram showing an embodiment of a third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 instruction cache device 2 instruction cache device 3 instruction cache device 4 prefetch address register 5 first cache 6 second cache 7 next address register 8 prefetch buffer 9 branch destination address register 10 instruction decoder 11 address generation means 12 to 15 instruction bus 17 Next address bus 18 Branch destination address bus 19 Instruction bus 20 Instruction bus 21 Transfer bus 50 Prefetch address bus 80 Cache entry 81 Instruction address 82 Instruction code 83 Valid bit

Claims (7)

[Claims] 1. An instruction cache device for fetching and storing instructions in block units from an external memory and fetching the next instruction from the external memory or the instruction cache, wherein the instruction block fetched from the external memory is stored. A first cache that stores an instruction block of a branch destination instruction of a branch instruction that is fetched from the external memory; and an instruction that is fetched from the first cache or the external memory or the second cache. An instruction decoder for determining whether the fetched instruction is a branch instruction or a non-branch instruction; and generating a branch destination instruction address of the branch instruction, a branch not taken of the branch instruction, and a next instruction address of the non-branch instruction. Address generating means to be executed, and a branch destination of the address generating means A destination address register for setting an instruction address; and a next address register for setting a next instruction address of the address generation means. When the instruction is a branch instruction and the branch is taken, the branch destination instruction is stored in the second cache. An instruction cache device characterized by taking out an instruction. 2. The first and second caches include: an instruction address for storing an instruction, an instruction code for storing an instruction at the instruction address, and a validity indicating whether the stored instruction is valid or invalid. The instruction cache device according to claim 1, wherein the instruction cache device is a buffer having an entry including a bit and an entry corresponding to the instruction block. 3. A control method for an instruction cache device, comprising: an instruction cache for fetching and storing an instruction in block units from an external memory; and fetching a next instruction from the external memory or the instruction cache. Determining whether the instruction is a non-branch instruction or a branch instruction; generating a next instruction address when the instruction is a non-branch instruction or a branch not taken by a branch instruction; setting the next instruction address in a next address register; Generating a branch destination instruction address in the case of branching of the instruction and setting it in the branch destination address register in parallel with the determination; and when the determination indicates that the instruction is a non-branch instruction, When the next instruction is hit in the search of the first cache, the next instruction is fetched from the first cache, and Fetching a next instruction from the external memory based on a next instruction address of the next address register when a mishit occurs, and storing an instruction block of the instruction in a first cache; Fetching the next instruction from the first cache or the external memory on the basis of the next instruction address of the next address register when the branch of the branch instruction is not taken; A step of searching the first and second caches based on a branch destination instruction address of the branch destination address register; and when the second cache hits a branch destination instruction in the search, the branch The instruction at the destination instruction address is fetched from the second cache, and the second cache misses the branch destination instruction. In preparative and when the first cache hit branch target instruction, the instruction of the branch target instruction address first
From the external memory based on the address of the branch destination instruction, and stores the instruction block of the branch destination instruction in the second cache. Fetching a branch target instruction from an external memory based on the branch target instruction address when mishits the branch target instruction, and storing an instruction block of the branch target instruction in a second cache. And a control method for the instruction cache device. 4. An instruction cache device having a prefetch buffer and an instruction cache for prefetching and storing instructions in block units from an external memory, and extracting the next instruction from the prefetch buffer or the instruction cache or the external memory. A prefetch buffer for storing an instruction block prefetched from the external memory; a first cache for storing an instruction block stored in parallel with the storage of the instruction block in the prefetch buffer, or storing an instruction block retrieved from the external memory; A second cache storing an instruction block of a branch destination instruction of a branch instruction fetched from the memory; and an instruction fetched from the prefetch buffer, the first cache, the second cache, or the external memory is a branch instruction. Or an instruction decoder for determining whether the instruction is a non-branch instruction; an address generating means for generating a branch destination instruction address of the branch instruction and a prefetch address of a branch not taken and a non-branch instruction of the branch instruction; A branch destination address register for setting a branch destination instruction address; and a prefetch address register for setting a prefetch address of the address generation means. When the instruction is a branch instruction and the branch is taken, the branch destination is read from the second cache. An instruction cache device for fetching instructions. 5. The prefetch buffer includes: an instruction address for storing an instruction; an instruction code for storing an instruction at the instruction address; and a valid bit indicating whether the stored instruction is valid or invalid. 5. The prefetch buffer according to claim 4, comprising a plurality of entries. 6. A control method for an instruction cache device, comprising: a prefetch buffer and an instruction cache for prefetching and storing instructions in block units from an external memory, and fetching a next instruction from the prefetch buffer or the instruction cache or the external memory. A step of fetching the next instruction from the prefetch buffer and determining whether the instruction is a non-branch instruction or a branch instruction; and Generating a prefetch address and setting the same in a prefetch address register, generating a branch target instruction address in the case where the branch instruction is taken and setting the same in a branch destination address register; and Fetches the next instruction from the prefetch buffer Transferring a command block of the prefetched instruction from the first cache to a prefetch buffer when a prefetch instruction hits in a search of the first cache by the prefetch address; Extracting an instruction block of a prefetch instruction based on a prefetch address from an external memory based on the prefetch address and storing the instruction block in the prefetch buffer and the first cache; and if the instruction is a branch instruction and the branch is not taken in the determination, the next instruction From the prefetch buffer; and, if the instruction is a branch instruction and the branch is taken in the determination, searching the first and second caches at the branch destination address, and invalidating the instruction in the prefetch buffer. And the second cache is obtained by the search. When a branch instruction is hit, the branch instruction is fetched from the second cache, the second cache mishits the branch instruction, and
When the cache hits the branch target instruction, the instruction block of the branch target instruction is fetched from the external memory, stored in the second cache, and the branch target instruction of the first cache is fetched. Fetching a branch target instruction from external memory when the instruction is a miss hit and the second cache mishits the branch target instruction, and storing an instruction block of the branch target instruction in the second cache. A method for controlling an instruction cache device, comprising: 7. The instruction cache device according to claim 4, wherein said instruction cache device has a transfer bus for transferring a branch target instruction stored in said first cache to said second cache. .