JPH0588891A - Cache memory controller - Google Patents

Abstract

PURPOSE:To improve the hit rate of a cache memory by exactly executing prefetching even when branching is generated. CONSTITUTION:This device is equipped with a cache memory 2 and a branch prediction circuit 3 to predict the address of a branch destination from the storage address of a branching instruction and in the case of executing feel processing because of cache error, the address of the cache error is registered on the branch prediction circuit 3. When there is no address of the predicted branch destination in the cache memory 2, a block containing the predicted branch destination address is prefetched immediately after a refeel processing and when there is the predicted branch destination address in the cache memory 2, a bus 113 is released immediately after the refeel processing. When the address of the cache error is not registered on the branch prediction circuit 3 and a block next to the block containing the address of the cache error does not exist in the cache memory 2, the next block is prefetched immediately after the refeel processing and when the block next to the block containing the address of the cache error is existent in the cache memory 2, the bus 113 is released immediately after the refeel processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory controller for controlling prefetch of cache memory.

[0002]

2. Description of the Related Art In recent years, in response to increasing processor speed,
To reduce the operating speed gap between the high-speed processor and the main memory, which has a relatively low access speed,
It is becoming commonplace to have faster cache memory between the processor and main memory. However, in the series of cache memory operations, the refill process of fetching the contents of the main memory device to the cache memory and the write-back process of writing the contents of the cache memory back to the main memory device take a very long time. , Overhead is large. Therefore, it is important to improve the cache memory hit rate and prevent refill processing and write back processing as much as possible in order to operate the processor efficiently.

Prefetching the instruction cache memory and the data cache memory is one technique for improving the hit rate. What is cache memory prefetch?
This is a method of predicting the block to be fetched next and fetching it in advance to reduce cache misses and reduce the overhead due to refill processing and writeback processing.

The conventional prefetch algorithm utilizes the locality of data and instruction sequences. The simplest algorithm is to unconditionally fetch the block next to the block currently being refilled.
With this method, prefetch is performed unconditionally, so
There are problems that (1) it is easy to perform unnecessary prefetch, (2) carelessly evicts a necessary block, and (3) occupies an external bus more than necessary.
In particular, the flow of an instruction sequence often changes greatly depending on a branch, and the method of simply fetching the next block is insufficient in prediction.

In particular, the following method has been proposed for the instruction cache memory. That is,
(1) When there is a cache miss and, as a result, the processor executes a refill from a certain address,
This is a method of immediately fetching the next block, or (2) immediately fetching the next block whenever an instruction in the cache memory is to be executed as a result of branching. However, this method has a drawback that the branch cannot be predicted in advance and prefetched into the cache memory.

On the other hand, with the improvement of the microfabrication technology, it has become general to mount a branch prediction circuit that could not be mounted in the past in the MPU. The branch prediction circuit is a circuit that predicts the branch destination address based on the address of the branch instruction based on the past branch history before executing the branch instruction. Normal,
Branch instructions are executed by obtaining the branch destination address in the execution stage and updating the program counter.
Causes disruption of the instruction pipeline. If the branch prediction circuit is used, it will branch to the predicted branch destination address before obtaining the actual branch destination address, so if the predicted branch destination address is correct, execution will not be disturbed in the instruction pipeline. You can continue.

However, even if the branch prediction circuit is used to complete the branch without disturbing the instruction pipeline, if the branch destination address causes a cache miss, the instruction pipeline stops, The effect of the branch prediction circuit is halved. Therefore, in order to reduce cache misses in the instruction cache memory, there has been a demand for a cache memory control device that pre-fetches a branch destination instruction by performing accurate branch prediction in advance for the branch instruction. It was

[0008]

As described above, according to the prefetch method in the conventional cache memory,
Since it is not possible to accurately predict the branch destination and perform prefetching, problems such as easy unnecessary prefetching, careless removal of necessary blocks, and unnecessarily occupying an external bus are encountered. there were.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and at the time of prefetching to the instruction cache memory, by referring to the branch prediction circuit to predict the branch destination, An object of the present invention is to provide a cache memory control device that performs prefetching more accurately and does not perform unnecessary prefetching even when a branch occurs.

[0010]

To achieve the above object, the present invention holds a cache memory for storing instructions and data, an address where a branch instruction is stored and a past branch history, and stores the branch instruction. A branch prediction circuit that predicts the next branch destination address according to the stored address, and the branch prediction in parallel with the refill processing when the refill processing is performed due to a cache miss in the address of the instruction to be executed next. The circuit is referred to based on the address in which the cache miss has occurred, and if the address in which the cache miss has occurred is registered in the branch prediction circuit, and the branch destination address predicted by this branch prediction circuit is in the cache memory. If it does not exist, the branch prediction address predicted by this branch prediction circuit is immediately released without releasing the bus after the refill processing is completed. Prefetch of a block, and if the address causing the cache miss is registered in the branch prediction circuit and the branch destination address predicted by the branch prediction circuit exists in the cache memory, the refill Immediately after the processing is completed, the bus is released immediately. If the address causing the cache miss is not registered in the branch prediction circuit, and the block next to the block including the address causing the cache miss exists in the cache memory. If you don't, after finishing the refill process,
The next block is immediately prefetched without releasing the bus, and if the address causing the cache miss is not registered in the branch prediction circuit, and the block next to the block including the address causing the cache miss is When present in the cache memory, the cache control unit releases the bus immediately after the refill processing is completed.

[0011]

With the above structure, according to the present invention, first, when a cache miss occurs in the cache memory, the refill is started from the main memory immediately. At this time, it is also transferred to the instruction queue. When the refill finishes, execution of the operation is immediately started according to the contents of the instruction queue, but the external bus is not released. On the other hand, when the refill is started, the address where the cache miss occurs is sent to the branch prediction circuit to perform branch prediction. If there is a hit, it is predicted that the next branch will also occur at the predicted address.

After the refill processing is completed, it is checked whether or not the block including the predicted address has already been fetched in the cache memory. If it has not been fetched, the external bus is not released and the branch destination address is immediately included. Prefetch blocks from main memory. During prefetch, the instructions in the instruction queue are being executed, so
Execution rarely stops during prefetch. In the branch prediction circuit, a plurality of branch destination addresses may be hit, but in this case, the branch destination address corresponding to the branch instruction stored in the smallest address is selected. If the block including the predicted branch destination address is already fetched in the cache memory, the external bus is released immediately and the prefetch is not performed.

If the branch prediction circuit does not hit, it is considered that the block currently being refilled does not include a branch instruction and therefore no branch occurs. Therefore, if the block next to the block currently being refilled has not been fetched into the cache memory, the next block is immediately prefetched without releasing the external bus. However, if the next block currently being refilled has already been fetched into the cache memory, the external bus is released immediately and prefetch is not performed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, as shown in FIG. 5, the processor performs (1) instruction fetch (F), (2) decode / operand fetch (D), (3) execution (E), (4) memory access. It is assumed that the instructions are executed in the five-stage instruction pipeline of (M) and (5) register write (W). Further, this processor basically executes one stage in one clock. However, floating-point arithmetic requires 3 clocks in the execution stage. Further, this processor is provided with an operand bypass in the instruction pipeline, and when the operation result of the current operation is used as an operand in the next operation, immediately after the execution stage of the current operation is finished, Operations can be performed. The bit width of the address bus is fixed at 32 bits and the word length of the instruction is fixed at 32 bits.

FIG. 1 is a block diagram showing the configuration of an embodiment relating to the cache memory control device of the present invention. This cache memory control device adopting the Harvard architecture includes an instruction cache memory 2, a cache control unit 6, a branch prediction circuit 3, an instruction queue 4, and a main storage device 1.
4 and the external bus 113.

In the figure, the program counter 1
Indicates the address of the main storage device 14 in which the instruction to be fetched next is stored.

The instruction cache memory 2 is constructed by the direct method, is an instruction cache memory based on the Harvard architecture, and has 128 entries, 1 block 128 bits, and a capacity of 16 Kbits. Lower 4 of main memory address 111 given by program counter 1
Bit represents the address 103 in the block, and upper 28 bits represent the block address. The lower 7 bits of the block address are the index 101 and the upper 21 bits are the tag 100. A 21-bit tag is stored in the tag memory 7.

The instruction cache memory 2 operates as follows. First, the index 101 is given to the tag memory 7, and the content of the address indicated by the index 101 is read as the tag 105. In parallel with this, the data memory 9 is accessed using the lower 11 bits of the main memory address 111 as an address. Tag 10 read
5 and tag 100 are compared in hit / miss detector 8.

By this comparison, the tag 105 and the tag 100
, The block containing main memory address 111 exists in data memory 9 and a copy of the contents of main memory address 111 from the accessed block is latched by latch 1
It is read to 0. On the contrary, if the read tag 105 and tag 100 do not match, the block including the main memory address 111 does not exist in the data memory 9, so the block including the main memory address 111 is read from the main memory device 14. , The block in the instruction cache memory 2 determined by the index 101 is replaced with the read block. At the same time, the content of the tag in the tag memory 7 is updated to the tag 100.

The branch prediction circuit 3 is a fully associative branch prediction circuit, and comprises an address memory 11 for storing the address of a branch instruction and a target memory 12 for storing the branch destination address. The bit width of the address memory 11 is 30 bits and the number of entries is 128. The address memory 11 is divided into four banks,
The main memory device 14 in which the branch instruction is stored in the specific bank indicated by the value of the lower 2 bits of the main memory address 111.
The address of is stored. However, the lower two are stored.
It is the top 30 bits excluding bits. The target memory 12 has a bit width of 32 bits and the number of entries is 128. The target memory 12 is the address memory 1
There is a one-to-one correspondence with one, and the corresponding address memory 1
The branch destination address of the past one time when the branch instruction of the address stored in 1 branched is stored.

Such a branch prediction circuit 3 normally operates as follows. First, branch destination prediction is performed as follows. When the main memory address 111 is given to the branch prediction circuit 3 at the instruction fetch stage, the lower 2 bits are decoded and a specific bank of the address memory 11 is accessed. The upper 30 bits are given to the address memory 11, and if there is a matching address in the designated bank, the address stored in the target memory 12 corresponding thereto is output as the predicted branch destination address 109. The processor changes the value of the program counter 1 to the predicted branch destination address 109 on the assumption that the address will branch to this address.

The history registration is performed as follows.
When the branch instruction is executed, the lower 2 bits of the address of the branch instruction
The upper 30 bits of the address of the executed branch instruction are stored in the specific bank of the address memory 11 indicated by. Further, the target memory 12 stores the branch destination address calculated by the execution unit inside the processor. The instruction queue 4 stores a block including an instruction currently being executed, and issues an instruction to the execution unit according to the value of the program counter 1.

The incrementer 5 is an incrementer having a bit width of 30 bits for calculating the start address of the block next to the block currently being refilled. cache·
The upper 30 bits of the address m in which a mistake has occurred are sent to the incrementer and incremented in parallel with the refill processing, and the head address m + 4 of the next block is calculated. The address m + 4 is transferred to the instruction cache memory 2 as the leading address of prefetch. Cache control unit 6
Is a logic circuit for controlling refill processing, prefetch processing, etc. of the instruction cache memory 2.

Next, the operation of the present invention will be described. The present invention operates only when the instruction cache memory 2 makes a cache miss. 2A to 3C are time charts showing the operation when the processor to which the cache memory control device of the present invention is applied executes the following instruction sequence. 4 (a) to 4 (c)
FIG. 6 is a time chart showing an operation when a processor to which the present invention is not applied executes a similar instruction sequence.

[0025] ADD, SUB, MUL
Is an integer addition / subtraction and multiplication instruction. JMPCZ
Branches if the result of the previous operation by the conditional branch instruction is "0". JMPCZ is a squash branch, and if the branch occurs, the m + 4 instruction is not executed. R
0, R1, R2, R3 and R4 represent registers. Also,
m-1, ..., M + 4, n, n + 1 represent addresses of the main storage device 14. m, m + 4, and n are placed at the boundaries of blocks.

[0026] Currently, the processor is sequentially executing the above instruction sequence. It is assumed that the processor makes a cache miss when it tries to fetch an instruction from the address m. The processor immediately refills the instruction cache memory 2 through the external bus 113. Refill is (1) acquisition of bus right of external bus 113,
(2) It is performed by continuous access to the main storage device 14. Although the time required for the process (1) depends on the state of the external bus 113, one clock is required in FIGS. 2 to 4.

The external bus 113 is 32 bits, and if it is possible to transfer 32 bits of data from the main storage device 14 in 2 clocks, it takes 8 clocks to transfer 1 block. Therefore, 9 clocks are required for the refill processing. The instruction cache memory 2 invalidates an arbitrary block in the data memory 8 and sets m,
The instructions at addresses m + 1, m + 2 and m + 3 are refilled. Also, at the same time as the refill, m,
Instructions at addresses m + 1, m + 2, m + 3 are transferred. When the refill ends, the processor immediately
Execution starts depending on the contents of. However, the processor does not release the external bus 113 even after the refill ends.

On the other hand, the processor starts the refill processing and sends the address m where the cache miss has occurred to the branch prediction circuit 3. The branch prediction circuit 3 performs branch prediction based on the upper 30 bits of the address m (BTB access). If there is a matching address in the address memory 11, the predicted branch destination address 109 is output from the corresponding target memory 12. Since the prediction is performed in the upper 30 bits of the address m, one entry may match for each bank, and up to four entries may match. When a plurality of entries match as described above, the output of the target memory 12 having the smallest bank number is given priority.

2A and 2B show the operation when there is a matching address in the address memory 11. The predicted branch address 109 is sent to the instruction cache memory 2, and after the refill is completed, it is tested whether or not it has already been transferred to the instruction cache memory 2.

FIG. 2A is a diagram showing the operation when the predicted branch destination address 109 causes a cache miss.
The instruction cache memory 2 immediately returns the predicted branch address 10
Prefetch a block including 9. External bus 11
Since the bus right of 3 is still acquired, prefetching requires only 8 clocks. FIG. 4A shows the operation in the case of the processor to which the present invention is not applied. Figure 2
As is clear from (a) and FIG. 4 (a), when the present invention is applied, it is possible to operate 4 clocks faster than when the present invention is not applied. Actually, if the external bus 113 is released, it takes a considerable time to acquire the bus right again, so that the effect of the present invention is further enhanced.

In FIG. 2B, the predicted branch destination address 109 is
This is a case where the instruction cache memory 2 is hit. There is no need to prefetch because it has already been fetched into the instruction cache memory 2. The cache control unit 6 immediately releases the external bus 113.

FIGS. 2 (c) and 3 (a) show the case where there is no address in the address memory 11 that matches the upper 30 bits of the address m. In this case, there are no branch instructions in the block currently being refilled, and therefore
It is considered that the instruction at the address m + 4 is executed after the instruction at the address m + 3 is completed. In this case as well, the processor immediately starts execution according to the contents of the instruction queue 4 after the refill ends, but does not release the external bus 113. on the other hand,
The incrementer 5 calculates the address m + 4 from the cache miss address m in parallel with the refill processing. Address m +
4 is sent to the instruction cache memory 2 to test whether it has already been transferred into the instruction cache memory 2.

FIG. 2C shows the operation when the address m + 4 causes a cache miss in the instruction cache memory 2. The instruction cache memory 2 has an address m +
Perform prefetch from 4. Since the external bus 113 remains acquired, prefetching requires only 8 clocks.

FIG. 3A shows the operation when the address m + 4 is hit in the instruction cache memory 2. In this case, there is no need for prefetching, so the external bus 113 is released immediately.

Further, FIG. 3B shows the same operation as in FIG. 2A, but shows the operation when the following instruction sequence is executed. In the instruction sequence below, FADD, FSUB, and FMUL are floating-point number addition / subtraction and multiplication instructions and require 3 clocks in the execution stage. In the following instruction sequence, the register has a write-to-read conflict, and the instruction at addresses m + 1, m + 2, and m + 3 cannot start the operation until the execution stage of the previous instruction ends.

[0036] In this case, as is clear from FIG. 3B, at the time when the branch instruction is executed, the branch destination instruction has already been fetched into the instruction cache memory 2, so if the branch prediction is correct, Execution continues without disturbing the instruction pipeline.

FIG. 4C shows the case of a processor to which the present invention is not applied. In this case, a cache miss occurs again where the branch destination instruction is fetched. As is clear from FIGS. 3B and 4C, when the present invention is applied, it is possible to operate 10 clocks faster. Actually, if the external bus 113 is released, it takes a considerable time to acquire the bus right again, so that the effect of the present invention is further enhanced.

FIG. 3C shows the operation when the branch prediction fails. Branch prediction failures are revealed at the clock of the execute stage. In this case, the cache control unit 6 immediately suspends prefetch. The block of the instruction cache memory 2 that has been prefetched becomes invalid by setting the invalid flag.

In this embodiment, for the sake of simplicity, the instruction cache memory 2 has a direct system and the branch prediction circuit 3 has a completely associative system. However, no matter how the instruction cache memory 2 and the branch prediction circuit 3 are configured, the effect of the present invention is not affected. Further, not only the Harvard architecture but also the architecture in which the instruction and the data are mixed in the cache memory, if the operation shown in this embodiment is performed only in the case of the instruction fetch, it is exactly the same. It is possible to obtain various effects.

[0040]

As described above, according to the cache memory control device of the present invention, the branch is predicted by referring to the branch prediction circuit.
It is possible to perform prefetch to the memory, and it is possible to improve the hit rate of the cache memory, reduce the disorder of the instruction pipeline, and reduce unnecessary refills. As a result, the processing speed of the processor can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment relating to a cache memory control device of the present invention.

FIG. 2 is a time chart showing the operation of the cache memory control device of the present invention.

FIG. 3 is a time chart showing the operation of the cache memory control device of the present invention.

FIG. 4 is a time chart showing the operation of a conventional cache memory control device.

FIG. 5 is an operation diagram for explaining a pipeline operation of a processor using the cache memory control device of the present invention.

[Explanation of symbols]

 1 program counter 2 instruction cache memory 3 branch prediction circuit 4 instruction queue 5 incrementer 6 cache control unit 7 tag memory 8 hit / miss detector 9 data memory 10 latch 11 address memory 12 target memory 13 decoder 14 Main storage device 100 Tag 101 Index 102 In-block address 103 In-block address (lower 2 bits) 104 Main storage address (upper 30 bits) 105 Tag 106 Storage data 107 Fetch data 108 Instruction 109 Predictive branch address 110 Bank selection signal 111 Main storage address 112 First address of next fetch block

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[Procedure amendment]

[Submission date] October 4, 1991

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (1)

[Claims] 1. A branch for holding a cache memory for storing instructions and data, an address for storing a branch instruction and a past branch history, and predicting a next branch destination address according to the address for storing the branch instruction. When performing a refill process due to the prediction circuit and the address of the instruction to be executed next caused a cache miss, the branch prediction circuit is referenced in parallel with the refill process based on the address at which the cache miss occurred. If the address causing the cache miss is registered in the branch prediction circuit and the branch destination address predicted by the branch prediction circuit does not exist in the cache memory, the bus is released after the refill processing is completed. A cache control unit that immediately prefetches a block including the branch prediction address predicted by this branch prediction circuit without A cache memory control device comprising: