KR19980083989A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, comprising a semiconductor substrate and a buried insulating layer formed on the semiconductor substrate, a first conductive single crystal silicon layer formed on the buried insulating layer and spaced apart from the buried insulating layer, and the single crystal silicon layer. A first field oxide film formed in contact with the buried insulating layer in a first field region defining an active region consisting of a transistor region and a contact region, and a second region defining the transistor region and the contact region in the insulating crystal silicon layer; A second field oxide film formed in a field region so as not to contact the buried insulating layer, a gate formed by interposing a gate oxide film on a transistor region of the single crystal silicon layer, and a transistor region of the single crystal silicon layer having a second conductivity type. The impurity region formed by doping with a high concentration of impurities and the contact region of the single crystal silicon layer have a first conductivity type. And a substrate contact region formed by doping impurities at a high concentration. Accordingly, different substrate voltages are applied to the active regions, thereby optimizing the device and the circuit. In addition, since the active regions are completely electrically separated from the CMOS structure, the latch-up phenomenon can be prevented from occurring.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which electrically separate adjacent elements using a buried insulating layer.

As semiconductor devices become more integrated, the separation distance between adjacent devices becomes smaller. As the separation distance between adjacent elements becomes smaller, unwanted electrical coupling occurs. Such undesired electrical coupling includes, for example, a latch up phenomenon that occurs because parasitic bipolar transistors are formed between the NMOS and the PMOS in a complementary metal oxide semiconductor (CMOS).

To solve this problem, a semiconductor device having a silicon on insulator (SOI) structure in which an insulating layer is formed on a semiconductor substrate and a single crystal silicon layer used as a depletion layer is formed on the insulating layer is developed. It became. A semiconductor device having an SOI structure is formed using a SIMOX (Seperation by Implanted Oxygen) substrate or a Bonded and Etchback SOI (BESOI) substrate. In the above, the SIMOX substrate is made by implanting oxygen (O ₂ ) or nitrogen (N) into the semiconductor substrate to form a buried insulating layer. In addition, the BESOI substrate is made by melting and attaching two semiconductor substrates having an insulating layer such as an SIO ₂ layer or a Si ₃ N ₄ layer and etching one semiconductor substrate to a predetermined thickness.

In the above, the semiconductor device having the SOI structure prevents PN junctions by insulating the semiconductor substrate and the single crystal silicon layer by the insulating layer, thereby preventing unwanted electrical coupling such as the formation of parasitic bipolar transistors.

However, in a semiconductor device having an SOI structure, when no body contact is made, carriers generated in a channel or a substrate are accumulated due to a high electric field in the vicinity of the drain region. Therefore, a floating body effect is generated to change the operating characteristics of the device.

Accordingly, a semiconductor device having an SOI structure that can prevent body floating by making body contact has been developed.

1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.

Referring to FIG. 1A, a buried insulating layer 13 is formed on a semiconductor substrate 11, and a P-type single crystal silicon layer 15 having a thickness of about 500 to 2000 GPa is formed on the buried insulating layer 13. Is formed. In the above, the buried insulating layer 13 and the single crystal silicon layer 15 are formed on the semiconductor substrate 11 by the SIMOX method or the BE method. When the buried insulating layer 13 and the single crystal silicon layer 15 are formed by the SIMOX method, the same P type semiconductor substrate 11 as the single crystal silicon layer 15 is used, and when formed by the BE method, the P type or the N type is formed. Semiconductor substrate 11 is used.

A pad oxide film 17 is formed on the single crystal silicon layer 15 by a thermal oxidation method, and silicon nitride is deposited on the pad oxide film 17 by chemical vapor deposition (hereinafter, referred to as CVD). The mask layer 18 is formed. The mask layer 18 and the pad oxide film 17 are patterned by a photolithography method so that the single crystal silicon layer 15 is exposed, thereby forming an active region including a transistor region T1 and a contact region BC1. And a field area consisting of first and second field areas F1 and F1. Using the mask layer 18 as an etch mask, the exposed portions of the single crystal silicon layer 15 are anisotropically etched by a method such as reactive ion etching (hereinafter referred to as RIE) to form the grooves 19. . At this time, the groove 19 is formed so that the buried insulating layer 13 is not exposed.

Referring to FIG. 1B, the surface of the single crystal silicon layer 15 is exposed by removing the mask layer 18 and the pad oxide film 17. Then, silicon oxide is deposited by the CVD method so as to fill the grooves 19 on the single crystal silicon layer 15. The silicon oxide is etched back by RIE or Chemical Mechanical Polishing (CMP) to expose the surface of the single crystal silicon layer 15, and the like. 21).

Referring to FIG. 1C, the gate oxide film 23 is formed on the surface of the single crystal silicon layer 15 by a thermal oxidation method. Then, amorphous silicon or polysilicon doped with impurities on the field oxide film 21 and the gate oxide film 23 is deposited by CVD and patterned by photolithography so as to remain only in a predetermined portion of the transistor region T1. 25).

Referring to FIG. 1D, an N-type impurity such as acenic or phosphorous (P) is doped at a high concentration on both sides of the gate 25 of the transistor region T1 to be used as a source and a drain region. The region 27 is formed, and the substrate contact region 29 in which the P-type impurities such as boron B or BF ₂ are heavily doped is formed in the contact region BC1. Therefore, the impurity region 27 is formed by forming a photoresist pattern on the contact region BC1 and ion implanting an N-type impurity with a high dose using the photoresist pattern and the gate as a mask. Subsequently, the substrate contact region 29 removes the photoresist pattern for forming the impurity region 27, forms a photoresist pattern on the transistor region T1, and then increases the P-type impurity in the contact region BC1. It is formed by ion implantation into the dose. Then, the photoresist pattern used as the mask is removed.

As described above, in the semiconductor device according to the related art, since the field oxide film is formed to be spaced apart from the buried insulating layer, the carrier generated in the transistor region is emitted through the substrate contact region, thereby preventing the floating body effect.

However, the semiconductor device according to the related art has a problem that it is difficult to optimize the device and the circuit because the transistor regions are all connected and the substrate voltage cannot be applied differently for each device. In addition, a latch-up phenomenon occurs in the CMOS structure.

Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are easy to optimize the device and the circuit by applying different substrate voltages for each device.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent the latch-up phenomenon from occurring in the CMOS structure.

According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, a first conductive single crystal silicon layer formed on the buried insulating layer, and the single crystal silicon. A first field oxide film formed in contact with the buried insulating layer in a first field region defining an active region comprising a transistor region and a contact region in a layer, and a second region defining the transistor region and the contact region in the single crystal silicon layer. A second field oxide film formed in two field regions so as not to contact the buried insulating layer, a gate formed through a gate oxide film on a transistor region of the single crystal silicon layer, and a second conductive type in the transistor region of the single crystal silicon layer. The first conductive type is formed in the contact region between the impurity region formed by doping with a high concentration of impurities and the single crystal silicon layer. It comprises a substrate contact region is formed, the impurity is doped at a high concentration.

In the semiconductor device manufacturing method according to the present invention for achieving the above object is a buried insulating layer is formed on a semiconductor substrate, a pad oxide film and a mask layer on the first conductive type single crystal silicon layer formed on the buried insulating layer Forming and patterning to define an active region consisting of a transistor region and a contact region and a field region comprising first and second field regions, and first anisotropically etching the first field region of the single crystal silicon layer to form a first groove. Forming a second groove by second anisotropically etching the second field region of the single crystal silicon layer and simultaneously etching the first groove to expose the buried insulating layer; And removing the pad oxide film and forming first and second field oxide films in the first and second grooves.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (A) to (D) is a manufacturing process diagram of a semiconductor device according to the prior art

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

4A to 4E are manufacturing process diagrams of the semiconductor device shown in FIG.

5A to 5D are manufacturing process diagrams according to the first embodiment of the semiconductor device shown in FIG.

6A to 6C are manufacturing process diagrams according to the second embodiment of the semiconductor device shown in FIG.

7A to 7C are manufacturing process diagrams according to the third embodiment of the semiconductor device shown in FIG.

* Description of the symbols for the main parts of the drawings *

31 semiconductor substrate 33 buried insulating layer

35 single crystal silicon layer 37 pad oxide film

39 mask layer 41 photoresist pattern

43, 45: first and second grooves 47, 49: first and second field oxide films

51 gate oxide film 53 gate

55 impurity region 57 substrate contact region

T11: transistor area BC11: contact area

F11, F12: first and second field areas

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

In the semiconductor device according to the embodiment, the buried insulating layer 33 is formed on the semiconductor substrate 31, and the single crystal silicon layer 35 doped with P-type impurities is formed on the buried insulating layer 33. It is formed to a thickness of about 300 to 1500Å. In the above, the buried insulating layer 33 and the single crystal silicon layer 35 form an SOI structure and are formed by the SIMOX method, the BE method, or the like. In the case where the buried insulating layer 33 and the single crystal silicon layer 35 are formed by the SIMOX method, the same P type as the single crystal silicon layer 35 is used for the semiconductor substrate 31, and the single crystal silicon is formed by the BE method. Regardless of the layer 35, a P-type or N-type semiconductor substrate 31 is used. In addition, although the single crystal silicon layer 35 has been described as being doped with P-type impurities, N-type impurities may be doped.

First and second grooves 43 and 45 are formed in the single crystal silicon layer 35 in the first and second field regions F11 and F12 that define an active region formed of the transistor region T11. In the above description, the first groove 43 is formed to expose the buried insulating layer 33, and the second groove 45 is formed to be shallower than the first groove 43 so that the buried insulating layer 33 is not exposed. Then, silicon oxide is filled in the first and second grooves 43 and 45 to form first and second field oxide films 47 and 49. That is, in the semiconductor device according to the embodiment of the present invention, the first and second field oxide films 47 and 49 have a structure of STI (Shalllow Trench Isolation).

In this case, the first field oxide film 47 is formed to be connected to the buried insulating layer 33 to completely insulate the devices from adjacent devices, and the second field oxide film 49 is not connected to the buried insulating layer 33. The transistor region T11 and the contact region BC11 in the same active region are connected to each other.

A gate 53 is formed by interposing a gate oxide film 51 in a predetermined portion on the transistor region T11 of the single crystal silicon layer 35. Impurities that are doped at high concentrations with N-type impurities such as an asic (As) or phosphorus (P) on both sides of the gate 53 of the transistor region T11 of the single crystal silicon layer 35 are used as the source and drain regions. Region 55 is formed. A substrate contact region 57 in which the contact region BC11 of the single crystal silicon layer 35 is heavily doped with P-type impurities such as boron B or BF ₂ is formed.

3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

In the semiconductor device according to another embodiment of the present invention, except that the first and second field oxide layers 47 and 49 are not formed of an STI structure but are formed of a Local Oxidation of Silicon (LOCOS) based structure. It is formed in the same structure as the semiconductor device according to the embodiment.

As described above, in the semiconductor device according to the present invention, an adjacent element is formed by forming a first field oxide film formed in a first field region formed of a transistor region and a contact region to define an active region in which the elements are formed to be in contact with a buried insulating layer. The second field oxide film is formed so as not to be in contact with the buried insulating layer in the second field region defining the transistor region and the contact region in the active region. Therefore, it is easy to optimize the holding and circuit by applying different substrate voltages through the substrate contact region for each active region, and also to prevent the latch-up phenomenon from occurring because the adjacent active regions are completely electrically separated from the CMOS structure. can do.

4A to 4E are manufacturing process diagrams of the semiconductor device shown in FIG.

Referring to FIG. 4A, a buried insulating layer 33 is formed on the semiconductor substrate 31, and a P-type single crystal silicon layer 35 having a thickness of about 500 to 2000 GPa is formed on the buried insulating layer 33. Is formed. In the above, the buried insulating layer 33 and the single crystal silicon layer 35 are formed on the semiconductor substrate 31 by the SIMOX method or the BE method. When the buried insulating layer 33 and the single crystal silicon layer 35 are formed by the SIMOX method, the same P-type semiconductor substrate 31 as the single crystal silicon layer 35 is used, and when it is formed by the BE method, P-type or N-type Semiconductor substrate 31 is used.

On the single crystal silicon layer 35, a pad oxide film 37 having a thickness of about 100 to 200 mW was formed by a thermal oxidation method, and silicon nitride was deposited to a thickness of about 1000 to 2000 mW by the CVD method on the pad oxide film 37. The mask layer 39 is formed. The mask layer 39 and the pad oxide film 37 are patterned by a photolithography method so that the single crystal silicon layer 35 is exposed, thereby forming an active region consisting of the transistor region T11 and the contact region BC11, and the first and first layers. A field area consisting of two field areas F11 and F12 is defined.

Referring to FIG. 4B, a photoresist pattern 41 exposing the first field region F11 is formed on the single crystal silicon layer 35. Then, using the photoresist pattern 41 as an etching mask, the first field region F11 exposing the single crystal silicon layer 35 is exposed to a depth of about 1/2, that is, about 250 to 1000 mm by RIE or the like. The first groove 43 is formed by anisotropic etching.

Referring to FIG. 4C, the photoresist pattern 41 is removed to expose the second field region F12 of the single crystal silicon layer 35. Then, using the mask layer 39 as an etching mask, the first and second field regions F11 and F12 of the single crystal silicon layer 35 are anisotropically etched again using a method such as RIE. At this time, the first groove 43 in the first field region F11 is deeper, and the second groove 45 in the second field region F12 is formed. In the above, the second groove 45 is formed by etching until the buried insulating layer 33 is exposed by the first groove 43.

Referring to FIG. 4D, the surface of the single crystal silicon layer 35 is exposed by removing the mask layer 39 and the pass oxide film 37. Then, silicon oxide is deposited by CVD to fill the first and second grooves 43 and 45 on the single crystal silicon layer 35. The silicon oxide is etched back using RIE or CMP to expose the surface of the single crystal silicon layer 35 and the first and second field oxide films 47 are formed in the first and second grooves 43 and 45. Form 49. In this case, the first field oxide film 47 is formed to be connected to the buried insulating layer 33 to completely insulate the devices from adjacent devices, and the second field oxide film 49 is not connected to the buried insulating layer 33. The transistor region T11 and the contact region BC11 in the same active region are connected to each other.

On the surface of the single crystal silicon layer 35, a gate oxide film 51 having a thickness of about 40 to 100 Å is formed by a thermal oxidation method. Then, amorphous silicon or polysilicon doped with impurities on the first and second field oxide films 47 and 49 and the gate oxide film 51 is deposited by CVD, and remains only in a predetermined portion of the transistor region T11. Patterned by lithographic method to form gate 53.

Referring to FIG. 4E, an N-type impurity such as acenic or phosphorous (P) is doped at a high concentration on both sides of the gate 53 of the transistor region T11 to be used as a source and a drain region. The region 55 is formed, and the substrate contact region 57 is heavily doped with P-type impurities such as boron B or BF ₂ in the contact region BC11. In the above, the impurity region 55 is formed by forming a photoresist pattern on the contact region BC11 and ion implanting an N-type impurity with a high dose using the photoresist pattern and the gate as a mask. Subsequently, the substrate contact region 57 removes the photoresist pattern for forming the impurity region 55, and again forms a photoresist pattern on the transistor region T11. It is formed by ion implantation into the dose. Then, the photoresist pattern used as the mask is removed.

5A to 5D are manufacturing process diagrams according to the first embodiment of the semiconductor device shown in FIG.

Referring to FIG. 5A, a buried insulating layer 33 is formed on the semiconductor substrate 31, and a P-type single crystal silicon layer 35 having a thickness of about 500 to 2000 GPa is formed on the buried insulating layer 33. Is formed. A pad oxide film 37 having a thickness of about 100 to 200 Å is formed on the single crystal silicon layer 35 by a thermal oxidation method, and a mask is deposited on the pad oxide film 37 by a CVD method with a thickness of about 1000 to 2000 Å of silicon nitride. Form layer 39. The mask layer 39 and the pad oxide film 37 are patterned by a photolithography method so that the single crystal silicon layer 35 is exposed, thereby forming an active region consisting of the transistor region T11 and the contact region BC11, and the first and first layers. A field area consisting of two field areas F11 and F12 is defined.

Referring to FIG. 5B, a photoresist pattern 41 exposing the first field region F11 is formed on the single crystal silicon layer 35. Then, using the photoresist pattern 41 as an etching mask, the exposed first field region F11 of the single crystal silicon layer 35 is anisotropic to a depth of about 1/2, that is, about 250 to 1000 microns by a method such as RIE. The groove 43 is formed by etching.

Referring to FIG. 5C, the photoresist pattern 41 is removed to expose the second field region F12 of the single crystal silicon layer 35. The first and second field oxide films 47 and 49 are formed on the exposed portions of the single crystal silicon layer 35 by using the mask layer 39 and the pad oxide film 37 as masks. At this time, since the single crystal silicon layer 35 has a large exposed area due to the grooves 43 in the first field region F11, the first field insulating film 47 is not only fast in oxidation but also thin in thickness, so it is buried within a short time. It is formed in contact with the insulating layer 33. However, since the groove 43 is not formed in the second field region F12, the surface area of the single crystal silicon layer 35 is small, so that the oxidation rate is slow and the thickness thereof is so thick that it does not come into contact with the buried insulating layer 33. Is formed. Accordingly, the first field oxide film 47 is formed to be connected to the buried insulating layer 33 to completely insulate the devices from adjacent devices, and the second field oxide film 49 is not connected to the buried insulating layer 33. The transistor region T11 and the contact region BC11 in the same active region are connected to each other. Then, the mask layer 39 and the pad oxide film 37 are removed.

Referring to FIG. 5 (D), a gate oxide film 51 having a thickness of about 40 to about 100 GPa is formed on the surface of the single crystal silicon layer 35 by a thermal oxidation method. Then, amorphous silicon or polycrystalline silicon doped with impurities on the first and second field oxide films 47 and 49 and the gate oxide film 51 is deposited by CVD and remains only in a predetermined portion of the transistor region T11. The gate 53 is formed by patting by lithography.

Next, the process of FIG. 4E is performed.

6A to 6C are manufacturing process diagrams according to the second embodiment of the semiconductor device shown in FIG.

Referring to FIG. 6A, a buried insulating layer 33 is formed on the semiconductor substrate 31, and a P-type single crystal silicon layer 35 having a thickness of about 500 to 2000 GPa is formed on the buried insulating layer 33. Is formed. On the single crystal silicon layer 35, a pad oxide film 37 having a thickness of about 100 to 200 mW was formed by a thermal oxidation method, and silicon nitride was deposited to a thickness of about 1000 to 2000 mW by the CVD method on the pad oxide film 37. The mask layer 39 is formed. The mask layer 39 and the pad oxide film 37 are patterned by a photolithography method so that the single crystal silicon layer 35 is exposed, thereby forming an active region consisting of the transistor region T11 and the contact region BC11, and the first and first layers. A field area consisting of two field areas F11 and F12 is defined.

Referring to FIG. 6B, a photoresist pattern 59 exposing the second field region F12 is formed on the single crystal silicon layer 35. Then, using the photoresist pattern 59 as a mask, ions such as nitrogen or fluorine, which inhibit oxidation, are implanted into the exposed second field region F12 of the single crystal silicon layer 35 to form the ion implantation region 61. Form.

Referring to FIG. 6C, the photoresist pattern 59 is removed to expose the second field region F12 of the single crystal silicon layer 35. The first and second field oxide films 47 and 49 are formed on the exposed portions of the single crystal silicon layer 35 by using the mask layer 39 and the pad oxide film 37 as masks. At this time, the first field oxide film 47 is formed in contact with the buried insulating layer 33. However, due to nitrogen ions in the ion implantation region 61 formed in the second field region F12, the second field oxide film 49 is formed to be in contact with the buried insulating layer 33 due to a slow oxidation rate. Accordingly, the first field oxide film 47 is formed to be connected to the buried insulating layer 33 to completely insulate the devices from adjacent devices, and the second field oxide film 49 is not connected to the buried insulating layer 33. The contact region BC11 of the transistor region T11 in the same active region is connected to each other.

Next, the process after FIG. 5 (D) is performed.

7A to 7C are manufacturing process diagrams according to the third embodiment of the semiconductor device shown in FIG.

Referring to FIG. 7A, a buried insulating layer 33 is formed on the semiconductor substrate 31, and a P-type single crystal silicon layer 35 having a thickness of about 500 to 2000 GPa is formed on the buried insulating layer 33. Is formed. On the single crystal silicon layer 35, a pad oxide film 37 having a thickness of about 100 to 200 Å is formed by a thermal oxidation method. Then, polycrystalline silicon is deposited on the pad oxide film 37 to a thickness of about 300 to 1500 mW by the CVD method to form a buffer layer 63, and on the buffer layer 63, silicon nitride is about 1000 to 2000 mW by the CVD method. The vapor deposition is performed to form the mask layer 39. Then, the mask layer 39 is patterned by a photolithography method so that the buffer layer 63 is exposed, and an active region consisting of the transistor region T11 and the contact region BC11 and the first and second field regions F11 and F12. To define a field area consisting of

Referring to FIG. 7B, a photoresist pattern 65 exposing the first field region F11 is formed on the single crystal silicon layer 35. The buffer layer 63 and the pad oxide film 37 of the second field region F12 are patterned to expose the single crystal silicon layer 35 using the photoresist pattern 65 as a mask.

Referring to FIG. 7C, the photoresist pattern 65 is removed to expose the buffer layer 63 of the second field region F12. First and second field oxide films 47 and 49 are thermally oxidized to the exposed portions of the single crystal silicon layer 35 using the mask layer 39, the buffer layer 63 and the pad oxide film 37 as a mask. To form. At this time, the first field oxide film 47 is formed in contact with the buried insulating layer 33. However, the second field oxide film 49 suppresses the diffusion of oxygen into the single crystal silicon layer 33 after the buffer layer 63 formed in the second field region F12 is rapidly oxidized. Therefore, the second field oxide film 49 prevents the single crystal silicon layer 63 from being oxidized after the buffer layer 63 is oxidized so that it does not come into contact with the buried insulating layer 33. Accordingly, the first field oxide film 47 is formed to be connected to the buried insulating layer 33 to completely insulate the devices from adjacent devices, and the second field oxide film 49 is not connected to the buried insulating layer 33. The transistor region T11 and the contact region BC11 in the same active region are connected to each other.

Next, the process after FIG. 5 (D) is performed.

As described above, in the semiconductor device according to the present invention, an adjacent element is formed by forming a first field oxide film formed in a first field region formed of a transistor region and a contact region to define an active region in which the elements are formed to be in contact with a buried insulating layer. The second field oxide film is formed so as not to be in contact with the buried insulating layer in the second field region defining the transistor region and the contact region in the active region.

Accordingly, the present invention facilitates optimization of devices and circuits by applying different substrate voltages to active regions, and also prevents latch-up from occurring because the active regions are completely separated from the CMOS structure. There is this.

Claims (16)

Semiconductor substrate, A buried insulating layer formed on the semiconductor substrate; A single crystal silicon layer of a first conductivity type formed on the buried insulating layer and spaced apart from each other; A first field oxide film formed in contact with the buried insulating layer in a first field region defining an active region comprising a transistor region and a contact region in the single crystal silicon layer; A second field oxide film formed on the single crystal silicon layer so as not to contact the buried insulating layer in a second field region defining the transistor region and the contact region; A gate formed on the transistor region of the single crystal silicon layer via a gate oxide film; An impurity region formed by doping a high concentration of impurities of a second conductivity type in the transistor region of the single crystal silicon layer; And a substrate contact region formed by highly doping a first conductive type impurity in the contact region of the single crystal silicon layer. The method according to claim 1, A semiconductor device comprising a silicon substrate of a first conductive type of the semiconductor substrate. The method according to claim 1, A semiconductor device comprising a silicon substrate of a first conductive type or a second conductive type of the semiconductor substrate. The method according to claim 1, And the first and second field oxide films have a shallow trench isolation (STI) structure. The method according to claim 1, The first and the second field oxide film is a semiconductor device having a LOCOS (Local Oxidation of Silicon) -based structure. A buried insulating layer is formed on the semiconductor substrate, and a pad oxide film and a mask layer are formed and patterned on the first conductive type single crystal silicon layer formed on the buried insulating layer to form an active region including a transistor region and a contact region. And defining a field region comprising a second field region, Forming a first groove by first anisotropically etching the first field region of the single crystal silicon layer; Exposing the buried insulating layer by etching the second field region of the single crystal silicon layer by second anisotropic etching to form a second groove and simultaneously etching the first groove; And removing the mask layer and the pad oxide film and forming first and second field oxide films in the first and second grooves. The method according to claim 6, Forming a gate oxide film and a gate on the transistor region of the single crystal silicon layer; Forming a second conductive impurity region to be used as a source and a drain region in the transistor region of the single crystal silicon; And forming a substrate contact region of a first conductivity type in the contact region of the single crystal silicon. The method according to claim 6, And a first anisotropic etching of the single crystal silicon layer to form the first groove to a depth of 250 to 1000 GPa. The method according to claim 6, The process of forming the first and second field oxide film, Depositing a silicon oxide layer on the single crystal silicon layer to fill the first and second grooves; And etching back the silicon oxide so as to remain only in the first and second grooves and to expose the surface of the single crystal silicon layer. A buried insulating layer is formed on the semiconductor substrate, and a pad oxide film and a mask layer are formed and patterned on the first conductive type single crystal silicon layer formed on the buried insulating layer to form an active region including a transistor region and a contact region. And defining a field region comprising a second field region, Forming a groove in the first field region of the single crystal silicon layer; The first field oxide film and the second field area are in contact with the buried insulating layer in the first field area where the groove is formed by oxidizing an exposed portion of the single crystal silicon layer using the mask layer and the pad oxide film as masks. Forming a second field oxide film on the buried insulating layer that is not in contact with the buried insulating layer; Removing the mask layer and the pad oxide film and forming a gate oxide film and a gate on the transistor region of the single crystal silicon layer; Forming a second conductive impurity region to be used as a source and a drain region in the transistor region of the single crystal silicon; And forming a substrate contact region of a first conductivity type in the contact region of the single crystal silicon. The method according to claim 10, A method of manufacturing a semiconductor device, wherein the groove is formed by anisotropic etching to a depth of 250 to 1000 GPa. A buried insulating layer is formed on the semiconductor substrate, and a pad oxide film and a mask layer are formed and patterned on the first conductive type single crystal silicon layer formed on the buried insulating layer to form an active region including a transistor region and a contact region. And defining a field region comprising a second field region, Implanting ions that inhibit oxidation into the second field region of the single crystal silicon layer; Using the mask layer and the pad oxide film as a mask, the exposed portion of the single crystal silicon layer is oxidized to contact the buried insulating layer in the first field region and the buried insulation in the second field region. Forming a second field oxide film not in contact with the layer, Removing the mask layer and the pad oxide film and forming a gate oxide film and a gate on the transistor region of the single crystal silicon layer; Forming a second conductive impurity region to be used as a source and a drain region in the transistor region of the single crystal silicon; And forming a substrate contact region of a first conductivity type in the contact region of the single crystal silicon. The method according to claim 12, A method of manufacturing a semiconductor device, wherein nitrogen or fluorine ions are implanted into the second field region of the single crystal silicon layer to suppress oxidation. A buried insulating layer is formed on the semiconductor substrate, a pad oxide film, a buffer layer, and a mask layer are formed on the first conductive single crystal silicon layer formed on the buried insulating layer, and the mask layer is patterned to expose the buffer layer. Defining an active region comprising a transistor region and a contact region and a field region comprising first and second field regions, Patterning the buffer layer and the pad oxide film in the first field region to expose the single crystal silicon layer; Oxidizing the exposed single crystal silicon layer of the first field region and the buffer layer of the second field region to form a first field oxide film in contact with the buried insulation layer and a second field oxide film not in contact with the buried insulation layer and, Removing the mask layer, the buffer layer and the pad oxide film, and forming a gate oxide film and a gate on the transistor region of the single crystal silicon layer; Forming a second conductive impurity region to be used as a source and a drain region in the transistor region of the single crystal silicon; And forming a substrate contact region of a first conductivity type in the contact region of the single crystal silicon. The method according to claim 14, A method for manufacturing a semiconductor device, wherein the buffer layer is formed of polycrystalline silicon. The method according to claim 15, A method for manufacturing a semiconductor device, wherein the buffer layer is formed to a thickness of 300 to 1500 Å.