KR19980083554A - Clock Regeneration Device for Digital Communication System - Google Patents

Abstract

An apparatus for reproducing a clock from a bipolar signal received in a digital communication system, comprising: first and second digital filters for removing noise of each polarity signal, and an output of the first and second digital filters An orifice for outputting a signal; a pulse generator for generating a pulse having a predetermined width from the received data as a reference signal; a phase detector for detecting a phase error for each polarity from the reference signal; The phase error calculation unit which counts the phase error with a predetermined clock and generates an increase or decrease request signal when the value reaches a predetermined threshold value, and the increase or decrease request signal for a signal having a predetermined frequency generated by the temperature compensated crystal oscillator. And a regeneration clock output unit which outputs a regeneration clock by dividing a predetermined frequency according to the occurrence state of.

Description

Clock Regeneration Device for Digital Communication System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproducing apparatus in a digital communication system, and more particularly, to an apparatus for generating a predetermined reference signal and regenerating a clock from G.703 received data which is a bipolar signal.

Digital transmissions require more bandwidth per channel than analog transmissions. Also, considering economics, analog transmission is more advantageous than digital transmission. Nevertheless, digital transmission has continued to develop because digital transmission has many advantages, such as no signal distortion and easy signal processing.

Signals used in digital communication are often unipolar, TTL (transistor transistor logic) or CMOS (Complementary Metal-Oxide-Semiconductor) signal. However, communication between stations or signals with other systems in the country is difficult to transmit with unipolar signals. In this case, the unipolar signal is converted into a bipolar signal and used. G.703 The same method is used for 64 Kbps codirectional data transmission. That is, the line encoding method converts a 64Kbps '1' signal into a 256Kbps signal of '1100' and a 64Kbps '0' signal into a 256Kbps signal of '1010'. The transmitter increases the frequency from 64Kbps to 256Kbps and converts the signal into a bipolar signal. The receiver reproduces the clock, that is, 256Kbps from the data, and extracts the received data from the reproduced clock. In this process, a reference signal is generated from the received data, which is an important factor for implementing a phase locked loop (hereinafter referred to as a PLL).

1 is a block diagram of a conventional clock reproducing apparatus, which adopts an analog-PLL scheme.

When the received bipolar signals are converted into unipolar signals RD + and RD- and input to the oragate 10 as shown, the oragate 10 outputs the received data DAT by ORing the two signals. The pulse generator 100 generates a pulse having a predetermined width from the received data DAT as a reference signal REF. Specifically, when the delay unit 24 delays and outputs the received data DAT, the edge detector 25 detects a rising edge from the output of the delay unit 24. The pulse generator 26 generates a predetermined pulse, the width of which depends on the detection of the rising edge.

Phase comparator 11 compares the reference signal REF with the variable signal VAR generated therein and then phase error. Detect. Loop filter 12 is the phase error The width of control voltage is determined according to the size of. Voltage controlled oscillator (hereinafter referred to as VCO) 13 generates a 256KHz clock that matches the control voltage.

However, the configuration of FIG. 1 requires an active device such as an operational amplifier, a VCO, and a passive device such as a resistor, a capacitor, and a coil separately. In addition, these devices have a great influence on environmental factors such as temperature and humidity, and thus, it is difficult to obtain the same circuit characteristics. Therefore, a lot of manufacturing process is required when producing a product, and has a problem of raising the production cost.

In another aspect, when the polarized G.703 signal is converted to unipolar, glitch may be generated during slicing by impulsive noise and level detection occurring in a transmission interval. The problem of clock reproduction due to the glitch can be solved by the loop filter 12, but there is a high possibility of causing an error since noise on the received data cannot be removed.

In another aspect, when the received data of the G.703 signal is 0 [1010], the clock reproduction of 256 KHz frequency is easy, but the clock reproduction of the 1 [1100] signal is difficult. In some cases, if the size of the passive elements of the loop filter is changed, the clock regeneration may fail when the 1 [1100] signal is repeated.

Accordingly, an object of the present invention is to generate a predetermined reference signal from the G.703 received data, which is a bipolar signal, and to provide a device capable of stable operation in any environment by reducing a system error by reproducing a stable clock. Is in.

According to an aspect of the present invention, there is provided an apparatus for reproducing a clock from a polarity signal received in a digital communication system, the apparatus comprising: first and second digital filters for removing noise of each polarity signal; An OR gate for outputting received data by ORing the outputs of two digital filters, a pulse generator for generating a pulse having a predetermined width from the received data as a reference signal, and detecting a phase error for each polarity from the reference signal. A phase detection unit for counting the phase error of each polarity with a predetermined clock and generating an increase or decrease request signal when the value reaches a predetermined threshold, and a predetermined frequency generated by the temperature compensated crystal oscillator. Reproduction for outputting a reproduction clock by dividing a signal having a predetermined frequency according to the state of occurrence of the increase or decrease Characterized by the configured portion Luck output.

1 is a block diagram of a conventional clock reproducing apparatus

2 is a block diagram illustrating a clock reproducing apparatus according to an exemplary embodiment of the present invention.

3 is an operation timing diagram of the clock reproducing apparatus of FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. Also, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a block diagram of a clock reproducing apparatus according to an exemplary embodiment of the present invention, and employs a digital-PLL scheme.

The received bipolar signals are converted into unipolar signals RD + and RD- and input to the first and second digital filters 21 and 22, respectively, as shown. The first and second digital filters 21 and 22 remove noise of each polarity signal. The OR gate 10 outputs the received data DAT by ORing the outputs of the first and second digital filters 21 and 22. The pulse generator 100 generates a pulse having a predetermined width from the received data DAT as a reference signal REF. Specifically, when the delay unit 24 delays and outputs the received data DAT, the edge detector 25 detects a rising edge from the output of the delay unit 24. The pulse output section 26 generates a predetermined pulse, the width of which depends on the detection of the rising edge.

The digital PLL unit 200 includes a phase detector 27, a phase error calculator 28, and a reproduction clock output unit 55. The phase detector 27 detects a phase error for each polarity from the reference signal. The phase error calculator 28 counts the phase error for each polarity with a predetermined clock and generates a decrease request signal Dec or an increase request signal Inc when the value reaches a predetermined threshold. The regeneration clock output unit 55 divides a signal having a predetermined frequency generated by a temperature compensation crystal oscillator (hereinafter referred to as TCXO) according to the generation state of the reduction request signal Dec or the increase request signal Inc. To output the reproduction clock.

The regeneration clock output unit 55 divides a signal having a predetermined frequency generated by the TCXO into first, second, and third divisions in response to generation of the increase request signal Dec, the steady state, and the decrease request signal Inc, respectively. (number controlled oscillator) 29 and a divider 30 for dividing the output of the oscillator 29 to output a reproduction clock.

3 is an operation timing diagram of the clock reproducing apparatus of FIG. 2. The operation of the clock reproducing apparatus will be described in detail with reference to the timing diagram as follows.

(3a) represents 64 Kbps data, and (3b) represents 256 Kbps data.

(3c) is a G.703 signal including a noise component, and (3d) shows a form in which glitches exist in the RD + signal converted from the G.703 signal because of the noise component. (3e) shows the form of the RD-signal converted from the G.703 signal. The first or second digital filters 21 and 22 used in the present embodiment use a majority vote logic correction method, which reads the RD + and RD- signals with a 16.384 MHz clock, which is the output of the TCXO, and includes a small number between the consecutive '1's. '0' is regarded as '1'. In the same way, a small number of '1's contained between consecutive' 0's are regarded as '0'. The generated RDP signal or RDN signal removes the glitch included in the original signal, and a slight time delay occurs compared to the original signal. The logical sum of the RDP signal and the RDN signal is the received data DAT, and the received data DAT has a stronger noise immunity than the conventional case. (3f) is the RDP signal, (3g) is the RDN signal, and (3h) is the received data DAT.

(3i) shows a pulse having a predetermined width generated from the received data DAT, that is, the reference signal REF. (3j) shows the variable signal VAR generated therein. Referring to FIG. 2, the reception data DAT is delayed by the delay unit 24 for a predetermined time because the pulse width of the reference signal REF applied in this embodiment is smaller than the 256 KHz reproduction clock period, so that the reproduction clock is in the middle of the reception data DAT. It is necessary to read exactly from The edge detector 25 and the pulse output unit 26 generate pulses starting from the rising edge of the signal output from the delay unit 24 as shown in (3i) above. The signal thus generated is the reference clock of the digital-PLL unit 200, and the width of the pulse is smaller than the period of the variable signal VAR shown in (3j). This method generates the same reference signal whether the received signal is 1 [1100] or 0 [1010], thereby having the same reproduction characteristics regardless of the shape of the signal. The phase detector 27 detects a phase error only during the reference signal period. '-' Phase error [-] when the variable signal VAR is high [1] during the reference signal period. ], If low [0] '+' phase error [+ ] Is considered. The phase error calculator 28 counts the phase error with a clock of 16.384 MHz. That is, the phase error calculation unit 28 performs the '-' phase error [- ] And '+' phase error [+ ] Is continuously counted to generate the decrement request signal Dec or the increase request signal Inc when the threshold is reached. If neither the reduction request signal Dec nor the increase request signal Inc are present, that is, in normal operation, the oscillator 29 divides the 16.384 MHz clock into four divisions. On the other hand, if the decrease request signal Dec is present, the frequency divider is divided by 5, and when the increase request signal Inc is present, the frequency divider is divided. A 256 KHz reproduction clock is obtained by dividing the output of the oscillator 26 by 16, and this signal is fed back as a variable signal VAR of the digital-PLL unit 200. The frequency of 256 Kbps used in this embodiment is used for retiming the received data, and can be read accurately in the middle of the received data DAT as shown in (3j).

In this embodiment, TCXO is used instead of VCO. The VCO is an analog device that is not only sensitive to external environments such as temperature changes and humidity, but also more expensive than the TCXO used in digital-PLL circuits. In other words, the TCXO may be relatively inexpensive and not sensitive to external environmental changes. In addition, since the TCXO can be commonly used in multiple integrated circuits in a unit, it is more advantageous when several clock recovery circuits are required in one unit.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

The present invention as described above has the advantage of reducing the error of the system by digitizing all the circuits required for clock reproduction for stable clock reproduction and to enable the system to operate in any environment stable.

Claims (9)

An apparatus for reproducing a clock from a bipolar signal received by a digital communication system, First and second digital filters for removing noise of each polarity signal; An orifice for outputting received data by ORing the outputs of the first and second digital filters; A pulse generator for generating a pulse having a predetermined width from the received data as a reference signal; A phase detector for detecting a phase error of each polarity from the reference signal; A phase error calculator for counting the phase error of each polarity with a predetermined clock and generating an increase or decrease request signal when the value reaches a predetermined threshold value; And a regeneration clock output unit for dividing a signal having a predetermined frequency generated by a temperature compensated crystal oscillator by a predetermined division according to a state of generating the increase or decrease request signal and outputting a regeneration clock. The method of claim 1, wherein the received data, G.703 Device characterized by a 64 Kbps bipolar signal. The method of claim 2, Wherein the signal generated by the temperature compensated crystal oscillator is 16.384 MHz. The method of claim 3, The received data is a device characterized in that the serial signal of 256Kbps. The method of claim 2, And the reproduction clock is fed back to the phase detector. The method of claim 2, wherein the pulse generation unit, A delay unit for delaying the received data a predetermined delay; An edge detector for detecting a rising edge from an output of the delay unit; And a pulse output unit for outputting a predetermined pulse having a width in accordance with the detection of the rising edge. The method of claim 1, wherein the regeneration clock output unit, An oscillator for dividing a signal having a predetermined frequency generated by a temperature compensated crystal oscillator in response to generation of the increase request signal, the steady state, and the decrease request signal, respectively; And a divider for dividing an output of the oscillator and outputting a reproduction clock. 8. The apparatus according to any one of claims 1 to 7, wherein the pulse width is shorter than a period of the reproduction clock. An apparatus for reproducing a clock from a bipolar signal received by a digital communication system, First and second digital filters for removing noise of each polarity signal; An orifice for outputting received data by ORing the outputs of the first and second digital filters; A delay unit for delaying the received data a predetermined delay; An edge detector for detecting a rising edge from an output of the delay unit; Generating a predetermined pulse, the width of the pulse being a pulse generator in accordance with the detection of the rising edge; A phase detector for detecting a phase error of each polarity from the reference signal; A phase error calculator for counting the phase error of each polarity with a predetermined clock and generating an increase or decrease request signal when the value reaches a predetermined threshold value; An oscillator for dividing a signal having a predetermined frequency generated by a temperature compensated crystal oscillator in response to generation of the increase request signal, the steady state, and the decrease request signal, respectively; And a divider for dividing an output of the oscillator and outputting a reproduction clock.