KR19980083097A - Crystallization method of amorphous silicon layer and manufacturing method of thin film transistor using same - Google Patents
Crystallization method of amorphous silicon layer and manufacturing method of thin film transistor using same Download PDFInfo
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- KR19980083097A KR19980083097A KR1019970018243A KR19970018243A KR19980083097A KR 19980083097 A KR19980083097 A KR 19980083097A KR 1019970018243 A KR1019970018243 A KR 1019970018243A KR 19970018243 A KR19970018243 A KR 19970018243A KR 19980083097 A KR19980083097 A KR 19980083097A
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- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 78
- 239000010409 thin film Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 238000002425 crystallisation Methods 0.000 title description 15
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000001678 irradiating effect Effects 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 18
- 238000000206 photolithography Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005224 laser annealing Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 102
- 239000013078 crystal Substances 0.000 description 43
- 239000002245 particle Substances 0.000 description 18
- 239000007787 solid Substances 0.000 description 10
- 230000008025 crystallization Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- -1 respectively Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
본 발명은 비정질 실리콘층의 결정화 방법 및 이를 사용한 박막트랜지스터의 제조방법에 관한 것으로, 비정질 실리콘층을 결정화하기 위하여 절연기판에 채널영역이 정의되는 비정질 실리콘층을 형성하는 단계와, 상기 비정질 실리콘층의 채널영역에 트렌치를 형성하는 단계와, 상기 비정질 실리콘층에 레이저를 조사하여 상기 비정질 실리콘층이 용융 및 고화되는 과정에서 상기 비정질 실리콘층을 결정화하는 단계를 포함하며, 캡핑층(capping layer)을 형성하지 않고도 비정질 실리콘층의 채널영역(channel region)을 결정화함으로써 캡핑층의 형성으로 인한 채널영역의 손상을 감소시킬 수 있다.The present invention relates to a method of crystallizing an amorphous silicon layer and a method of manufacturing a thin film transistor using the same, forming an amorphous silicon layer having a channel region defined on an insulating substrate in order to crystallize the amorphous silicon layer, and Forming a trench in a channel region, and crystallizing the amorphous silicon layer in the process of melting and solidifying the amorphous silicon layer by irradiating the amorphous silicon layer with a laser; forming a capping layer By crystallizing the channel region of the amorphous silicon layer without damage, damage to the channel region due to the formation of the capping layer can be reduced.
Description
본 발명은 비정질 실리콘층의 결정화 방법 및 이를 사용한 박막트랜지스터의 제조방법에 관한 것으로 특히, 캡핑층(capping layer)을 형성하지 않고도 비정질 실리콘층의 채널영역(channel region)을 결정화함으로써, 캡핑층의 형성으로 인한 채널영역의 손상을 감소시킬 수 있는 비정질 실리콘층의 결정화 방법 및 이를 이용한 박막트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of crystallizing an amorphous silicon layer and a method of manufacturing a thin film transistor using the same, in particular, by forming a capping layer by crystallizing a channel region of the amorphous silicon layer without forming a capping layer. The present invention relates to a crystallization method of an amorphous silicon layer capable of reducing damage to a channel region due to the same, and a method of manufacturing a thin film transistor using the same.
비정질 실리콘(amorphous silicon)에 레이저 등의 에너지를 공급하여 용융상태로 만든 후에, 냉각 또는 고화시키면, 결정으로서 석출되어 간다. 이때 최초에 생긴 작은 결정핵이 씨(seed)가 되어 점점 성장해가면서 큰 결정을 형성함으로써 결정화가 이루어진다. 이때, 결정의 성장조건에 영향을 받아 결정의 성장방향이 단일하도록 성장하게 되면, 단결정(single-crystallization)이 되고, 많은 결정이 동시에 생성되고, 성장하여 다결정(poly-crystallization)이 된다.After supplying energy, such as a laser, to amorphous silicon to make it molten and cooling or solidifying, it precipitates as crystals. At this time, the first small crystal nucleus becomes seed and grows to form large crystals. At this time, when the growth direction of the crystal grows so as to be affected by the growth conditions of the crystal, it becomes a single crystal (single-crystallization), a large number of crystals are produced at the same time, and grow to become poly-crystallization (poly-crystallization).
비정질 실리콘을 사용하는 박막트랜지스터는 단결정 혹은 다결정 실리콘을 사용하는 박막트랜지스터보다 저온에서 형성될 수 있다는 장점이 있으나, 채널영역으로 캐리어(carrier)의 이동도가 낮다는 단점을 가지고 있다. 또한, 다결정 실리콘을 사용하는 박막트랜지스터는 단결정 실리콘을 사용하는 박막트랜지스터에 비해 위치에 따라 성질이 다른 결정들이 만들어지므로 특성이 균일하지 않아서, 캐리어의 이동도가 낮다. 이는 다결정 실리콘이 단결정 실리콘에 비교할 때 결정입자가 많기 때문인데, 결정입자가 많을 수록 채널의 캐리어들이 많은 결정입자의 벽을 통과하여야 하는 그레인 바운더리 효과(grain boundary effect)에 영향을 받기 때문이다. 따라서 비정질 실리콘을 결정화하여 채널영역으로 사용할 박막트랜지스터에 있어서는, 결정화 공정시, 결정입자가 크도록 형성함으로써, 결정입자의 수를 줄여서 그레인 바운더리 효과를 감소시키는 것이 캐리어의 이동도를 높이는 방법이다. 그런데 레이저를 조사하여 비정질 실리콘을 결정화한 후의 결정입자의 크기는 레이저 에너지 밀도, 기판의 온도 및 결정화 속도에 함수관계를 나타낸다. 따라서 이들의 관계를 이용하여 비정질 실리콘에서 결정입자의 생성 및 성장을 적절하게 조절하는 것이 중요하다.A thin film transistor using amorphous silicon has an advantage that it can be formed at a lower temperature than a thin film transistor using single crystal or polycrystalline silicon, but has a disadvantage of low carrier mobility in the channel region. In addition, thin film transistors using polycrystalline silicon are not uniform in characteristics because crystals having different properties are made according to positions, compared to thin film transistors using single crystal silicon, so that carrier mobility is low. This is because polycrystalline silicon has more crystal grains as compared to single crystal silicon, because the more crystal grains are affected by the grain boundary effect that the carriers of the channel have to pass through the walls of many crystal grains. Therefore, in the thin film transistor to be used as the channel region by crystallizing the amorphous silicon, the crystal grains are formed to be large during the crystallization process, thereby reducing the grain boundary effect by reducing the number of crystal grains. However, the size of crystal grains after crystallizing amorphous silicon by laser irradiation shows a functional relationship to laser energy density, substrate temperature and crystallization rate. Therefore, it is important to appropriately control the formation and growth of crystal grains in amorphous silicon using these relationships.
도 1A부터 도 1D는 박막트랜지스터의 채널영역을 결정화시키는 종래의 기술을 설명하기 위한 도면으로, 캡핑층을 이용하여, 채널영역 결정화하는 공정을 나타낸다.1A to 1D are views for explaining a conventional technique of crystallizing a channel region of a thin film transistor, and show a process of crystallizing a channel region using a capping layer.
산화실리콘이나 질화실리콘과 같은 반반사 코팅물질(antireflective coatings)로 형성되는 캡핑층은 그 하부에 있는 비정질 실리콘층 영역이 그렇지 않은 비정질 실리콘층 영역보다 더 빨리 승온되게 한다. 따라서 캡핑층 하부에 있는 비정질 실리콘층 영역이 완전하게 용융되도록 하고, 그렇지 않은 비정질 실리콘층 영역은 완전하게 용융되지 않도록 하는 적절한 크기의 에너지 밀도를 가지는 레이저를 조사함으로써, 채널영역의 결정화공정을 진행한다.The capping layer formed of antireflective coatings such as silicon oxide or silicon nitride allows the amorphous silicon layer region beneath it to warm up faster than the amorphous silicon layer region. Therefore, the crystallization process of the channel region is performed by irradiating a laser having an energy density of an appropriate size such that the amorphous silicon layer region under the capping layer is completely melted, and the non-crystalline silicon layer region is not completely melted. .
도 1A를 참조하면, 유리기판(10)에 박막트랜지스터의 활성층을 형성할 비정질 실리콘층(11)을 형성한다. 이후, 캡핑층을 형성하기 위하여 실리콘 산화막을 형성한 후, 실리콘 산화막에 사진식각공정을 실시하여 캡핑층(12)을 형성한다. 이때 비정질 실리콘층(11)에서 채널영역으로 예정될 부분의 상단에 캡핑층(12)이 형성되도록 한다. 이어서, 적당한 에너지를 가지는 레이저를 전면에 조사한다.Referring to FIG. 1A, an amorphous silicon layer 11 for forming an active layer of a thin film transistor is formed on a glass substrate 10. Thereafter, after forming a silicon oxide film to form a capping layer, a capping layer 12 is formed by performing a photolithography process on the silicon oxide film. In this case, the capping layer 12 is formed on the upper portion of the amorphous silicon layer 11 to be a channel region. Subsequently, the front side is irradiated with a laser having a suitable energy.
도 1B를 참조하면, 레이저 조사 결과, 캡핑층(12) 하부에 있는 비정질 실리콘층 영역(이하 채널영역이라 한다.)(11C)은 언급한 바와 같이, 캡핑층(12)의 영향으로 완전히 용융되며, 캡핑층(12)이 상부에 위치하지 않은 비정질 실리콘층 영역(이하 비채널영역이라 한다.)(11A)은 완전히 용융되지 않아 고체입자(11s)가 잔존하게 된다.Referring to FIG. 1B, as a result of laser irradiation, the amorphous silicon layer region (hereinafter referred to as a channel region) 11C below the capping layer 12 is completely melted under the influence of the capping layer 12 as mentioned. 11A of the amorphous silicon layer region (hereinafter referred to as non-channel region) in which the capping layer 12 is not located at the top is not completely melted so that the solid particles 11s remain.
도 1C를 참조하면, 용융된 비정질 실리콘층은 점진적으로 고화 혹은 냉각되어 결정성장이 이루어진다. 비채널영역(11A)에 용융되지 않고 잔존하는 고체입자(11s)는 이 과정에서 씨드(seed)로 작용하게 되어 결정성장을 진행한다. 즉, 잔존하는 각 고체입자는 씨드로 작용하게 되어 각기 결정성장을 하게 되고, 동시에 여러 곳에서 많은 결정이 생성 및 성장하게 된다. 그 결과 성장된 많은 결정들이 서로 엉키게 되어 다결정질을 이룬다. 이때 캡핑층 하부에 위치하는 채널영역(11C)은 캡핑층(12)의 영향으로 고화 또는 냉각되는 속도가 비채널영역(11A)에 비교하여 아주 작기 때문에 여전히 용융된 상태로 있게 된다.Referring to FIG. 1C, the molten amorphous silicon layer is gradually solidified or cooled to achieve crystal growth. The solid particles 11s that remain without melting in the non-channel region 11A act as seeds in this process and proceed with crystal growth. That is, each of the remaining solid particles acts as a seed, so that each crystal grows, and many crystals are produced and grown in various places at the same time. As a result, many grown crystals become entangled with one another and are polycrystalline. At this time, the channel region 11C positioned below the capping layer remains molten because the rate of solidification or cooling due to the capping layer 12 is very small compared to the non-channel region 11A.
도 1D를 참조하면, 비채널영역(11A)에서 성장되는 다결정질이 아직 용융상태로 존재하는 채널영역(11C)에 다다르게 되면, 채널영역(11C)과 경계가 되는 비채널영역(11A)에 형성된 다결정질의 바운더리(11L)가 새로운 씨드로 작용하게 되어 바운더리 래터럴 성장(boundary lateral growth)이 이루어진다. 그 결과 채널영역(11C)에는 입자의 크기가 큰 결정이 형성된다.Referring to FIG. 1D, when the polycrystalline grown in the non-channel region 11A reaches the channel region 11C that is still present in the molten state, it is formed in the non-channel region 11A that is bounded by the channel region 11C. The polycrystalline boundary 11L acts as a new seed, resulting in boundary lateral growth. As a result, crystals having a large particle size are formed in the channel region 11C.
이와 같이 하여 결정성장이 끝나면, 채널영역에서는 입자의 크기가 큰 결정질을 얻을 수 있어서, 결정입자의 바운더리 수를 줄일 수 있다. 따라서 그레인 바운더리 효과를 억제할 수 있기 때문에 캐리어의 이동도가 큰 채널 영역을 형성할 수 있는 것이다.When the crystal growth is completed in this way, the crystal grains having a large particle size can be obtained in the channel region, so that the number of boundaries of the crystal grains can be reduced. Therefore, the grain boundary effect can be suppressed, so that a channel region with large carrier mobility can be formed.
그러나 이와 같은 종래의 기술에서, 산화실리콘으로 형성되는 캡핑층이 전체적으로 그 두께가 균일하거나, 적절하지 않으면, 결정화를 위한 레이저를 조사하는 과정에서 캡핑층에 균열이 일어나는 등의 손상이 일어나게 된다. 그 결과 캡핑층 하부에 위치하는 비정질 실리콘층 즉, 채널영역의 결정화가 불량하게 일어나거나, 물질특성에 손상을 주게 된다.However, in such a conventional technique, if the capping layer formed of silicon oxide is uniform in thickness or not appropriate as a whole, damage such as cracking of the capping layer occurs in the process of irradiating a laser for crystallization. As a result, the crystallization of the amorphous silicon layer, that is, the channel region, located under the capping layer is poor, or the material properties are damaged.
본 발명은 비정질 실리콘으로 형성된 채널영역을 결정화하는 공정에서 캡핑층을 형성하지 않고, 단지 비정질 실리콘의 두께를 적절하게 조절하여 레이저 에너지의 흡수정도를 조절함으로써, 채널영역에 손상을 주지 않은 상태에서 결정화 공정을 진행하려 하는 것이다.The present invention does not form a capping layer in the process of crystallizing a channel region formed of amorphous silicon, but only by appropriately adjusting the thickness of the amorphous silicon to control the absorption of laser energy, thereby crystallizing in a state without damaging the channel region. We are going to proceed with the process.
이를 위한 본 발명은 절연기판에 채널영역을 비채널영역보다 얇게 형성되는 비정질 실리콘층에 레이저 어닐링을 실시하여 상기 비정질 실리콘층을 결정화하는 비정질 실리콘층의 결정화 방법이다.The present invention for this purpose is a method of crystallizing an amorphous silicon layer to crystallize the amorphous silicon layer by performing laser annealing on the amorphous silicon layer formed in the insulating substrate thinner than the non-channel region channel region.
본 발명은 절연기판에 채널영역이 정의되는 비정질 실리콘 층을 형성하는 단계와, 상기 비정질 실리콘층의 채널영역에 트렌치를 형성하는 단계와, 상기 비정질 실리콘층에 레이저를 조사하여 상기 비정질 실리콘층을 결정화하는 단계를 포함하는 비정질 실리콘층의 결정화 방법이다.The present invention provides a method of forming an amorphous silicon layer having a channel region defined on an insulating substrate, forming a trench in a channel region of the amorphous silicon layer, and irradiating a laser to the amorphous silicon layer to crystallize the amorphous silicon layer. It is a crystallization method of an amorphous silicon layer comprising a step.
또한, 본 발명에 의하여 결정화된 실리콘층을 이용하여 박막트랜지스터를 제조하는 방법에는 절연기판에 채널영역이 정의되는 비정질 실리콘층을 형성하는 단계와, 상기 비정질 실리콘층의 채널영역에 트렌치를 형성하는 단계와, 상기 비정질 실리콘층에 레이저를 조사하여 상기 비정질 실리콘층을 결정화하는 단계와, 상기 결정화된 실리콘층에 사진식각공정을 진행하여 채널영역을 포함하는 활성층을 형성하는 단계와, 상기 활성층상에 게이트절연막과 게이트전극을 순차적으로 형성하는 단계와, 상기 게이트전극을 마스크로하여 이온도핑 공정을 실시하여 상기 채널영역의 좌우측에 접하는 소오스 및 드레인영역을 형성하는 단계와, 상기 게이트절연막에 상기 소오스 및 드레인영역의 일부를 노출시키는 콘택홀을 형성하는 단계와, 상기 노출된 소오스 및 드레인영역에 각각 연결된 소오스 및 드레인전극을 형성하는 단계를 포함한다.In addition, the method for manufacturing a thin film transistor using the silicon layer crystallized by the present invention comprises the steps of forming an amorphous silicon layer defining a channel region on an insulating substrate, and forming a trench in the channel region of the amorphous silicon layer Irradiating a laser to the amorphous silicon layer to crystallize the amorphous silicon layer, and performing a photolithography process on the crystallized silicon layer to form an active layer including a channel region, and forming a gate on the active layer. Sequentially forming an insulating film and a gate electrode, performing an ion doping process using the gate electrode as a mask, and forming source and drain regions in contact with the left and right sides of the channel region, and forming the source and drain in the gate insulating film. Forming a contact hole exposing a portion of the region; And forming a source and drain electrodes respectively connected to the OSU and the drain region.
이때, 비정질 실리콘층을 결정화하는 단계와, 결정화된 실리콘층에 사진 식각공정을 진행하여 활성층을 형성하는 단계는 그 순서를 바꾸어 진행할 수 있다.In this case, the step of crystallizing the amorphous silicon layer and the step of forming an active layer by performing a photolithography process on the crystallized silicon layer may be reversed.
도 1A부터 도 1D는 종래 기술에 의한 비정질 실리콘층의 결정화 방법을 설명하기 위한 도면1A to 1D are views for explaining a crystallization method of an amorphous silicon layer according to the prior art.
도 2A부터 도 2D는 본 발명에 따른 비정질 실리콘층의 결정화 방법의 제 1 실시예를 나타낸 도면2A to 2D show a first embodiment of a method for crystallizing an amorphous silicon layer according to the present invention.
도 3A부터 도 3C는 본 발명의 제 1 실시예에 의한 실리콘층을 이용한 박막트랜지스터의 제조공정도3A through 3C are manufacturing process diagrams of the thin film transistor using the silicon layer according to the first embodiment of the present invention.
도 4A부터 도 4E는 본 발명에 따른 비정질 실리콘층의 결정화 방법의 제 2 실시예를 나타낸 도면4A through 4E illustrate a second embodiment of a method of crystallizing an amorphous silicon layer according to the present invention.
도 5는 본 발명의 제 2 실시예에 의한 실리콘층을 이용하여 제조된 박막트랜지스터5 is a thin film transistor manufactured using a silicon layer according to a second embodiment of the present invention
도 6은 본 발명에 따른 비정질 실리콘층의 결정화 방법의 제 3 실시예를 설명하기 위한 도면6 is a view for explaining a third embodiment of the method of crystallizing an amorphous silicon layer according to the present invention;
*도면의 주요부분에 대한 부호의 설명** Explanation of symbols for main parts of drawings *
20. 절연기판21. 비정질 실리콘층20. Insulation substrate 21. Amorphous silicon layer
21A. 비채널영역21C. 채널영역21A. Non-Channel Area 21C. Channel area
21L. 채널영역의 래터럴성장시, 씨드로 작용하는 바운더리부분21L. Boundary part acting as seed during lateral growth of channel area
21S. 소오스영역21D. 드레인영역21S. Source area 21D. Drain area
23. 게이트전극25S. 소오스전극23. Gate electrode 25S. Source electrode
25D. 드레인전극25D. Drain electrode
도 2A부터 도 2D는 본 발명에 따른 비정질 실리콘층의 결정화 방법의 제 1 실시예를 설명하기 위한 도면이다.2A to 2D are views for explaining a first embodiment of a method for crystallizing an amorphous silicon layer according to the present invention.
도 2A를 참조하면, 유리기판(20)에 박막트랜지스터의 활성층을 형성할 비정질 실리콘층(21)을 형성한다. 이후, 채널영역(21C)으로 정의된 부분이 비채널영역(21A)으로 정의된 부분보다 얇은 두께를 가지도록 형성한다. 이는 막의 두께에 따른 레이저 에너지의 흡수정도의 함수관계를 이용한 것으로, 레이저 조사시, 채널영역(21C)을 완전히 용융시키고, 비채널영역(21A)을 부분적으로 용융시켜서 입자를 잔존시키게 하기 위한 것이다.Referring to FIG. 2A, an amorphous silicon layer 21 for forming an active layer of a thin film transistor is formed on the glass substrate 20. Thereafter, the portion defined by the channel region 21C is formed to have a thickness thinner than the portion defined by the non-channel region 21A. This is a function of the degree of absorption of the laser energy according to the thickness of the film, which is used to completely melt the channel region 21C and partially melt the non-channel region 21A during laser irradiation so that the particles remain.
이를 성취하기 위하여 유리기판(20)에 화학기상증착법, 혹은 스퍼터링법을 사용하여 비정질 실리콘층(21)을 형성한 후, 비정질 실리콘층(21)에 채널영역이 정의된 패턴마스크를 이용한 사진식각공정을 실시하여 비정질 실리콘층의 채널영역(21C)이 되는 부분에 트렌치를 형성한다.To achieve this, after forming the amorphous silicon layer 21 on the glass substrate 20 by chemical vapor deposition or sputtering, a photolithography process using a pattern mask in which a channel region is defined on the amorphous silicon layer 21 is formed. The trench is formed in a portion of the amorphous silicon layer, which becomes the channel region 21C.
이후, 비정질 실리콘층(21)을 용융시키기 위하여 레이저를 전면에 조사한다. 이때 레이저의 에너지 크기는 비정질 실리콘층(21)의 채널영역(21C)과 비채널영역(21A)의 두께를 고려하여 채널영역(21C)은 완전히 용융되게 하고, 비채널영역(21A)은 부분적으로 고체입자가 잔존되게 하도록 적절한 값으로 결정한다.Thereafter, the laser is irradiated to the entire surface to melt the amorphous silicon layer 21. In this case, the energy of the laser is completely melted in consideration of the thickness of the channel region 21C and the non-channel region 21A of the amorphous silicon layer 21, and the non-channel region 21A is partially. Determine appropriate values to allow solid particles to remain.
도 2B를 참조하면, 레이저 조사 결과, 채널영역(21C)은 얇기 때문에 레이저 에너지를 흡수하여 완전히 용융된 상태가 된다. 채널영역(21C)에 비해 두껍게 형성된 비채널영역(21A)은 채널영역(21C)만이 용융된 상태가 되도록 적당한 에너지 크기를 가지는 레이저를 조사하였기 때문에 부분적으로 용융되지 않아서 고체입자(21s)가 잔존하게 되는 상태로 남아 있게 된다.Referring to Fig. 2B, as a result of laser irradiation, the channel region 21C is thin, so that it absorbs laser energy and is in a completely molten state. Since the non-channel region 21A formed thicker than the channel region 21C is irradiated with a laser having a suitable energy size so that only the channel region 21C is in a molten state, the non-channel region 21A is not partially melted so that the solid particles 21s remain. Will remain.
도 2C를 참조하면, 용융된 비정질 실리콘층(21)은 점진적으로 고화 혹은 냉각되어 결정성장이 이루어진다. 비채널영역(21A)에 용융되지 않고 잔존하는 고체입자(21s)는 이 과정에서 씨드로 작용하게 되어 결정성장을 진행한다. 즉, 잔존하는 각 고체입자(21s)는 씨드로 작용하게 되어 각기 결정성장을 하게 되고, 동시에 여러 곳에서 많은 결정이 생성 및 성장하게 된다. 그결과 성장된 많은 결정들이 서로 엉키게 되어 다결정질을 이룬다. 이때 채널영역(21C)은 고화 또는 냉각되는 속도가 비채널영역(21A)에 비해 아주 작기 때문에 여전히 용융된 상태로 있게 된다.Referring to FIG. 2C, the molten amorphous silicon layer 21 is gradually solidified or cooled to achieve crystal growth. The solid particles 21s that remain without melting in the non-channel region 21A act as seeds in this process and proceed with crystal growth. In other words, each of the remaining solid particles 21s acts as a seed to grow crystals, respectively, and many crystals are produced and grown at various places at the same time. As a result, many grown crystals become entangled with each other and are polycrystalline. At this time, the channel region 21C is still in a molten state because the rate of solidification or cooling is very small compared to the non-channel region 21A.
도 2D를 참조하면, 채널영역(21C)에서 형성되는 다결정질이 아직 용융상태로 존재하는 채널영역(21C)에 다다르게 되면, 채널영역(21A)의 경계가 되는 부분에서 다결정질의 바운더리(21L)가 새로운 씨드로 작용하게 되어 바운더리 래터럴 성장(boundary lateral growth)이 이루어진다.Referring to FIG. 2D, when the polycrystalline formed in the channel region 21C reaches the channel region 21C which is still present in the molten state, the polycrystalline boundary 21L is formed at the portion that becomes the boundary of the channel region 21A. It acts as a new seed, resulting in boundary lateral growth.
이와 같이 하여 결정성장이 끝나면, 채널영역에서는 입자의 크기가 큰 결정질을 얻을 수 있고, 결정입자의 바운더리 수를 줄일 수 있어서, 그레인 바운더리 효과를 억제할 수 있다. 따라서 이와 같은 입자의 이동도가 큰 채널영역을 형성할 수 있는 것이다. 이후, 이렇게 결정화된 실리콘층에 사진식각공정을 진행하여 박막트랜지스터의 활성층을 형성한다.In this way, when the crystal growth is completed, crystal grains having a large particle size can be obtained in the channel region, and the number of boundaries of the crystal grains can be reduced, so that the grain boundary effect can be suppressed. Therefore, a channel region having such a high mobility of particles can be formed. Thereafter, a photolithography process is performed on the crystallized silicon layer to form an active layer of the thin film transistor.
도 3A부터 도 3C는 본 발명의 제 1 실시예에 의하여 형성한 다결정화된 실리콘층을 이용하여 박막트랜지스터를 제조하는 공정을 설명하기 위한 도면이다.3A to 3C are views for explaining a process of manufacturing a thin film transistor using the polycrystalline silicon layer formed according to the first embodiment of the present invention.
도 3A를 참조하면, 상술한 바와 같이 본 발명의 제 1 실시예에 의하여 얻은 다결정화된 실리콘층(도 2D에 보임)에 사진식각공정을 실시하여 활성층(21')을 형성한다.Referring to FIG. 3A, as described above, the active layer 21 'is formed by performing a photolithography process on the polycrystalline silicon layer (shown in FIG. 2D) obtained in accordance with the first embodiment of the present invention.
도 3B를 참조하면, 활성층상(21')에 제 1 절연막(22)과 제 1 도전층을 연속적으로 형성한 후, 제 1 도전층에 사진식각공정을 진행하여 게이트전극(23)을 형성한다. 이후, 전면에 이온도핑공정을 실시하여 활성층(21')의 비채널영역(21A)에 소오스영역(21S)와 드레인영역(21D)을 형성한다.Referring to FIG. 3B, after the first insulating layer 22 and the first conductive layer are successively formed on the active layer 21 ′, the gate electrode 23 is formed by performing a photolithography process on the first conductive layer. . Thereafter, an ion doping process is performed on the entire surface to form the source region 21S and the drain region 21D in the non-channel region 21A of the active layer 21 '.
도 3C를 참조하면, 노출된 전면에 제 2 절연막(24)을 형성한 후, 제 2 절연막(24)에 사진식각공정을 실시하여 소오스영역(21S)과 드레인영역(21D)을 노출하는 콘택홀을 형성한다. 이후, 전면에 제 2 도전층을 형성한 후, 제 2 도전층에 사진식각공정을 실시하여 소오스전극(25S)과 드레인전극(25D)을 형성한다.Referring to FIG. 3C, after forming the second insulating film 24 on the exposed entire surface, the second insulating film 24 is subjected to a photolithography process to expose the source region 21S and the drain region 21D. To form. Subsequently, after the second conductive layer is formed on the entire surface, a photolithography process is performed on the second conductive layer to form the source electrode 25S and the drain electrode 25D.
이와 같이 하여 제조된 박막트랜지스터는 결정입자가 큰 채널영역을 활성층의 일부로 사용함으로써, 캐리어의 이동도를 높일 수 있다.The thin film transistor manufactured in this way can increase the mobility of the carrier by using a channel region having large crystal grains as part of the active layer.
도 4A부터 도 4E는 본 발명에 따른 비정질 실리콘층의 결정화 방법의 제 2 실시예를 나타낸 도면이다. 박막트랜지스터의 활성층이 될 부분을 미리 사진 식각공정에 의하여 형성한 후, 결정화공정을 실시한 것이다.4A to 4E illustrate a second embodiment of a method for crystallizing an amorphous silicon layer according to the present invention. After forming the portion to be the active layer of the thin film transistor by a photolithography process in advance, a crystallization process is performed.
도 4A를 참조하면, 유리기판(40)에 산화실리콘 혹은 질화실리콘과 같은 절연물질을 화학기상증착방법에 의하여 증착하여 완충막(49)을 형성한다. 완충막(49)은 비정질 실리콘층을 결정화하는 공정에서, 유리기판의 불순물이 비정질 실리콘층에 침투하는 것을 방지하기 위하여 형성한다.Referring to FIG. 4A, an insulating material such as silicon oxide or silicon nitride is deposited on the glass substrate 40 by chemical vapor deposition to form a buffer film 49. In the process of crystallizing the amorphous silicon layer, the buffer film 49 is formed to prevent impurities from the glass substrate from penetrating into the amorphous silicon layer.
도 4B를 참조하면, 완충막(49)상에 비정질 실리콘층을 형성한 후, 비정질 실리콘층에 사진식각공정을 실시하여 활성층(41)을 형성한다. 이후, 활성층(41)의 채널영역(41C)으로 정의된 부분이 비채널영역(41A)으로 정의된 부분 보다 얇은 두께를 가지도록 형성한다. 이는 막의 두께에 따른 레이저 에너지의 흡수정도의 함수관계를 이용한 것으로, 레이저 조사시, 채널영역(41C) 완전히 용융시키고, 비채널영역(41A)을 부분적으로 용융시켜서 입자를 잔존시키게 하기 위한 것이다. 이를 위하여 활성층(41)에 채널영역이 정의된 패턴마스크를 이용한 사진식각공정을 실시하여 활성층(41)의 채널영역(41C)이 되는 부분에 트렌치를 형성한다.Referring to FIG. 4B, after the amorphous silicon layer is formed on the buffer layer 49, the active layer 41 is formed by performing a photolithography process on the amorphous silicon layer. Thereafter, the portion defined by the channel region 41C of the active layer 41 is formed to have a thickness smaller than the portion defined by the non-channel region 41A. This is to use the functional relationship of the degree of absorption of the laser energy in accordance with the thickness of the film, to completely melt the channel region 41C and partially melt the non-channel region 41A during laser irradiation, so that the particles remain. To this end, a photolithography process using a pattern mask in which a channel region is defined in the active layer 41 is performed to form a trench in a portion of the active layer 41 that becomes the channel region 41C.
그런데, 이러한 공정들은 완충막(49)상에 비정질 실리콘층을 형성한 후, 채널영역(41C)이 되는 부분에 트렌치를 형성한 다음, 비정질 실리콘층에 사진식각공정을 실시하여 활성층(41)을 형성하는 순으로 공정진행순서를 바꿀 수도 있다.However, in these processes, an amorphous silicon layer is formed on the buffer layer 49, a trench is formed in a portion of the channel region 41C, and a photolithography process is performed on the amorphous silicon layer to form the active layer 41. You can also change the process order in the order they are formed.
이후, 활성층(41)을 용융시키기 위하여 레이저를 전면에 조사한다. 이때 레이저의 에너지 크기는 채널영역(41C)과 비채널영역(41A)의 두께를 고려하여 채널영역(41C)은 완전히 용융되게 하고, 비채널영역(41A)은 부분적으로 고체입자가 잔존하도록 적절한 값으로 결정한다.Subsequently, a laser is irradiated to the entire surface to melt the active layer 41. At this time, the energy level of the laser allows the channel region 41C to be completely melted in consideration of the thickness of the channel region 41C and the non-channel region 41A, and the non-channel region 41A is an appropriate value to partially retain solid particles. Decide on
도 4C를 참조하면, 레이저 조사 결과, 채널영역(41C)은 얇기 때문에 레이저 에너지를 흡수하여 완전히 용융된 상태가 된다. 채널영역(41C)에 비해 두껍게 형성된 비채널영역(41A)은 채널영역(41C)만이 용융된 상태가 되도록 적당한 에너지 크기를 가지는 레이저를 조사하였기 때문에 부분적으로 용융되지 않아서 고체입자(41s)가 잔존하는 상태가 된다.Referring to Fig. 4C, as a result of laser irradiation, the channel region 41C is thin, so that it absorbs laser energy and is in a completely molten state. The non-channel region 41A, which is thicker than the channel region 41C, is irradiated with a laser having a suitable energy size so that only the channel region 41C is in a molten state. It becomes a state.
도 4D를 참조하면, 용융된 활성층(41)은 점진적으로 고화 혹은 냉각되어 결정성장이 이루어진다. 비채널영역(41A)에 용융되지 않고 잔존하는 고체입자(41s)는 이 과정에서 씨드로 작용하게 되어 결정성장을 진행한다. 즉, 잔존하는 각 고체입자(41s)는 씨드로 작용하게 되어 각기 결정성장을 하게 되고, 동시에 여러 곳에서 많은 결정이 생성 및 성장한다. 그 결과 성장된 많은 결정들이 서로 엉키게 되어 다결정질을 이룬다. 이때 채널영역(41C)은 고화 또는 냉각되는 속도가 비채널영역(41A)에 비해 아주 작기 때문에 여전히 용융된 상태이다.Referring to FIG. 4D, the molten active layer 41 is gradually solidified or cooled to achieve crystal growth. The solid particles 41s remaining unmelted in the non-channel region 41A act as seeds in this process to proceed with crystal growth. In other words, each of the remaining solid particles 41s acts as a seed to grow crystals, respectively, and many crystals are produced and grown in various places at the same time. As a result, many grown crystals become entangled with one another and are polycrystalline. At this time, the channel region 41C is still molten because the rate of solidification or cooling is very small compared to the non-channel region 41A.
도 2E를 참조하면, 채널영역(41C)에서 형성되는 다결정질이 아직 용융상태로 존재하는 채널영역(41C)에 다다르게 되면, 채널영역(41A)의 경계가 되는 부분에서 다결정질의 바운더리(41L)가 새로운 씨드로 작용하게 되어 바운더리 래터럴 성장(boundary lateral growth)이 이루어진다.Referring to FIG. 2E, when the polycrystalline formed in the channel region 41C reaches the channel region 41C which is still in the molten state, the polycrystalline boundary 41L is formed at the portion that becomes the boundary of the channel region 41A. It acts as a new seed, resulting in boundary lateral growth.
이와 같이 하여 결정성장이 끝나면, 채널영역에서는 입자의 크기가 큰 결정질을 얻을 수 있어서, 결정입자의 바운더리 수를 줄일 수 있어서, 그레인 바운더리 효과를 억제할 수 있다. 따라서 이와 같은 입자의 이동도가 큰 채널영역을 형성할 수 있는 것이다. 이후, 이렇게 결정화된 활성층을 이용하여 박막트랜지스터를 형성한다.In this way, when the crystal growth is completed, crystal grains having a large particle size can be obtained in the channel region, so that the number of boundaries of the crystal grains can be reduced, and the grain boundary effect can be suppressed. Therefore, a channel region having such a high mobility of particles can be formed. Thereafter, a thin film transistor is formed using the crystallized active layer.
본 발명의 제 2 실시예에서 얻은 결과는 본 발명의 제 1 실시예에서 얻은 결과와 비교하여 완충막 형성만을 제외하고는 같다. 그러나 도 5에 보인 바와 같이, 본 발명의 제 1 실시예에서 공정초기에 완충막(29)을 형성하고 이후의 공정을 실시하면 같은 결과를 얻을 수 있다.The results obtained in the second embodiment of the present invention are the same except for buffer film formation as compared with the results obtained in the first embodiment of the present invention. However, as shown in FIG. 5, in the first embodiment of the present invention, the same result can be obtained by forming the buffer film 29 at the beginning of the process and performing the subsequent process.
도 6은 본 발명의 제 2 실시예에 의하여 형성한 다결정화된 실리콘층을 이용하여 제조된 박막트랜지스터의 단면을 나타낸다.6 is a cross-sectional view of a thin film transistor manufactured using the polycrystalline silicon layer formed by the second embodiment of the present invention.
제조공정은 도 3A부터 도 3C를 참조하여 상술한 바와 같으므로 그 설명은 생략한다.Since the manufacturing process is as described above with reference to Figs. 3A to 3C, the description thereof will be omitted.
도면에서, 40은 절연기판, 41S는 소오스영역, 41D는 드레인영역, 41C는 채널영역, 42는 게이트절연막, 43은 게이트전극, 44는 층간절연막, 45S는 소오스전극 및 45D는 드레인전극을 나타낸다.In the figure, 40 is an insulating substrate, 41S is a source region, 41D is a drain region, 41C is a channel region, 42 is a gate insulating film, 43 is a gate electrode, 44 is an interlayer insulating film, 45S is a source electrode and 45D is a drain electrode.
상술한 바와 같이, 본 발명은 비정질 실리콘층의 채널영역을 결정화시키는 과정에서, 캡핑층을 사용하지 않고 비정질 실리콘층의 두께조절에 의하여 결정화공정을 실시한다. 따라서 레이저 조사시, 캡핑층의 손상으로 인하여 야기되는 채널영역의 손상을 염려할 필요가 없다. 그 결과 결정입자의 크기가 크고 결정입자의 바운더리수를 줄이도록 채널영역을 형성하는 결정화공정을 채널영역의 손상없이 진행할 수 있어서, 박막트랜지스터의 신뢰성을 향상시킬 수 있다.As described above, the present invention performs a crystallization process by controlling the thickness of the amorphous silicon layer without using a capping layer in the process of crystallizing the channel region of the amorphous silicon layer. Therefore, during laser irradiation, there is no need to worry about damage to the channel region caused by damage of the capping layer. As a result, the crystallization process of forming the channel region so that the crystal grain size is large and the boundary number of the crystal grain is reduced can be performed without damaging the channel region, thereby improving the reliability of the thin film transistor.
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970018243A KR100234894B1 (en) | 1997-05-12 | 1997-05-12 | Crystalizing method of amorphous silicon layer and method of fabricating thin film transistor using the same |
| FR9804558A FR2766613B1 (en) | 1997-05-12 | 1998-04-10 | PROCESS FOR CRYSTALLIZING AMORPHOUS SILICON LAYER AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR |
| GB9808250A GB2325342B (en) | 1997-05-12 | 1998-04-17 | Method of crystallizing amorphous silicon layer and method of fabricating a thin film transistor |
| JP11065898A JP4203141B2 (en) | 1997-05-12 | 1998-04-21 | Method for crystallizing amorphous silicon layer and method for producing thin film transistor using the same |
| DE19820441A DE19820441A1 (en) | 1997-05-12 | 1998-05-07 | Method for crystallizing an amorphous silicon layer and manufacturing method for a thin film transistor |
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| KR1019970018243A KR100234894B1 (en) | 1997-05-12 | 1997-05-12 | Crystalizing method of amorphous silicon layer and method of fabricating thin film transistor using the same |
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| KR (1) | KR100234894B1 (en) |
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| KR100380141B1 (en) * | 2000-09-25 | 2003-04-11 | 엘지.필립스 엘시디 주식회사 | array panel for liquid crystal display and fabricating method of the same |
| KR100486676B1 (en) * | 2002-10-04 | 2005-05-03 | 엘지.필립스 엘시디 주식회사 | Phase Shift Laser Mask and sequential lateral solidification Crystallization Method using by the same |
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| DE19802131B4 (en) * | 1998-01-21 | 2007-03-15 | Robert Bosch Gmbh | Process for producing a monocrystalline layer of a conductive or semiconductive material |
| SE514645C2 (en) | 1998-10-06 | 2001-03-26 | Perstorp Flooring Ab | Floor covering material comprising disc-shaped floor elements intended to be joined by separate joint profiles |
| DE29911462U1 (en) | 1999-07-02 | 1999-11-18 | Akzenta Paneele & Profile Gmbh | Fastening system for panels |
| SE518184C2 (en) | 2000-03-31 | 2002-09-03 | Perstorp Flooring Ab | Floor covering material comprising disc-shaped floor elements which are joined together by means of interconnecting means |
| JP4501859B2 (en) * | 2003-06-27 | 2010-07-14 | 日本電気株式会社 | Thin film transistor, thin film transistor substrate, electronic device, and method for manufacturing polycrystalline semiconductor thin film |
| JP4973698B2 (en) * | 2009-06-30 | 2012-07-11 | カシオ計算機株式会社 | THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR |
| KR101116093B1 (en) | 2009-06-26 | 2012-02-21 | 가시오게산키 가부시키가이샤 | Semiconductor device and fabrication method thereof and display device |
| DE102010004717A1 (en) | 2010-01-15 | 2011-07-21 | Pergo (Europe) Ab | Set of panels comprising retaining profiles with a separate clip and method for introducing the clip |
| CA2906474C (en) | 2010-05-10 | 2018-12-18 | Pergo (Europe) Ab | Set of panels |
| CN103325688A (en) * | 2013-06-17 | 2013-09-25 | 深圳市华星光电技术有限公司 | Method for forming channel of thin film transistor and compensating circuit |
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- 1998-04-10 FR FR9804558A patent/FR2766613B1/en not_active Expired - Lifetime
- 1998-04-17 GB GB9808250A patent/GB2325342B/en not_active Expired - Lifetime
- 1998-04-21 JP JP11065898A patent/JP4203141B2/en not_active Expired - Lifetime
- 1998-05-07 DE DE19820441A patent/DE19820441A1/en not_active Ceased
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100380141B1 (en) * | 2000-09-25 | 2003-04-11 | 엘지.필립스 엘시디 주식회사 | array panel for liquid crystal display and fabricating method of the same |
| US7057675B2 (en) | 2000-09-25 | 2006-06-06 | Lg.Phillips Lcd Co., Ltd. | Liquid crystal display device and the fabricating method thereof comprising pixel electrode completely covering adjacent gate line and adjacent channel region unconnected to the pixel electrode |
| KR100486676B1 (en) * | 2002-10-04 | 2005-05-03 | 엘지.필립스 엘시디 주식회사 | Phase Shift Laser Mask and sequential lateral solidification Crystallization Method using by the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2325342A (en) | 1998-11-18 |
| FR2766613B1 (en) | 2003-01-17 |
| JPH10321870A (en) | 1998-12-04 |
| GB2325342B (en) | 2000-03-01 |
| FR2766613A1 (en) | 1999-01-29 |
| KR100234894B1 (en) | 1999-12-15 |
| JP4203141B2 (en) | 2008-12-24 |
| GB9808250D0 (en) | 1998-06-17 |
| DE19820441A1 (en) | 1998-11-19 |
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