KR19980082255A - Flash memory device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, and more particularly, to a flash memory device suitable for forming a floating gate and a control gate in a vertical structure on a substrate, and a method of manufacturing the same. A plurality of second conductivity type first impurity regions formed in one direction at intervals, a plurality of field oxide films formed in a matrix form at a predetermined interval on the first impurity region, and adjacent first impurities among the field oxide films A first conductive semiconductor layer in which a plurality of pairs are formed in a pillar shape on the semiconductor substrate between the regions, a plurality of floating gates formed on side surfaces of the pair of first conductive semiconductor layers, and perpendicular to the first impurity region A plurality of control gate lines formed to surround the floating gates in the same direction And a plurality of second conductive second impurity regions formed in the top portions of the first conductive semiconductor layer, and a plurality of metal lines connected to the second impurity regions on the same line in a direction perpendicular to the control gate line. It is characterized by.

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory devices, and more particularly, to a flash memory device suitable for forming a floating gate and a control gate in a vertical structure with respect to a substrate, and a manufacturing method thereof.

In general, memory devices are classified into read only memory (ROM) and random access memory (RAM).

The ROM includes a mask ROM for inputting and programming program data into a mask in a manufacturing process, and a PROM (Programmable ROM) for manufacturing and mounting a chip and then electrically programming the chip.

The PROM is further classified into an EPROM (Erasble ROM) capable of erasing input data using ultraviolet rays and an EEPROM (Electrkcally Erassable PROM) capable of electrically erasing input data.

The EEPROM is divided into a three-layer gate type flash memory element capable of electrically erasing input data by forming an erase gate and a two layer gate type flash memory element that emits an electric field on the source side.

Hereinafter, a conventional flash memory device and a method of manufacturing the same will be described with reference to the accompanying drawings.

1 is a layout view of a conventional flash memory device, Figure 2 is a perspective view of a conventional flash memory device. 3A is a cross-sectional view taken along the line II of FIG. 1, and FIG. 3B is a cross-sectional view taken along the line II-II of FIG. 1.

That is, in the conventional flash memory device, a plurality of first impurity regions 6b are formed in one direction at predetermined intervals in the surface of the p-type first semiconductor substrate 1.

A plurality of pillar-shaped second semiconductor substrates 2a are formed in the matrix form on the first semiconductor substrate 1 so as to overlap each of the first impurity regions 6b.

A tunneling insulating film 4a is formed on the surfaces of the first and second semiconductor substrates 1 and 2a, and a plurality of floating gates 5a are formed on the tunneling insulating film 4a on the side surface of the second semiconductor substrate 2a. Is formed. At this time, each floating gate 5a is formed lower than the second semiconductor substrate 2a and is formed to surround the second semiconductor substrate 2a.

A plurality of control gates are formed on the surface of each floating gate 5a to surround the plurality of floating gates 5a on the same line in a direction perpendicular to the first impurity region 6b. Line 8 is formed. At this time, the height of the control gate line 8 is also formed as the height of the floating gate 5a, and the second impurity region 6a is formed in the top portion of each second semiconductor substrate 2a.

A planarization insulating film 9 is formed on the entire surface of the first semiconductor substrate 1 with a contact hole in the second impurity region 6a, and at regular intervals in a direction perpendicular to the control gate line 8. A plurality of metal lines 11 are formed on the planarization insulating film 9. In this case, the metal line 11 is used as a bit line and is connected to the second impurity region 6a in the same direction.

The manufacturing method of a conventional flash memory device having such a structure is as follows.

4A to 4G are cross-sectional views illustrating a manufacturing method according to line I-I of FIG. 1, and FIGS. 5A to 5G are cross-sectional views illustrating a manufacturing method according to line II-II of FIG. 1.

As shown in FIGS. 4A and 5A, the first polysilicon layer 2 and the first insulating film 3 are sequentially formed on the p-type first semiconductor substrate 1. In this case, a nitride film is used as the first insulating film 3.

After depositing the first photoresist PR1 on the first insulating layer 3 and defining a portion to be a channel portion, the pattern is selectively patterned, and then using the patterned first photoresist PR1 as a mask. 1 The insulating film 3 is selectively etched.

4B and 5B, the LOCOS oxide film 4 is formed on the exposed surface of the first polysilicon layer 2 using the first insulating film 3 as a mask by a thermal oxidation process. After that, the remaining first insulating film 3 is removed.

In addition, the first polysilicon layer 2 is selectively removed through a dry etching process using the LOCOS oxide film 4 as a mask to form a pillar-shaped second layer in a direction perpendicular to the first semiconductor substrate 1. The semiconductor substrate 2a is formed. At this time, when the first polysilicon layer 2 is etched using the LOCOS oxide film 4 as a mask, the LOCOS oxide film 4 is also etched to become very thin.

Subsequently, as shown in FIGS. 4C and 5C, a tunneling insulating film 4a is formed on the surface of the first semiconductor substrate 1 including the second semiconductor substrate 2a, and a floating gate is formed on the tunneling insulating film 4a. After the second polysilicon layer 5 to be used is formed, impurity ions are implanted for the conductivity of the second polysilicon layer 5.

At this time, the tunneling insulating film 4a is formed by thermally oxidizing the surfaces of the first and second semiconductor substrates 1 and 2a.

Subsequently, as shown in FIGS. 4D and 5D, the second polysilicon layer 5 is etched back to expose the second semiconductor substrate 2a by using a dry etching process. The floating gate 5a is formed around it. At this time, the second polysilicon layer 5 is overetched so that the floating gate 5a is formed lower than the second semiconductor substrate 2a.

In order to form an impurity region in only one direction with a predetermined interval between the second semiconductor substrates 2a, a second semiconductor substrate is formed between the second semiconductor substrates 2a as shown in FIG. 4D. After forming the second photoresist PR2 mask to expose the top portion of (2a), the first semiconductor substrate 1 is formed by implanting impurity ions using the second photoresist PR2 as a mask. A source region 6b is formed in the drain region, and a drain region 6a is formed in the second semiconductor substrate 2a.

In addition, an oxide film (not shown) naturally formed on the surfaces of the first and second semiconductor substrates 1 and 2a is removed.

Subsequently, as shown in FIGS. 4E and 5E, after removing the second photoresist PR2, a second insulating film 7 is formed on the floating gate 5a, and a second insulating film 7 is formed on the second insulating film 7. After depositing the 3 polysilicon layer, a control gate line 8 is formed on the floating gate 5a using a dry etching process in an etch apparatus without a photo process.

In this case, the second insulating layer 7 uses ONO, and the height of the control gate line 8 is also formed as the height of the floating gate 5a and is used as a word line. The floating gate 5a and the control gate line 8 are formed in a direction perpendicular to the first semiconductor substrate 1.

Subsequently, as shown in FIGS. 4F and 5F, the planarization insulating film 9 is formed on the first and second semiconductor substrates 1 and 2a including the control gate line 8. The third photoresist PR3 is deposited on 9), and then selectively patterned using an exposure and development process. The contact hole 10 is exposed to selectively expose the drain region 6a of the second semiconductor substrate 2a by selectively removing the planarization insulating layer 9 using the patterned third photoresist PR3 as a mask. Form.

Subsequently, as illustrated in FIGS. 4G and 5G, a metal is deposited on the planarization insulating film 9 including the contact hole 10, and the metal line on the second semiconductor substrate 2a is etched using an etching process. 11) form. In this case, the metal line 11 is used as a bit line and is connected to the drain region 6a.

Herein, the operation of the conventional flash memory device will be described.

That is, the programming method of the flash memory device is programmed by hot electron injection in the upper portion of the pillar-shaped second semiconductor substrate 2a, and the erasing method is a tunneling method in which electrons flow from the floating gate 5a to the source region 6b. Is done.

As described above, the conventional flash memory device and the manufacturing method thereof have the following problems.

Floating gates and control gate lines surrounding the pillar-shaped second semiconductor substrate have a large loss of effective area in the device configuration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the flash memory device suitable for improving the integration of the device by separating the floating gate and the control gate line surrounding the pillar-shaped semiconductor substrate and the pillar-shaped semiconductor substrate and its manufacturing method The purpose is to provide.

1 is a layout view of a conventional flash memory device

2 is a perspective view of a conventional flash memory device

3A is a cross-sectional view taken along the line I-I of FIG.

3B is a cross-sectional view taken along the line II-II of FIG.

4A to 4G are cross-sectional views illustrating a manufacturing method according to line I-I of FIG.

5A to 5G are cross-sectional views illustrating a manufacturing method according to line II-II of FIG. 1.

6 is a layout view of the flash memory device of the present invention.

7 is a perspective view of a flash memory device of the present invention;

8A is a cross-sectional view taken along the line I-I of FIG. 6

8B is a cross-sectional view taken along the line II-II of FIG. 6.

FIG. 8C is a cross-sectional view taken along the line III-III of FIG. 6

9A to 9H are cross-sectional views illustrating a manufacturing method according to line II of FIG. 6.

10A to 10H are cross-sectional views illustrating a manufacturing method according to line II-II of FIG. 6.

11A to 11H are cross-sectional views illustrating a manufacturing method according to line III-III of FIG. 6.

12 is a perspective view showing another embodiment of the present invention

13A to 13H are cross-sectional views illustrating another embodiment of the present invention.

* Explanation of symbols for main parts of drawings *

30: first semiconductor substrate 31a: source region

31b: drain region 32: field oxide film

33: first polysilicon layer 33a, 33b: second semiconductor substrate

34: first insulating film 36: locos oxide film

37 tunneling insulating film 38 second polysilicon layer

38a, 38b: floating gate 39: second insulating film

40, 40a: control gate line 41: first photoresist line

42 second photoresist 43 third photoresist sidewall

44: insulating film for planarization 45: metal line

The flash memory device of the present invention for achieving the above object is a plurality of second conductivity type first impurity regions formed in one direction with a predetermined interval in the surface of the first conductivity type semiconductor substrate, and on the first impurity region A plurality of field oxide films having a predetermined interval and formed in a matrix form, and a first conductivity type semiconductor layer in which a plurality of pairs are formed in a pillar shape on the semiconductor substrate between adjacent first impurity regions among the field oxide films, wherein each pair of A plurality of floating gates formed on side surfaces of the first conductivity type semiconductor layer, a plurality of control gate lines formed to surround collinear floating gates in a direction perpendicular to the first impurity region, and each of the first conductivity type semiconductors Second impurity regions formed in the top portion of the layer, and a direction perpendicular to the control gate line And a plurality of metal lines connected to the second impurity region on the same line. The method of manufacturing a flash memory device of the present invention includes preparing a first conductivity type semiconductor substrate, and having a predetermined interval within the surface of the semiconductor substrate. Forming a plurality of second conductivity type first impurity regions in one direction, forming a plurality of field oxide films in a matrix form at predetermined intervals on the first impurity region, and adjacent adjacent ones of the field oxide films Forming a plurality of first conductive semiconductor layers in a matrix form on the semiconductor substrate between the second conductive impurity regions, and forming a tunneling insulating layer on the surfaces of the first conductive semiconductor substrate and the first conductive semiconductor layer Forming a plurality of floating gates on each side of the semiconductor layer so as to be lower than a plurality of semiconductor layers; Forming a plurality of second conductivity type second impurity regions in the top portion of the semiconductor layer, forming a dielectric film on each floating gate, and covering the floating gate in a direction perpendicular to the first impurity region. Forming a control gate line, removing a central portion of each of the first conductive semiconductor layer, the floating gate, and the control gate line in a length direction of each of the control gate lines, thereby doubling the cells; Forming a contact hole to expose the second conductivity type second impurity region, and forming a plurality of metal lines to be connected to the second impurity region in a direction perpendicular to the control gate line. It features.

Hereinafter, a flash memory device and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

6 is a layout view of a flash memory device of the present invention, Figure 7 is a perspective view showing a flash memory device of the present invention. FIG. 8A is a cross-sectional view taken along line II of FIG. 6, FIG. 8B is a cross-sectional view taken along line II-II of FIG. 6, and FIG. 8C is a cross-sectional view taken along line III-III of FIG. 6.

That is, in the flash memory device of the present invention, a plurality of first impurity regions 31a are formed in one direction at predetermined intervals on the surface of the p-type first semiconductor substrate 30, and on the first impurity region 31a. A plurality of field oxide films 32 are formed in a matrix form at regular intervals.

A plurality of pillar-shaped second semiconductor substrates 33b are formed so as to be perpendicular to the first semiconductor substrate 30 on the field oxide film 32 so as to overlap the first impurity region 31a. At this time, two second semiconductor substrates 33b overlap each of the field oxide films 32.

A tunneling insulating film 37 is formed on the surfaces of the first and second semiconductor substrates 30 and 33b, and a plurality of floating gates 38b are formed on the tunneling insulating film 37 on the side surface of the second semiconductor substrate 33b. Is formed. In this case, each floating gate 38b is formed lower than the second semiconductor substrate 33b and is formed to surround the second semiconductor substrate 33b.

A second insulating film 39 is formed on the surface of each floating gate 38b, and a plurality of control gate lines are formed to surround the plurality of floating gates 38b on the same line in a direction perpendicular to the first impurity region 31a. 40a is formed. At this time, the height of the control gate line 40a is also formed as the height of the floating gate 38b, and the second impurity region 31b is formed at the top of each second semiconductor substrate 33b.

A planarization insulating film 44 is formed on the entire surface of the first and second semiconductor substrates 30 and 33b with a contact hole in the second impurity region 31b, and is perpendicular to the control gate line 40a. A plurality of metal lines 45 are formed on the planarization insulating film 44 at regular intervals. In this case, the metal line 45 is used as a bit line and is connected to the second impurity region 31b in the same direction.

A method of manufacturing the flash memory device of the present invention having such a structure is as follows.

9A to 9H are cross-sectional views illustrating a manufacturing method according to line I-I of FIG. 6, and FIGS. 10A to 10H are cross-sectional views illustrating a manufacturing method according to line II-II of FIG. 6. 11h is a process sectional view showing the manufacturing method along line III-III of FIG. 6.

As shown in FIGS. 9A, 10A, and 11A, a plurality of source regions 31a having a predetermined interval in one direction are formed in the p-type first semiconductor substrate 30 through impurity ion implantation, and the source regions 31a are formed. ), A plurality of field oxide films 32 having a predetermined interval are formed.

Subsequently, as shown in FIGS. 9B, 10B, and 11B, the first polysilicon layer 33 and the first insulating layer 34 are sequentially formed on the first semiconductor substrate 30 including the field oxide film 32. . In this case, a nitride film is used as the first insulating film 34.

After depositing the first photoresist PR1 on the first insulating layer 34 and defining a portion to be a channel portion, the pattern is selectively patterned, and then using the patterned first photoresist PR1 as a mask. The first insulating film 34 is selectively removed.

Next, as illustrated in FIGS. 9C, 10C, and 11C, the LOCOS oxide film 36 is formed on the exposed surface of the first polysilicon layer 33 by using the first insulating film 34 as a mask by a thermal oxidation process. .

After removing the remaining first insulating layer 34, the first polysilicon layer 33 is selectively removed through an etching process using the LOCOS oxide layer 36 as a mask to form the first semiconductor substrate ( A columnar second semiconductor substrate 33a is formed in a direction perpendicular to 30. In this case, the second semiconductor substrate 33a overlaps the field oxide layer 32.

Subsequently, as shown in FIGS. 9D, 10D, and 11D, a tunneling insulating film 37 is formed on the surfaces of the first and second semiconductor substrates 30 and 33a using a thermal oxidation process, and the tunneling insulating film ( A second polysilicon layer 38 is formed on 37 to be used as the floating gate. In this case, impurity ions are implanted into the second polysilicon layer 38 for conductivity.

Subsequently, as shown in FIGS. 9E, 10E, and 11E, the second polysilicon layer 38 is etched back to expose the second semiconductor substrate 33a by using a dry etching process. After the floating gate 38a is formed around the 33a, the impurity region is formed only in the top portion of the second semiconductor substrate 33a, as shown in FIGS. 10e and 11e, between the second semiconductor substrate 33a. The second photoresist PR2 is formed to expose the top portion of the second semiconductor substrate 33a. A drain region 31b is formed in the second semiconductor substrate 33a by implanting impurity ions using the second photoresist PR2 as a mask.

In this case, the second polysilicon layer 38 is overetched so that the floating gate 38a is formed lower than the second semiconductor substrate 33a.

The oxide films (not shown) that are naturally formed on the surfaces of the first and second semiconductor substrates 30 and 33a are removed.

9F, 10F, and 11F, the second photoresist PR2 is removed, a second insulating film 39 is formed on the floating gate 38a, and the second insulating film 39 is formed. After depositing a third polysilicon layer on the control gate line, the control gate line 40 is formed on the floating gate 38a using a dry etching process in an etch apparatus without a photo process. In this case, the second insulating layer 39 uses ONO, the control gate line 40 is used as a word line, and the height of the control gate line 40 is also formed at the height of the floating gate 38a.

A third photoresist is deposited on the entire surface including the control gate line 40, and a third photoresist line 41 is formed between the control gate lines 40 using an etch back process. In this case, the height of the third photoresist line 41 is also formed at the height of the control gate line 40.

Subsequently, as shown in FIGS. 9G, 10G, and 11G, a fourth photoresist is deposited on the entire surface including the third photoresist line 41, and then, on the third photoresist line 41 using a photolithography process. And a fourth photoresist line 42 so as to span the second semiconductor substrate 33a.

After depositing a fifth photoresist on the side of the fourth photoresist line 42 and forming a fifth photoresist sidewall 43 on the side of the fourth photoresist line 42 using an etch back process, The tunneling insulating layer 37, the second semiconductor substrate 33a, the floating gate 38a, and the control gate line 40 are etched by using the fifth photoresist sidewall 43 as a mask, respectively. The second semiconductor substrate 33b, the floating gate 38b, and the control gate line 40a are formed.

Subsequently, as shown in FIGS. 9H, 10H, and 11H, the remaining third and fourth photoresist lines 41 and 42 and the fifth photoresist sidewall 43 are removed, and then the first semiconductor substrate ( 30 and a planarization insulating film 44 are formed on each of the second semiconductor substrates 33b.

The planarization insulating layer 44 is etched to expose the drain region 31b of each of the second semiconductor substrates 33b by using a photolithography process to form a contact hole, and then planarization including the contact hole. A metal is deposited on the insulating film 44 and a metal line 45 is formed on each of the second semiconductor substrates 33b using an etching process. In this case, the metal line 45 is used as a bit line and is connected to the drain region 31b.

12 is a perspective view showing another embodiment of the present invention.

That is, a plurality of first impurity regions 31a are formed in the surface of the p-type first semiconductor substrate 30 in one direction at predetermined intervals, and have a predetermined interval on the first impurity region 31a in a matrix form. A plurality of field oxide films 32 are formed.

A plurality of pillar-shaped second semiconductor substrates 33a are formed in a form perpendicular to the first semiconductor substrate 30 on the field oxide film 32 so as to overlap the first impurity region 31a.

A tunneling insulating film 37 is formed on the surfaces of the first and second semiconductor substrates 30 and 33a, and a plurality of floating gates 38b are formed on the tunneling insulating film 37 on the side surface of the second semiconductor substrate 33a. Is formed. In this case, the floating gate 38b overlaps the two floating gates 38b on the respective field oxide layers 32, and each floating gate 38b is formed lower than the second semiconductor substrate 33a and the second semiconductor. It is formed to surround the substrate 33a.

A second insulating film 39 is formed on the surface of each floating gate 38b, and a plurality of control gate lines are formed to surround the plurality of floating gates 38b on the same line in a direction perpendicular to the first impurity region 31a. 40a is formed. At this time, the height of the control gate line 40a is also formed as the height of the floating gate 38b, and the second impurity region 31b is formed at the top of each second semiconductor substrate 33a.

A planarization insulating film 44 is formed on the entire surface of the first and second semiconductor substrates 30 and 30a with a contact hole in the second impurity region 31b, and is perpendicular to the control gate line 40a. A plurality of metal lines 45 are formed on the planarization insulating film 44 at regular intervals. In this case, the metal line 45 is used as a bit line and is connected to the second impurity region 31b in the same direction.

Thus, the manufacturing method of another embodiment of the present invention having the structure is as follows.

13A to 13H are cross-sectional views illustrating a method of manufacturing another embodiment of the present invention.

13A to 13F are the same as those of FIGS. 10A to 10F.

Subsequently, as shown in FIG. 13G, a fourth photoresist is deposited on the entire surface including the third photoresist line 41 and on the third photoresist line 41 and the second semiconductor substrate using a photolithography process. A fourth photoresist line 42 is formed to span 33a).

After depositing a fifth photoresist on the side of the fourth photoresist line 42 and forming a fifth photoresist sidewall 43 on the side of the fourth photoresist line 42 using an etch back process, Using the fifth photoresist sidewall 43 as a mask, the tunneling insulating layer 37, the floating gate 38a, and the control gate line 40 are etched to control the tunneling insulating layer 37a and the floating gate 38b, respectively. The gate line 40a is formed.

Subsequently, as shown in FIG. 13H, the remaining third and fourth photoresist lines 41 and 42 and the fifth photoresist sidewall 43 are removed, and then the first and second semiconductor substrates 30 ( The planarization insulating film 44 is formed on 33a).

Then, the planarization insulating film 44 is etched to expose the drain region 31b of the second semiconductor substrate 33a by using a photolithography process to deposit a metal on the planarization insulating film 44, and the etching process is performed. Metal lines 45 are formed on the respective second semiconductor substrates 33b. In this case, the metal line 45 is used as a bit line and is connected to the drain region 31b.

Herein, the operation of the flash memory device of the present invention will be described.

Programmed by hot electron injection in the second semiconductor substrate, the erase method is a tunneling method in which electrons flow from the floating gate to the source region, thereby increasing the degree of integration and doubling the speed.

As described above, the flash memory device of the present invention and the manufacturing method thereof have the following effects.

First, since the photoresist is used to form each floating gate and control gate, the size can be formed below the minimum of the lithography resolution, and the process can be simplified because no additional process is required when removing the photoresist. have.

Second, since the control gate and the floating gate are formed separately, the integration degree of the cell area can be improved.

Third, the number of bits that can be accessed is increased due to the increase of the number of cells twice.

Claims (10)

A plurality of second conductivity type first impurity regions formed in one direction at regular intervals in the surface of the first conductivity type semiconductor substrate; A plurality of field oxide films formed in a matrix form on the first impurity region at predetermined intervals; A first conductivity type semiconductor layer in which a plurality of pairs are formed in a pillar shape on the semiconductor substrate between adjacent first impurity regions among the field oxide films; A plurality of floating gates formed on side surfaces of the pair of first conductive semiconductor layers; A plurality of control gate lines formed to enclose collinear floating gates in a direction perpendicular to the first impurity region; Second conductive second impurity regions formed in the top portions of the first conductive semiconductor layer; And a plurality of metal lines connected to the second impurity region on the same line in a direction perpendicular to the control gate line. The method of claim 1, The height of each of the floating gate and the control gate line is formed lower than the second semiconductor substrate. The method of claim 1, And a tunneling insulating film is further formed between the semiconductor substrate and the first conductive semiconductor layer and the floating gate, and a dielectric film is further formed between the floating gate and the control gate line. The method of claim 1, And the floating gate is formed on side surfaces of the semiconductor substrate except for a pair of semiconductor layers. Preparing a first conductivity type semiconductor substrate; Forming a plurality of second conductivity type first impurity regions in one direction at predetermined intervals in the surface of the semiconductor substrate; Forming a plurality of field oxide films in a matrix form at predetermined intervals on the first impurity region; Forming a plurality of first conductive semiconductor layers in a matrix form on a semiconductor substrate between adjacent second conductive first impurity regions among the field oxide films; Forming a tunneling insulating layer on surfaces of the first conductive semiconductor substrate and the first conductive semiconductor layer; Forming a plurality of floating gates on the side surfaces of the semiconductor layers so as to be lower than the plurality of semiconductor layers; Forming a plurality of second conductivity type second impurity regions in the top portion of the semiconductor layer; Forming a dielectric film on each floating gate, and forming a plurality of control gate lines to surround the floating gate in a direction perpendicular to the first impurity region; Doubling the cells by removing center portions of the first conductive semiconductor layer, the floating gate, and the control gate line in the length direction of each control gate line; Forming a planarization insulating film on the entire surface, and forming a contact hole to expose the second conductivity type second impurity region; And forming a plurality of metal lines to be connected to the second impurity region in a direction perpendicular to the control gate line. The method of claim 5, Wherein each of the semiconductor layers is formed such that both corner portions thereof overlap with the adjacent field oxide layer. The method of claim 5, The tunneling insulating film is a method of manufacturing a flash memory device, characterized in that formed using a thermal oxidation process. The method of claim 5, And the floating gate and the control gate line are formed lower than the second semiconductor substrate. The method of claim 5, In the step of doubling the cell, Forming a first photoresist on said floating gate and control gate line; Forming a plurality of second photoresist lines to overlap the control gate lines on the first photoresist; Forming a third photoresist sidewall on the side of the second photoresist line; And removing a center portion of the first conductive semiconductor layer, the floating gate, and the control gate line using the third photoresist sidewall as a mask. Preparing a first conductivity type semiconductor substrate; Forming a plurality of second conductivity type first impurity regions in one direction at a predetermined interval within the surface of the first conductivity type semiconductor substrate; Forming a plurality of field oxide films in a matrix form on the first impurity region; Forming a plurality of first conductive semiconductor layers in a matrix form on the semiconductor substrate between adjacent second conductive first impurity regions among the field oxide films; Forming a tunneling insulating layer on surfaces of the first conductive semiconductor substrate and the first conductive semiconductor layer; Forming a plurality of floating gates on the side surfaces of the semiconductor layers so as to be lower than the semiconductor layers; Forming a plurality of second conductivity type second impurity regions in each top portion of the semiconductor layer; Forming a dielectric film on the floating gate and forming a plurality of control gate lines to surround the floating gate in a direction perpendicular to the first impurity region; Doubling the cell by removing a center portion of each floating gate and a control gate line in a length direction of each control gate line; Forming a planarization insulating film on the entire surface of the semiconductor layer, and forming contact holes to expose each of the second conductivity type second impurity regions; And forming a plurality of metal lines to be connected to the second impurity region in a direction perpendicular to the control gate line.