KR19980080540A - Redundant semiconductor memory with flexibility in fuse placement - Google Patents

Abstract

Disclosed are a semiconductor memory having a main memory cell array and a redundant memory cell using a plurality of fuses that can be physically branched from an associated fuse latch. Physical separation is possible by implementing a serial transfer circuit for serially transferring fuse data from the fuse to the latch. As a result, only a small number of wires are required to connect the fuse to the fuse latch, allowing flexible fuse placement in the memory.

Description

Redundant semiconductor memory with flexibility in fuse placement

TECHNICAL FIELD The present invention relates to semiconductor memories, and more particularly to semiconductor memories such as dynamic random access memories (DRAMs) having redundancy memory cells and fuses for storing defective memory cell address data.

As the density and complexity of current random access memory (RAM) increases, it has become difficult to fabricate a flawless RAM in a memory cell array. Thus, in order to increase the yield of such a device, part of the memory cell array is designed as a redundant memory part. Each time it is determined that the input address corresponds to a defective portion of the main memory, the memory cells of the redundancy memory are accessed. ON-CHIP type logic circuits are used to store defective main memory addresses and facilitate the writing and reading of data into redundant memories. This logic circuit includes a plurality of fuse groups, each fuse in the fuse group being open or shorted to indicate a logic state. Each fuse group thus forms a logical word corresponding to the address of the cell or cell group that has a coupling in the main memory.

Referring to FIG. 1, a simplified block diagram of an integrated circuit 10 of a conventional DRAM is shown. DRAM 10 includes DRAM memory block 12 having M × N memory cells 15 forming M rows (R ₁ -R _M ) times N columns (C ₁ -C _N ). Although only one memory block 12 and associated circuitry are shown in FIG. 1, there are generally many memory blocks fabricated on a single DRAM chip. Within each M × N array, K redundancy columns (C _NJ -C _N ) (J = K-1) and Z redundancy columns (R _MY -R _M ) (Y = Z-1) are designed for redundancy memory do. The row decoder logic circuit 13 decodes the parallel row address input signal RA to enable one or more rows R ₁ -R _MZ corresponding to the row addresses. Similarly, one or more columns C ₁ -C _N are enabled by column decoder logic 11 in response to column address input CA. Data is written to or read from a specific memory cell or cells 15 enabled by row decoder 13 and column decoder 11. Data flows in the direction controlled by the write / read signal R / W through the bit line BL connected to each cell.

Column and row fuse banks 18 and 18 'each include a plurality of fuse groups, each of which stores a column or row address corresponding to a defective column or row. Each fuse is a laser meltable link and is covered by a uniform dielectric layer, such as silicon dioxide. After DRAM fabrication, a test is performed on the memory array to determine which rows and / or columns contain cells with bonds. The address is then written to the fuse group by laser destruction of the optional fuse link to form an electrical open state. Each fuse group contains about 10 fuses to store row or column addresses.

When power is supplied to the DRAM chip, the fuse information in the column or row fuse banks is written to the respective column and row fuse latches 16 and 16 'as parallel data. The fuse latch is written during the chip operation by the relevant column and row fuse decoders 14 and 14 '. The column address CA, which is input to the column decoder logic circuit 11, is actively provided to the column fuse decoder 14 which compares the address with those stored in the fuse latch 16. If matched, the column decoder logic 11 does not enable the column select line SCL _i corresponding to the address. Instead, the thermal fuse decoder 14 enables a particular one of the column select lines SCL _NJ -SCL _N to activate the redundancy column for data storage. The row fuse decoder 14 ′ operates in a similar fashion with the row decoder logic circuit 13 to enable any redundancy row select lines RSL _MY -RSL _M.

Figure 2 shows the practical architecture of a conventional DRAM chip, such as a 64M chip. Four 16M memory blocks 12a-12d are disposed in area 20, each area having respective decoder / fuse decoders 24a-24d adjacent to each memory block in the center area therebetween. Each decoder / fuse decoder 24a-24d, hereafter decoder 24a-24d, is a column associated with the column fuse logic circuit 11 associated with the column fuse decoder 14 and / or the row associated with the row fuse decoder 14 ′ described above. Decoder logic circuit 13 is included. Fuse latches 26a-26d and fuse banks 28a-28d are located adjacent to separate decoders 24a-24d. Typically, a DRAM contains thousands of fuses, each of which is connected to an associated fuse latch. As such, the fuse bank is placed in the vicinity of the fuse latch and fuse decoding logic circuitry to minimize the necessary wiring. The remaining circuits, such as the timing and control logic circuits 31a and 31b and the address buffer 41, are located in regions 30a and 30b away from the memory block, for example.

The type of packaging technology often used in DRAM chips is known as Leadframe On Chip (LOC) technology, where the leadframe is bonded to the chip surface using LOC tape means. The lead frame is an internal electrical component of the chip that supports the connection of conductive leads or terminals. The LOC tape acts not only as a physical connection between the chip and the leadframe, but also as a soft buffer when the bonding wire is connected to the tip of the lead. Bonding is only allowed on the lead region supported by the tape.

As shown in FIG. 2, LOC tape 32 extends across DRAM 10 and overlays two memory blocks 12a and 12b. A row of electrical contact pads 34 is disposed at the midpoint of the top and bottom of the layout. The bonding wires 23 electrically connect the contact pads 34 to the leads 33. The circuit connection to the contact pad 34 includes an address input line, that is, an R / W line or the like. The placement of the LOC tape 32 is limited by the fuse bank for reasons of reliability. Since the LOC tape attracts moisture, an unprotected fuse area should be considered when the tape is very close to the fuse. As a result, the LOC tape 32 must be cut to prevent it from extending above the fuse bank. General tape design rules require a tape break of at least one millimeter. This reduction in the overall tape length results in a smaller lead pitch. Reduced read pitch is a problem for memory where a large number of leads must be accommodated in small die sizes such as 64M DRAM designed based on 0.25 [mu] m technology. For example, using a chip length of 10mm, a 1mm tape brake reduces lead pitch by about 10%.

Instead of cutting the LOC tape, the fuse can be hypothetically transferred to another area of the chip, such as areas 30a and 30b. In order to perform parallel fuse cut data transfer, moving a fuse to one of the areas 30a, 30b or anywhere on the chip requires a very large number of connecting wires to connect the fuse to the fuse latch. Alternatively, the fuse can in principle be moved together with the fuse latch and decoder logic circuitry; However, it also incurs a price for a very expensive large number of connection wires or speeds. Accordingly, prior art architectures place limited fuses in the vicinity of the associated latch and decoder logic circuits, and there is only limited flexibility in moving the fuses.

Thus, there is a need for a memory architecture that avoids the need to cut LOC tapes with associated shrinkage in the lead pitch and does not use overly complex wiring devices.

1 is a block diagram of a DRAM cell integrated circuit of the prior art;

2 shows a DRAM layout of the prior art;

3 illustrates a memory architecture in accordance with the present invention.

4 schematically illustrates a serial data transfer circuit for transferring fuse data to a fuse patch.

5 is a timing diagram illustrating the flow of various signals in the circuit of FIG.

6 illustrates timing signals for performing fuse latch refresh at low power consumption;

* Explanation of symbols for main parts of drawings *

10: DRAM 11: column decoder logic circuit

12: memory block 13: row decoder logic circuit

14, 14 ': column and row fuse decoder 15: memory cell

16, 16 ': column and row fuse latch 18, 18': column and row fuse bank

31a, 31b, 58a, 58b: timing and control logic

32: LOC tape

100, 200: serial data transmission circuit

The present invention relates to a semiconductor memory having a redundancy memory cell and a main memory cell array having a plurality of fuses which can be physically separated from the associated fuse latches. Physical separation is possible by specifying a serial transmission circuit that serially transfers fuse data from the fuse to the latch. As a result, only a small number of wires are required to connect the fuse to the fuse latch, allowing for flexible fuse placement in the memory.

In an exemplary embodiment, the fuses are arranged in a fuse group for storing address information, each fuse being in an open or shorted state corresponding to a bit of an address of at least one defective cell in the main memory cell array. The fuse latch stores address information received from the fuse during operation of the semiconductor memory in order to easily store data in the redundancy cell in place of the defective cell in the main memory. The serial transmission circuit serially transmits at least a portion of the address information from the fuse toward the latch. Thus, a small number of bus lines can be used to simultaneously transmit fuse data from a small number of corresponding fuses in a sequential manner. Preferably, reading of the sequential fuse data does not cause as many power surges as in the prior art where all fuse data are transmitted in parallel at the same time.

The serial transfer circuit includes a first shift register adjacent a fuse bank, a second shift register adjacent a fuse latch, and timing and control logic circuits coupled with respective shift registers for synchronizing transfer of fuse data to the latch. do. Using this configuration, fuse latch refresh can be performed through low power consumption. This shift register can be modified as a ring shift register for this purpose.

The semiconductor memory may be DRAM using LOC packaging. Preferably, since the fuse bank can be moved away from the main memory cell array, the LOC tape can extend continuously across the memory without cutting. As a result, the lead pitch can be increased over prior art designs.

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described with reference to the drawings, in which like elements are denoted by like reference numerals.

Example

The present invention relates to a memory device having redundancy memory cells. The present invention provides increased flexibility in the placement of fuses used to store the addresses of defective memory cells in a memory array. As discussed above, this increased flexibility facilitates the design and manufacture of high density memory devices. For purposes of explanation, the present invention will be described with respect to a DRAM chip. However, the present invention has a wider application. By way of example only, the present invention provides an alternative method of using a fuse or other bit storage element to store the address of a defective memory cell such as EDO-DRAM, SDRAM, RAMBUS-DRAM, SLDRAM, MDRAM or SRAM. It also includes applications in memory devices.

Referring to Fig. 3, a substantial architecture of a semiconductor memory according to the present invention is schematically shown. As shown, the memory 50 is, for example, a DRAM. The memory 50 is an improvement over the memory 10 described above in that at least a portion of the fuse bank is removed from the area in the center of the chip between the memory blocks 12a-12d. Fuse banks 28a and 28b may be moved to partial regions within region 30a, which may be unused silicon regions. As a result, the LOC tape 32 is allowed to extend continuously across the chip, thereby making it possible to increase the lead pitch. Since the lead 33 is connected to a part of the middle of the LOC tape for the wire bonding connection to the contact pads centered at the same marks 34 and 34 ', an increase in the lead pitch is possible. In addition, the memory 50 uses serial data transfer between the fuse banks and their individual fuse latches, thereby minimizing wiring between the fuses and the fuse latches.

In the illustrated embodiment, the lower fuse banks 28c and 28d retain their previous positions adjacent to the fuse latches 26c and 26d, respectively. Optionally, such fuse banks can also be moved away from the fuse latches. In general, the present invention allows for high fluidity in fuse placement, thus allowing flexibility in the layout of other circuits on the chip.

Physical separation of the fuse banks 28a and 28b from the fuse latches 26a and 26b associated with the fuse bank is achieved by using a serial data transfer circuit (SDTC) 10. In one embodiment, the SDTC 10 comprises a parallel / serial converter (P / S converters 52a, 52b), a serial / parallel converter (S / P converters 54a, 54b) and associated timing and control logic circuits. 58 is included on the chip. (As used herein, parallel / serial conversion means that data is generated on parallel lines and transmitted as serial data on a reduced number of lines. Similarly, parallel / serial conversion is serial on one or more lines. Means that the data is transmitted as parallel data on a large number of lines.) The serial / parallel converters 54a, 54b are adjacent to individual fuse latches 26a, 26b within the space previously occupied by the fuse bank. Is located. The address corresponding to the defective memory cell location is stored in the fuse bank, and each fuse stores one bit of address. For example, the fuses may be arranged in a fuse group of about ten fuses for storing column or row addresses. While applying power to the chip, fuse data is transferred to parallel / serial converters 52a and 52b on parallel lines. Preferably, this transmission is performed sequentially as described below. A bus 59 consisting of n bus lines connects each P / S converter with a separate S / P converter. Bus 59 transmits data from the P / S converter to the S / P converter in series. The S / P converter then transfers data on parallel lines to adjacent fuse latches for storage. Each sequential transmission contains information from n fuses. As such, as the number n decreases, the number of transfers required to transfer information from all fuses to the latch increases. For example, in the extreme case where n equals 1, each serial transmission contains information from a single fuse. By reducing the transfer time required to store information from all the fuses to the latch, although a large number improves performance, this is accomplished using additional wiring costs. Thus, in the selection of the number of serial bit lines 59, there is a balance of speed versus wiring complexity.

In theory, n may be chosen to be 1 ≦ n ≦ G, where G is equal to the number of fuses in the fuse bank. However, in order to improve the efficiency of the transmission, n should be chosen such that G is a multiple of it. In addition, the upper limit of n should be G / 2. In one embodiment, n is selected such that 1 ≦ n ≦ G / 2.

In general, fuse data is transmitted during the power up process of the main chip. Since the power up process is generally slow, n can be kept reasonably low to reduce wiring and reduce the chip area used. Preferably n is selected within the range of 4 to 10 bus lines. During the time spent for general powering up, this number of bus lines is generally sufficient to serially transfer address data stored in thousands of fuses, such as a particular 64M DRAM.

Another advantage of using serial data transfer between fuses and fuse latches of memory 50 is the reduction of power surges during fuse read operations. In the prior art, in order to transfer the fuse data to the fuse latch, the fuse latch is generally switched at the same time, so that a power surge occurs. Since only a small number of latches are active at any given time, the serial transmission technique prevents such power surges.

Other characteristics of the memory 50 are the same or similar to those signed with reference to the memory 10 shown in FIGS. 1 and 2. For example, decoders 24a-24d compare the input address with addresses stored in corresponding fuse latches 26a-26d. When matched with the input address and the address of a defective row or column, each decoder 24a-24d applies an appropriate voltage on the column select line or row select line, thereby causing associated memory blocks 12a-12d. Activate a redundancy row or column (or a portion of a row or column therein).

4 shows a schematic block diagram of an exemplary SDTC 10. The SDTC is implemented to serially transfer fuse data from the fuse bank 28 to the fuse latch 26. Empirically, the fuse bank consists of G fuses F ₁ -F _G. The fuse latch bank also consists of _G latches L ₁ -L _G corresponding to the fuses F ₁ -F _G. The SDTC transfers the information from the fuse F _i to the corresponding latch L _i , where i belongs to 1 to G. A data bus 59 consisting of n bus lines makes it possible to serially transfer information from n fuses to n corresponding latches. As such, complete transfer of all fuse information to the fuse latch requires G / n transfers.

The shift register SR ₁ and the switch sets S ₁ -S _G work together to perform the parallel / serial conversion function. Each switch (S _i) is coupled to a corresponding fuse (F _i), where i belongs to from 1 to G. For example, the switch is a FET. Timing and control logic (TCL) 58a and 58b individually control shift registers SR ₁ and SR _2. As shown, the TCL inputs a power-on signal. And generate a signal set_1, a reset signal, and a clock CLK, for example, the clock CLK may be coupled to a system clock or to a separate clock that generates CLK. As a matter of fact, the TCL 58b can be synchronized with the TCL 58a by receiving the CLK signal from the TCL 58a. The shift register SR ₁ is configured to receive the fuse information in response to the output of the TCL 58a. Initialize the serial transfer to the latch.

The shift register contains, for example, G / n bits corresponding to the number of transfers required to store all fuse information in the fuse latch. Each bit of shift register SR ₁ is coupled to n switches. The switches in any group are not connected to the other bits of the shift register SR ₁ . In addition, the switches in the group each connect their fuses to only one of the n bus lines. When the TCL initiates a serial transfer of fuse information from the fuse bank to the fuse latch bank, the shift register SR ₁ activates a unique group of switches using each clock cycle so that the information from the associated fuses is on the bus. To be sent to.

Shift register SR ₂ operates in conjunction with latch bank 26 to perform a serial / parallel conversion function. In one embodiment, the shift register SR ₂ is the same as the shift register SR ₁ . Shift register SR ₂ responds to the output of TCL 58b. As shown, individual TCLs are used to control the shift registers SR ₁ , SR ₂ . Alternatively, a common TCL is used to control both shift registers. Each bit of shift register SR ₂ activates a group of n latches to store information from the data bus. The latches in any group are not connected to the other bits of the shift register SR ₂ . In addition, the latches in the group store information from only one of the n bus lines. When the TCL initiates a serial transfer of fuse information from the fuse bank to the fuse latch, the shift register SR ₂ uses each clock cycle to activate a unique group of latches, and information from the associated fuses on the bus is stored in the latch. Be sure to

One bit of the shift register corresponds to a register cell. As shown, the shift registers SR ₁ , SR ₂ include G / n shift register cells ((C ₁ -C _{G / n} ) and (C ₁ '-C _{G / n} '), respectively. In one embodiment, each shift register C ₁ , C ′ ₁ (except for the last cell C _{G / n} , C _{G / n} ') has two flip flops (FF _iA , FF _iB ) or (FF _iA ', FF _iB '), respectively. The output X of the A flip flop of the cell corresponds to the bits of the shift register. As such, the outputs X are each connected to a group of n unique fuses. Each output X 'of the A flip flop is connected to n latch input latch sets of the corresponding group. The outputs X, X 'of the A, A', B, B 'flip-flops are connected to the inputs I, I' of the next upper A, A ', B, B' flip-flops, respectively. As described above, the shift register is a shift right register. That is, using each clock cycle, the data stored therein is shifted one bit to the right. However, other shift registers may also be used. For example, a shift left register or a combination of a shift right register and a shift left register may be used as long as the SDTC is configured to transfer information from each fuse to a corresponding latch. In the example of FIG. 4, n = 4. In this manner, are transmitted to four corresponding latches within a time of four fuses at the same time data bus line (59 ₁ -59 ₄₎ latch bank 26 through.

Operation with respect to the circuit of FIG. 4 is described with reference to the timing diagram of FIG. In operation, when power is first applied to the memory at a time t = t ₀ , a power on pulse is applied to the TCL 58. In response, the TCL generates a reset signal to reset all the flip flops in the shift registers SR ₁ and SR ₂ to have an output of logic zero. Then at time t ₁ , clock 63 in TCL 58 starts generating a clock pulse provided to each flip flop in shift register SR ₁ , SR ₂ to perform the data shift function. . For example, in synchronization with the leading edge of the first clock pulse, a pulse set_1 is generated. Empirically, pulse set_1 is an active high (logical 1) pulse. The use of active low (logical 0) pulses is also useful. In an embodiment, the width of pulse set_1 is slightly longer than the width of the clock pulse. The length of pulse set_1 is sufficiently longer than a clock pulse so that the set is locked in the shift register. For example, if pulse set_1 goes low (inactive) before the clock pulse goes low, the set pulse in the shift register is lost. Prior to the next clock pulse, pulse set_1 is deactivated. A pulse set_1 is applied to both data input ports I _1A and I _1A ′ of each of the outermost flip flops FF _1A and FF _1A ′. Incidentally, logic 1 of pulse set_1 is transmitted to outputs X _1A and X _1A ′ at time t ₁ . At the trailing edge (time t ₂ ) of the first clock pulse, logic 1 is applied to the output ports X _1B and X _1B ′ of each flip flop FF _1B and FF _1B ′. The pulse set_1 then drops to logic 0 at time t ₃ before the next clock pulse is set, and remains logic 0 for the rest of the data shift operation.

The output line X _1A of the flip flop FF _1aA is connected to the gate of the FETs S ₁ to S _n (in this embodiment, S _n = S ₄ ). As such, when logic 1 of pulse set_1 is transferred to outputs X _1A and X _1A ′ at time t ₁ , FETs S _1- S ₄ are switched on. On the other hand, since the other flip flops (FF _2A , FF _{G / 4A} ') were previously reset, their outputs are all zero so that the other switches S ₅ -S _G are all off. Thus, as is separately transmitted in a time (t ₁₎ and the next clock leading edge (the time (t ₄₎₎ only the fuse data only and the bus line (58 ₁ -59 ₄₎ of the fuse (F ₁ -F ₄₎ in between the pulses . When any given fuse F _i remains (unchanged), logic 0 is sent to the relevant line 59 _i since all the fuses are connected to the ground potential on only one side. When the fuse (F _i) is to be melt-cut, and the high impedance state is provided on the bus lines, and this as an indication of a logical high and is detected by the associated latch circuit (L _i). This condition is detected, for example, if the bus line is precharged to 5 volts (because these voltages are not discharged) or if a weak bleeder circuit is used on the chip. Alternatively, the fuse may be connected to a bus line connected to a voltage source and ground. As such an example, a fuse that has been melted and blown causes logic 0 to be sent, and an unchanged fuse causes logic 1 to be sent.

During the time interval in which the switches S ₁ -S ₄ are shorted, that is, during the time t ₁ -t ₄ , the logic high at the output port X _1A ′ enters the latch set input of the latches L _1- L ₄ . provided in (set). A logic high at the latch set inputs activates the latches makes it possible that, at the same time, whereby the line data is transmitted separately to the latch (L ₁ -L ₄₎ on the (59 ₁ -59 _4).

First clock flip-flop (FF _1B, FF _1B ') at the trailing edge of the pulse has a flip-flop of the pulse (set_1) of the logic high the next stage (FF _2A, FF _2A') each input (I _2A, I _2A ') To serial to. At the leading edge of the second clock pulse (time t ₄ ), the logic high at the inputs I _2A , I _2A ′ is transmitted to the outputs X _2A , X _2A ′, while the inputs I _1A , I _1A ′ are The logic high provided at) is sent to the output (X _1A , X _1A '). This opens the switches S _1- S ₄ , disables the latches L _1- L ₄ , while shorting the switches S _5- S ₈ and outputs their latch set input (X). Enable latches L ₅ -L ₈ (connected to _2A , X _2A '). In this way it is sent to the time (t ₄₎ and the time (t ₆₎ the fuse (F ₅ -F ₈₎ only the fuse data of each fuse latch (L ₅ -L ₈₎ in between. (Time (t ₆₎ is Sequential fuse read and transfer is performed until data from the last set of fuses F _G-3 to F _G is transferred to the corresponding latches L _G-3 to L _G. Continues. (Note that in the embodiment of Fig. 4, the lowest shift register cell C _{G / n} contains only one flip flop FF _{(G / n) A. The} last fuse read is the pulse set_1 Occurs when a logic high is sent to the output of the last flip flop (X _{(G / n) A} ).)

As shown in FIG. 4, each flip flop FF _{i in the} shift registers SR ₁ and SR ₂ is a three-phase buffer inverter 61 having its own input as a flip flop data input port such as input I _1A . ) May be included. The clock signal is applied to an inverter 67 whose output is connected to the enable port of the buffer 61. Each buffer 61a of the A flip flop is enabled at the rising edge of the clock pulse, while each buffer 61b of the B flip flop is enabled at the falling edge of the clock pulse. The other inverter 65 is in series with the inverter 61. The output of the inverter 65 becomes the output X _i of the flip flop. The feedback inverter 63 is connected across the inverter 65. A reset signal is applied to the gate of the FET switch 69. When reset is high. Since the FET 69 driving the output X _i low is turned on, the flip flip is reset. In any case, other configurations for shift register flip flops known to those skilled in the art may also alternatively be used.

Preferably, the circuit arrangement of FIG. 4 has a minimum of only n + 1 wires for forming a path to the associated fuse latch region, i.e. clock wire 61 for synchronizing with n data wires of bus line 59. Requires. This implementation is very efficient and only requires a minimum cost. As such, there is high flexibility at the fuse location. In addition, the shift register layout can be implemented using two metal layers so that the data bus and reset signals can be routed through the register region within the third metal layer. Using n bus lines, the layout, which is not excessively small (eg, in the range of 4 to 6), is essentially controlled by the metal pitch of the read data bus 59.

As mentioned above, a large number of fuses have been involved in conventional DRAM designs. As a result, such a memory that reads all fuses in parallel causes a large amount of power surge. However, reading fuse data in accordance with the present invention contributes to power consumption over a relatively long time interval, thereby avoiding many power surges.

An important problem associated with conventional DRAM is the reliability of fuse data. The detection of power application was very complicated, and detection can occur by accident even though the internal power supply is very low. This may cause invalid fuse data provided to the fuse decoder. In addition, during chip operation, supply voltage bumps (changes) can change the fuse latch data.

Referring to FIG. 6, the serial data transmission circuit 200 is designed to mitigate the above-mentioned problem of fuse data reliability. The circuit 200 is a modification of the circuit 100 of FIG. 4. Flip-flops (FF _{(G / n) B} and FF _{(G / n) B} ') are added to the last shift registers (C _{G / n} and C _{G / n} '), respectively, and outputs (X _{(G / n) B} and By returning X _{(G / n) B} ') to the input ports I _1A and I _1A ' of the respective first flip-flop, the shift registers SR ₁ and SR ₂ become ring shift registers SR ₁ and SR _2. ) Can be modified. When logic 1 of pulse set_1 reaches its last output (X _{(G / n) B} , X _{(G / n) B} '), logic 1 fed back to port (I _1A , I _1A ') is essentially new It operates as a pulse set_1, and the data of the fuses F ₁ -F _G ′ are sequentially transferred to the corresponding latches L ₁ -L _G ′. Accordingly, as long as the clock signal is continuously generated, the fuse latch can be continuously updated using the ring shift register. Alternatively, the clock signal can be selectively stopped to realize a discontinuous update of the fuse latch.

By simple modification of the logic circuits in the logic blocks 58a 'and 58b', it is possible to activate the clock signal CLK during the low cycle of each Row Address Strobe (RAS) signal. This is illustrated in the timing diagram of FIG. On the falling edge of each RAS pulse, the clock signal can be activated for a certain number of pulses. The frequency of the clock can be adjusted to vary the number of clock pulses during each RAS low cycle. Power consumption can be exchanged freely against the RAS cycle required to refresh all fuse latches. For example, full refresh of all fuses is realized after 32 RAS cycles. It should be noted that the fuse refresh depends on the RAS-alternatively on each CAS cycle, or may be a continuous process of time as described above using a ring shift register.

In addition to the modification of the TCL, it is also possible to refresh the fuse latch at an increased rate during a predetermined number, for example eight initial RAS only ROR cycles after chip power up. When a suitable supply voltage (VCC) bump detection circuit (not shown) has an identified VCC bump event, the fuse latch may alternatively be refreshed.

While the foregoing description includes many features, these features are not limited as a limitation of the scope of the present invention, but are merely illustrative of preferred embodiments. Although described with particular reference to, for example, semiconductor memories using fuses, memories using fuses and equivalents may also benefit from the present invention. Although the present invention has been described above in accordance with one preferred embodiment of the present invention, various modifications may be made without departing from the spirit of the present invention as defined by the appended claims. It is obvious to those skilled in the art.

The present invention has a serial transmission circuit for serially transferring fuse data from a fuse to a latch, the main memory cell array having a plurality of fuses and a redundant memory cell that can be physically separated from an associated fuse latch. By forming a semiconductor memory cell, only a small number of wires are required to connect the fuse to the fuse latch, so the number of wires can be reduced and flexibility in fuse placement can be provided.

Claims (22)

A semiconductor memory having a main memory cell array and a redundant memory cell, A plurality of fuses in an open or shorted state corresponding to bits of an address of at least one defective cell in said main memory cell array, for storing address information; A plurality of latches for storing address information stored in the fuse during operation of the semiconductor memory for easily storing data in the redundancy cell in place of a defective cell in the main memory; And And a serial transfer circuit capable of serially transferring at least a portion of said address from said fuse to said latch. 2. The semiconductor memory of claim 1 wherein the semiconductor memory is a dynamic random access memory (DRAM). 2. The semiconductor memory of claim 1 wherein the semiconductor memory is packaged using a leadframe on chip (LOC) packaging technique, and further continuous LOC tape extends across the memory. 4. The semiconductor device of claim 3, further comprising at least first and second main memory cells, wherein the fuse latch is disposed between the first and second memory cell arrays, and the fuse is disposed in the semiconductor memory spaced apart from the fuse latch. Disposed in an area, wherein the LOC tape extends from the first memory cell array to the second memory cell array across the fuse latch. 2. The semiconductor memory of claim 1 wherein a number n of bus lines are used to transfer data in parallel between the fuse and the latch, wherein n is much smaller than the number of fuses. The semiconductor memory of claim 5, wherein n is in a range of 4 to 10. 7. 2. The apparatus of claim 1, wherein the serial transfer circuit comprises a first shift register adjacent to a fuse bank, a second shift register adjacent to the fuse latch, and a respective shift register to synchronize transfer of the address information from the fuse to a corresponding latch. And a combined timing and control logic circuit. 10. The apparatus of claim 7, further comprising a plurality of switches coupled between the fuse and at least one bus line, the switches being sequential by the first shift register to serially transmit fuse data on the bus line. Paragraphs, The plurality of latches are coupled to the at least one bus line, and the second shift register sequentially activates a latch set input of the latch to sequentially transfer the fuse data from the at least one bus line to the latch. And a semiconductor memory. 8. The semiconductor memory according to claim 7, wherein the first and second shift registers are ring shift registers, thereby easily refreshing the fuse latches sequentially. 2. The semiconductor memory of claim 1 wherein the fuse stores a column address of the main memory cell array having defective cells. 2. The semiconductor memory of claim 1 wherein the fuse stores a row address of the main memory cell array having defective cells. 2. The semiconductor memory of claim 1, wherein the main memory cell array and the redundancy memory cell are each part of a common memory block, and the redundancy memory cell is comprised of specific columns and rows of the memory block. 13. The apparatus of claim 12, further comprising a fuse decoder circuit disposed adjacent to the fuse block and the fuse block to enable columns and rows of the redundancy memory whenever an address corresponding to an address stored in the fuse is input. A semiconductor memory, characterized in that. A random access memory (RAM) having a plurality of memory blocks each having a main memory cell array and a redundant memory cell, A plurality of fuse banks each associated with one of the memory blocks and having a plurality of fuses for storing address information, each fuse addressing at least one defective cell in the main memory cell array; Is in a short or open state corresponding to a bit of; A plurality of fuse latches each having a plurality of fuse latches for storing address information stored in one of the fuse banks during operation of the RAM to easily store data in the redundancy memory cell in place of a defective cell in the main memory Fuse latch section; At least one first shift register proximate at least one of the fuse banks; A plurality of switches coupled between at least one bus line and a fuse of one of said fuse banks, said switches being configured by said first shift register to serially transfer said fuse data onto said bus line; Sequentially shorted, the second shift register sequentially activates a latch set input of the latch to sequentially transfer the fuse data from at least one bus line to the latch; And And a logic circuit coupled between the first and second shift registers to synchronize the shift registers with each other and control fuse data transfer timing. 15. The random access memory of claim 14 wherein the random access memory is a dynamic random access memory (DRAM). 15. The random access memory of claim 14 wherein the at least one bus line consists of a plurality (n) of bus lines, where n is much smaller than the number of fuses in the associated fuse bank. A plurality of fuses for storing address information indicating a main memory cell array, a redundant memory cell for storing data on behalf of the defective cell of the main memory, a defective cell or a group of cells having a defective cell; A method for transferring address information from the fuse to the latch in a semiconductor memory having a plurality of fuse latches for storing address information of the fuse during operation of the semiconductor memory. Providing at least one bus line between the plurality of fuses and the plurality of latches; And And transmitting at least a portion of said address information serially through said at least one bus line from said fuse to said latch. 18. The method of claim 17, wherein the at least one bus line consists of a plurality (n) of bus lines, where n is much smaller than a plurality of fuses, such that n fuse data is transferred to the latch at one time. How to. 18. The method of claim 17, further comprising sequentially refreshing the fuse latches. 20. The method of claim 19, wherein the semiconductor memory is a dynamic random access memory, and wherein the refreshing is synchronized with one of a RAS signal and a CAS signal. 20. The method of claim 19, wherein said refreshing is performed based on identification of a particular supply voltage bump event. 20. The method of claim 19, wherein the semiconductor memory is a dynamic random access memory and the refreshing is performed during a time associated with a predetermined number of RAS only refresh (ROR) cycles.