KR19980077553A - Bonded S.O.I wafer manufacturing method - Google Patents
Bonded S.O.I wafer manufacturing method Download PDFInfo
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- KR19980077553A KR19980077553A KR1019970014719A KR19970014719A KR19980077553A KR 19980077553 A KR19980077553 A KR 19980077553A KR 1019970014719 A KR1019970014719 A KR 1019970014719A KR 19970014719 A KR19970014719 A KR 19970014719A KR 19980077553 A KR19980077553 A KR 19980077553A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 235000012431 wafers Nutrition 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000004140 cleaning Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 abstract description 12
- 238000005406 washing Methods 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 239000010419 fine particle Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 229910052710 silicon Inorganic materials 0.000 description 29
- 239000010703 silicon Substances 0.000 description 29
- 239000000243 solution Substances 0.000 description 15
- 238000004381 surface treatment Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 241000252506 Characiformes Species 0.000 description 3
- -1 hydrogen ions Chemical class 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Cleaning Or Drying Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
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Abstract
본 발명은 접합형 SOI 웨이퍼 제조방법에 관한 것으로, SOI 웨이퍼의 접합공정인 피라나용액과 SC-1 용액으로 두개의 웨이퍼를 세정하고 이를 접합한 다음, 열처리하여 접합형 SOI 웨이퍼를 제조하는 방법에 있어서, 상기 SC-1 용액의 농도와 온도를 조절하여, 미세공극의 발생을 억제하기 위해 표면의 친수화 처리, 불순 입자 제거를 웨이퍼의 표면 미세조도에 영향을 주지 않는 방법으로 세정을 실시함으로써 미세공극 발생으로 인한 부작용을 최소한으로 줄여 전체 수율 향상 및 소자의 신뢰도를 증진시킬 수 있는 기술이다.The present invention relates to a method for manufacturing a bonded SOI wafer, and to a method of manufacturing a bonded SOI wafer by cleaning two wafers with a Pirana solution and an SC-1 solution, which are a bonding process of the SOI wafer, and then bonding them, followed by heat treatment. In order to control the concentration and temperature of the SC-1 solution to suppress the generation of micropores, the surface is subjected to a hydrophilic treatment and impurities to remove fine particles by washing in a manner that does not affect the surface fine roughness of the wafer. It is a technology that can improve overall yield and device reliability by minimizing side effects caused by voids.
Description
본 발명은 접합형 에스.오.아이.(silicon on insulator, 이하에서 SOI 라 함) 웨이퍼 제조방법에 관한 것으로, 특히 두 개의 기판을 세정하고 상기 두 개의 기판의 접합 및 열처리 공정 후 결점이 발생되지 않도록 하여 소자의 특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a bonded S.O.I (hereinafter referred to as SOI) wafer, and in particular, to clean two substrates and to eliminate defects after bonding and annealing the two substrates. It relates to a technique for improving the characteristics of the device by avoiding.
현재, 대부분의 반도체는 한 장의 실리콘 웨이퍼 위에 소자를 형성시키는 방법을 채택하고 있는데, 고집적화가 진행되면서 펀치쓰루(punchthrough), 래치업(latchup), 열전자 현상 등과 같은 단점이 대두되어 이를 극복하고자 하는 많은 연구들이 이루어지고 있다.Currently, most semiconductors adopt a method of forming a device on a single silicon wafer, and as the integration becomes high, disadvantages such as punchthrough, latchup, and thermoelectric phenomenon arise, and many of them try to overcome this problem. Research is being done.
그 가운데, 절연막 위에 얇은 실리콘층을 형성하고 상기 실리콘층에 소자를 형성하는 방법인 SOI 기술이 활발히 진행되고 있다.Among them, SOI technology, which is a method of forming a thin silicon layer on an insulating film and forming an element in the silicon layer, is actively progressing.
상기 SOI 웨이퍼를 만드는 방법은, 절연막은 형성시킨 실리콘 웨이퍼에 수소이온을 주입한 다음, 또 다른 실리콘 웨이퍼와 접합하여 후속 열처리 과정을 통해 수소이온 주입 웨이퍼에 이온 주입위치 밑부분이 떨어져 나감으로써 얇은 실리콘층을 형성하는 스마트 컷(Smart-Cut)이라는 방법, 실리콘 웨이퍼위에 다공질의 실리콘층을 형성시키고 그 위에 다결정 실리콘층을 에피탁시얼(epitaxial) 로 형성시킨 다음, 절연막을 형성시킨 실리콘 웨이퍼와 접합한 후, 단결정을 형성시킨 웨이퍼의 실리콘 웨이퍼 전부와 다공질 실리콘층을 연마 및 식각공정으로 제거함으로써 평탄한 실리콘층을 얻는 엘트란(ELTRAN; Epitaxial Layer TRANsfer) 이라는 방법, 실리콘 웨이퍼에 고농도의 산소 이온을 주입한 후 후속 열처리 과정을 통해 실리콘 웨이퍼와 산소이온간의 반응을 통해 웨이퍼 내에 산화막(barriedoxdie)을 형성시켜 그 산화막위의 소자를 만들 수 있는 실리콘층을 만든 사이목스(SIMOX; Separtion by IMplanted OXygen) 방법, 한 장의 실리콘 웨이퍼에 절연막을 형성시키고 또 다른 실리콘 웨이퍼와 접합한 다음, 한 쪽면의 실리콘을 약 0.2㎛ 정도만 남기고 다 제거하여 얇은 실리콘층을 얻는 직접 접합형(Silicon Direct Bonding) SOI 방법 등이 있다.In the method of making the SOI wafer, a thin silicon is formed by injecting hydrogen ions into a silicon wafer on which an insulating film is formed, and then bonding it to another silicon wafer to remove the lower portion of the ion implantation site from the hydrogen ion implanted wafer through subsequent heat treatment. A method called Smart-Cut, which forms a layer, forms a porous silicon layer on a silicon wafer, epitaxially forms a polycrystalline silicon layer thereon, and then bonds the silicon wafer with an insulating film. Then, a method called ELTRAN (Epitaxial Layer TRANsfer), which obtains a flat silicon layer by removing all of the silicon wafer and the porous silicon layer of the single crystal-formed wafer by polishing and etching processes, injects a high concentration of oxygen ions into the silicon wafer. After the subsequent heat treatment, the reaction between silicon wafer and oxygen ion Sepimion by IMplanted OXygen (SIMOX) method, in which a silicon layer is formed on a wafer to form a device on the oxide, and an insulating film is formed on one silicon wafer and bonded to another silicon wafer. Next, there is a silicon direct bonding SOI method in which a thin silicon layer is removed by removing only about 0.2 μm of silicon on one side.
한편, 이온 주입에 의한 방법과 단결정을 성장시키는 방법은 실리콘 웨이퍼에 전위(dislocation) 과 같은 결함 등을 유발하거나 표면의 균일성 등의 문제점들이 나타나는 반면에 직접 접합형 SOI 방법은 결함이 없고 표면의 평탄도가 우수한 실리콘층을 제조할 수 있다는 점에서 이점을 가지고 있다.On the other hand, the method by ion implantation and the method of growing single crystals cause defects such as dislocations or surface uniformity on silicon wafers, whereas problems such as surface uniformity appear. There is an advantage in that a silicon layer having excellent flatness can be produced.
그러나, 이 직접 접합형 SOI 방법은, 접합시 발생할 수 있는 두 웨이퍼 사이에 존재할 수 있는 공극(void) 이 생기지 않도록 해야 하며, 웨이퍼 한 쪽을 거의 제거하는 연마(grinding)와 같은 후속 공정에서도 접합면이 떨어지지 않을 정도의 충분한 접합 강도를 갖도록 해 주어야 한다.However, this direct bonded SOI method must ensure that there are no voids that may exist between the two wafers that may occur during bonding, and that the bonding surface may be used in subsequent processes such as grinding, which almost eliminates one side of the wafer. The bond strength must be sufficient to prevent it from falling.
이를 위해서 접합 전 웨이퍼의 표면 처리를 다음과 같이 한다.To this end, the surface treatment of the wafer before bonding is performed as follows.
먼저, 접합면을 친수성(hydropjilic)으로 만들어 주어야 하며, 공극(void)의 원인이 될 수 있는 유기물질이나 불순입자(particle) 등을 제거해 주어야 하며, 이를 위해 황산(H2SO4)과 순수의 혼합용액을 이용하는 피라나(piranha) 세정, NH3플라즈마, 암모니아수(NH4OH)와 과산화수소(H2O2) 그리고 순수를 혼합한 용액을 이용하는 SC-1 세정과 같은 방법을 이용한다.First, the bonding surface should be made hydropjilic, and organic materials or impurities, which may cause voids, should be removed. For this, sulfuric acid (H 2 SO 4 ) and pure water should be removed. Methods such as piranha washing using a mixed solution, NH 3 plasma, ammonia water (NH 4 OH), hydrogen peroxide (H 2 O 2 ), and SC-1 washing using a pure water solution are used.
그리고, 상기 표면 처리 후, 상기 두 개의 웨이퍼를 접합시키고 후속 열처리를 거쳐 접합 웨이퍼를 형성한다.After the surface treatment, the two wafers are bonded and subjected to a subsequent heat treatment to form a bonded wafer.
이때, 상기 접합 웨이퍼는, 적외선을 이용하여 측정한 경우에 있어서 공극이 검출되지 않는다고 문헌에 보고되어 있다(T.Abe et al., Jpn. J. Appl. Phys. 29, L23111990). 그러나, 소자가 형성될 실리콘층과 소자간의 절연을 담당하고 있는 절연막(주로 산화물) 사이에 초음파에 의해 검출될 수 있는 미세공극(microvoid) 이 존재함으로써 소자 형성 후 소자의 오작동 내지는 불량을 유발하게 된다.At this time, it is reported in the literature that the bonded wafer does not detect voids when measured using infrared rays (T. Abe et al., Jpn. J. Appl. Phys. 29, L23111990). However, microvoids, which can be detected by ultrasonic waves, exist between the silicon layer on which the device is to be formed and the insulating film (mainly oxide) that is insulated between the devices, causing malfunction or failure of the device after the device is formed. .
참고로, 두장의 웨이퍼간의 공극을 조사하는 방법으로 주로 적외선을 이용하는 방법이 있는데, 이 방법은 적외선의 파장보다 작은 공극에 대해서는 검출해낼 수 없어 실제로 작은 미세공극에 대해서는 사용할 수 없다. 이에 반해, 초음파를 이용할 경우에는 적외선을 이용하여 측정했을 때 나타나지 않던 공극까지도 검출해 낼 수 있다. 실제로, 위 표면 처리후 접합한 웨이퍼의 후속 열처리를 행한 접한 웨이퍼에 대해 초음파를 이용해 공극을 조사한 결과 적외선을 이용해 측정했을 때 나타나지 않던 미세공극이 나타남을 알 수 있었다.For reference, a method of irradiating a gap between two wafers mainly uses infrared rays. This method cannot detect pores smaller than the wavelength of infrared rays, and thus cannot be used for small micropores. On the other hand, when using ultrasonic waves, it is possible to detect even voids which did not appear when measured using infrared rays. In fact, when the pores were irradiated with ultrasonic waves on the contacted wafers subjected to the subsequent heat treatment of the bonded wafers after the above surface treatment, it was found that the micropores did not appear when measured with infrared rays.
상기한 바와 같이 종래기술에 따른 접합형 SOI 웨이퍼 제조방법은, 초음파에 의하여 검출될 수 있는 미세공극으로 인하여 소자의 오동작이나 불량을 유발하여 반도체소자의 특성 및 신뢰성을 저하시키고 반도체소자의 수율을 저하시키는 문제점이 있다.As described above, the bonded SOI wafer manufacturing method according to the related art causes malfunction or failure of the device due to micropores that can be detected by ultrasonic waves, thereby degrading the characteristics and reliability of the semiconductor device and lowering the yield of the semiconductor device. There is a problem.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, SC-1세정에 사용되는 용액의 농도와 온도를 조절하여 세정 효과를 극대화함으로써 미세공극의 유발을 억제하는 접합형 SOI 웨이퍼 제조방법을 제공하는데 그 목적이 있다.The present invention provides a bonded SOI wafer manufacturing method that suppresses the occurrence of micropores by maximizing the cleaning effect by adjusting the concentration and temperature of the solution used in the SC-1 cleaning to solve the above problems of the prior art. The purpose is.
이상의 목적을 달성하기 위해 본 발명에 따른 접합형 SOI 웨이퍼 제조방법은, SOI 웨이퍼의 접합공정전 피라나용액과 SC-1 용액으로 두개의 웨이퍼를 세정하고 이를 접합한 다음, 열처리하여 접합형 SOI 웨이퍼를 제조하는 방법에 있어서, 상기 SC-1 용액의 농도와 온도를 조절하여 세정하는 것이다.In order to achieve the above object, the bonded SOI wafer manufacturing method according to the present invention, prior to the bonding process of SOI wafer, two wafers are cleaned with a Pirana solution and an SC-1 solution and bonded, and then heat treated to bond SOI wafer. In the method for preparing, by controlling the concentration and temperature of the SC-1 solution to wash.
이때, 상기 SC-1 용액은 NH4OH:H2O2:H2O의 농도비가 0.25∼1:1:5 인 것과, 상기 세정공정은 25∼45℃ 정도의 온도에서 실시하는 것이다.At this time, the SC-1 solution is a concentration ratio of NH 4 OH: H 2 O 2 : H 2 O is 0.25 to 1: 1: 5, and the washing step is carried out at a temperature of about 25 ~ 45 ℃.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
일반적으로, 미세공극은 접합 방법 등과 같은 외적인 요인 등에 의해서는 영향을 받지만, 주로 웨이퍼 표면에 존재하는 유기 물질, 불순 입자(particle) 등에 의해서 발생하는 것으로 보고되고 있다. 이러한 유기 물질과 불순 입자 등은 웨이퍼의 친수성 처리 또는 병행해야 한다. 그래서 상기의 표면 처리 방법 중, 피라나 세정과 SC-1 세정 방법을 병행하여 유기 물질, 불순 입자 제거하는 동시에 웨이퍼의 표면을 친수성으로 만들어 주되, 표면의 친수화(親水化)와 불순 입자 제거를 담당하는 SC-1 세정 조건의 농도와 온도를 조절함으로써 SC-1 세정의 효과를 극대화하는 것이다.In general, micropores are influenced by external factors such as a bonding method and the like, but are reported to be mainly caused by organic materials, impurities, and the like present on the wafer surface. Such organic substances and impurities should be subjected to hydrophilic treatment or parallel processing of the wafer. Therefore, among the surface treatment methods described above, both the Pirana cleaning and the SC-1 cleaning methods are used to remove organic substances and impurity particles, and to make the surface of the wafer hydrophilic, but to remove the surface hydrophilization and impurities. The effect of SC-1 cleaning is maximized by controlling the concentration and temperature of the responsible SC-1 cleaning conditions.
이하, 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail.
본 발명이 응용되는 공정의 순서를 간단히 설명하면 다음과 같다.The sequence of the process to which the present invention is applied is briefly described as follows.
먼저, 열산화법을 이용해 약 3500Å 정도의 얇은 산화막을 성장시킨 웨이퍼와 실리콘 웨이퍼의 세정을 위해 웨트 스테이션(wet station)에서 피라나 세정과 SC-1 세정을 순차적으로 진행한 다음, 접합 장비를 이용하여 접합한다.First, Pirana cleaning and SC-1 cleaning are sequentially performed at a wet station to clean a wafer and a silicon wafer having a thin oxide film having a thickness of about 3500 kW using a thermal oxidation method. Bond.
이 때, 상기 SC-1 세정은 NH4OH : H2O2: H2O의 농도비가 0.5 : 1 : 5,2 : 1: 5, 0.25:1:5인 용액에 대하여 온도를 다르게 조절하게 진행하였다.At this time, the SC-1 cleaning is to adjust the temperature differently for the solution of the concentration ratio of NH 4 OH: H 2 O 2 : H 2 O is 0.5: 1: 5, 2: 1: 5, 0.25: 1: 5 Proceeded.
그 다음에, 접합면은 수소 결합에 의해 접합이 이루어진 상태이기 때문에 약 1050℃ 정도의 온도와 N2또는 O2분위기에서 약 2시간 정도 후속적인 고온 열처리를 통해 접합 강도를 증진시켜 준다.Next, since the bonding surface is bonded by hydrogen bonding, the bonding strength is enhanced through subsequent high temperature heat treatment at a temperature of about 1050 ° C. and about 2 hours in an N 2 or O 2 atmosphere.
그리고, 상기와 같은 공정으로 형성된 SOI 웨이퍼의 밑부분에서 적외선을 쐬어 주고, 투과된 적외선을 위부분에서 설치된 적외선 카메라를 이용해 공극의 존재 여부를 측정한 후, 비교를 위해 동일한 웨이퍼에 대해 초음파를 이용하여 역시 공극의 존재 여부를 측정하였다.Then, infrared rays are emitted from the bottom of the SOI wafer formed by the above process, and the transmitted infrared rays are measured by using an infrared camera installed at the upper portion, and then ultrasonic waves are used for the same wafer for comparison. The presence of voids was also measured.
여기서, 상기 SC-1의 용액중, NH4OH : H2O2: H2O의 농도비가 0.5 : 1 : 5 인 용액의 온도를 35℃로 유지한 상태에서 세정을 행한 경우와, 85℃로 유지한 상태에서 세정을 행한 경우에 대해 초음파를 이용해 접합면의 공극 존재 여부 측정하였다. 이때, 전자(前者)의 경우는 미세공극이 존재하지 않은 반면에, 후자(後者)의 경우에는 많은 수의 미세공극이 관찰되었다.Here, in the solution of SC-1, washing was carried out while maintaining the temperature of the solution having a concentration ratio of NH 4 OH: H 2 O 2 : H 2 O of 0.5: 1: 5 at 35 ° C, and 85 ° C. About the case where washing | cleaning was performed in the state hold | maintained in the state, the presence of the space | gap of the joint surface was measured using the ultrasonic wave. At this time, in the former case, no micropores existed, whereas in the latter case, a large number of micropores were observed.
이때, 상기 SC-1의 용액을 35℃로 하여 세정하는 경우는, 낮은 온도로 인해 암모니아(NH4OH)에 의해 식각되어 떨어져 나가는 얇은 실리콘층과, 메가소니(megasonic)으로 인해 표면의 불순 입자들이 최종적으로 제거된다.At this time, when washing the solution of SC-1 at 35 ° C., a thin silicon layer etched away by ammonia (NH 4 OH) due to low temperature and impurities on the surface due to megasonic Are finally removed.
그러나, 85℃에서는 암모니아 전자(前者)에 비해 더 많은 실리콘층을 제거함으로써 미세조도(micro-roughness)에 영향을 미치게 되어 접합후 이러한 불균일성으로 인해 미세공극(microvoid)이 생기게 되었다.However, at 85 ° C., the micro-roughness is affected by removing more silicon layers than the former ammonia electrons, resulting in microvoids after bonding.
한편, 상기 미세공극이 불순 입자로 기인한 것이 아님을 증명해 보이기 위하여, 상기 두 경우에 대해서 웨이퍼 표면의 불순 입자의 개수를 측정한 결과, 수 개 정도의 불순 입자만이 관찰되었으며, 그 불순 입자의 위치가 미세공극이 관찰된 웨이퍼의 미세공극 위치와도 일치하지 않는 것으로부터 불순 입자로 인한 미세 공극이 아님을 알 수 있었다.On the other hand, in order to prove that the micropores are not caused by impurity particles, the number of impurity particles on the surface of the wafer was measured in both cases, and only a few impurity particles were observed. From the fact that the position does not coincide with the micropore position of the wafer where the micropores were observed, it was found that they were not micropores due to impurities.
이와 같이 동일한 농도의 용액을 이용하여 세정을 할 때, 온도의 조절을 통해 동일한 시간내에 식각되는 실리콘의 양을 미세조절함으로써 접합후 생성되는 미세공극의 발생을 억제할 수 있다.As such, when cleaning using a solution having the same concentration, it is possible to suppress the generation of micropores generated after bonding by finely controlling the amount of silicon etched within the same time by controlling the temperature.
본 발명은 실리콘 웨이퍼와 SiO2절연막을 성장시킨 웨이퍼간의 접합 뿐만 아니라, 직접 접합형 SOI 웨이퍼의 제조시에 모든 두 웨이퍼간의 접합, 예를들면 실리콘과 실리콘간의 접합, 실리콘과 BPSG 간의 접합, 실리콘과 화학증착산화막 웨이퍼간의 접합시의 표면 처리에 적용될 수 있다.The invention provides not only bonding between a silicon wafer and a wafer on which SiO 2 insulating film is grown, but also bonding between all two wafers in the fabrication of a direct bonded SOI wafer, such as bonding between silicon and silicon, bonding between silicon and BPSG, and It can be applied to the surface treatment at the time of bonding between chemical vapor deposition oxide wafers.
그리고, 상기 세정공정은 피라나용액으로 먼저 실시하고 SC-1 용액을 이용하여 실시하거나, 상기 SC-1 용액을 이용하여 실시하고 피라나용액을 이용하여 실시할 수도 있다.In addition, the washing step may be carried out first using a piranha solution and then using an SC-1 solution, or may be performed using the SC-1 solution and using a piranha solution.
이상에서 설명한 바와 같이 본 발명에 따른 접합형 SOI 웨이퍼 제조방법은, 미세공극의 발생을 억제하기 위해 표면의 친수화 처리, 불순 입자 제거를 웨이퍼의 표면 미세조도에 영향을 주지 않는 방법으로 세정을 실시함으로써 미세공극 발생으로 인한 부작용을 최소한으로 줄여 전체 수율 향상 및 소자의 신뢰도를 증진시킬 수 있는 효과가 있다.As described above, in the bonded SOI wafer manufacturing method according to the present invention, in order to suppress the generation of micropores, surface hydrophilization treatment and impurities removal are performed by a method that does not affect the surface fine roughness of the wafer. As a result, the side effects due to the generation of micropores can be minimized, thereby improving overall yield and reliability of the device.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480490B1 (en) * | 2002-05-15 | 2005-04-06 | 유재언 | Multi bonded wafer void inspection system |
| KR100827471B1 (en) * | 2006-10-27 | 2008-05-06 | 동부일렉트로닉스 주식회사 | Method for manufacturing analog capacitor |
| KR100827907B1 (en) * | 2005-04-19 | 2008-05-07 | 가부시키가이샤 섬코 | Process for cleaning silicon substrate |
| KR101969679B1 (en) * | 2018-07-27 | 2019-04-16 | 한양대학교 산학협력단 | Method for forming and transferring thin film using soi wafer and thermal process |
| CN113555274A (en) * | 2021-07-21 | 2021-10-26 | 江西圆融光电科技有限公司 | Chip cleaning method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP2012347B1 (en) | 2006-04-24 | 2015-03-18 | Shin-Etsu Handotai Co., Ltd. | Method for producing soi wafer |
| US7910455B2 (en) | 2006-04-27 | 2011-03-22 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR950007007A (en) * | 1993-08-13 | 1995-03-21 | 김주용 | Removal Method of Natural Oxide in Semiconductor Device |
| KR0140652B1 (en) * | 1994-12-21 | 1998-07-15 | 김주용 | Cleaning method of semiconducotr substrate |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480490B1 (en) * | 2002-05-15 | 2005-04-06 | 유재언 | Multi bonded wafer void inspection system |
| KR100827907B1 (en) * | 2005-04-19 | 2008-05-07 | 가부시키가이샤 섬코 | Process for cleaning silicon substrate |
| US7534728B2 (en) | 2005-04-19 | 2009-05-19 | Sumco Corporation | Process for cleaning silicon substrate |
| KR100827471B1 (en) * | 2006-10-27 | 2008-05-06 | 동부일렉트로닉스 주식회사 | Method for manufacturing analog capacitor |
| KR101969679B1 (en) * | 2018-07-27 | 2019-04-16 | 한양대학교 산학협력단 | Method for forming and transferring thin film using soi wafer and thermal process |
| US10957538B2 (en) | 2018-07-27 | 2021-03-23 | Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University) | Method of forming and transferring thin film using SOI wafer and heat treatment process |
| CN113555274A (en) * | 2021-07-21 | 2021-10-26 | 江西圆融光电科技有限公司 | Chip cleaning method |
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