JP5865057B2 - Semiconductor substrate recycling method and SOI substrate manufacturing method - Google Patents

Description

The present invention relates to a method for regenerating a semiconductor substrate. The present invention also relates to a method for manufacturing a regenerated semiconductor substrate using the method for regenerating the semiconductor substrate. The present invention also relates to a method for manufacturing an SOI (Silicon on Insulator) substrate.

In recent years, an integrated circuit using an SOI substrate in which a thin single crystal silicon layer is provided on an insulating surface has been developed. By utilizing the characteristics of the thin single crystal silicon layer formed over the insulating surface, the transistors in the integrated circuit can be completely separated from each other. Further, since the transistor can be a fully depleted type, a semiconductor integrated circuit with high added value such as high integration, high speed driving, and low power consumption can be realized.

As one of methods for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known. In the hydrogen ion implantation separation method, a single crystal silicon substrate (bond substrate) into which hydrogen ions are implanted is bonded to another substrate (base substrate) through an insulating layer, and the bond substrate is separated in the ion implantation region by subsequent heat treatment. Thus, a single crystal silicon layer is obtained on the base substrate. By using the hydrogen ion implantation separation method, an SOI substrate having a single crystal silicon layer over an insulating substrate such as a glass substrate can be manufactured (see, for example, Patent Document 1).

In the case where an ion implantation separation method is used as a method for manufacturing an SOI substrate, a plurality of SOI substrates can be manufactured from one bond substrate, so that there is an advantage that the cost of the bond substrate in manufacturing the SOI substrate can be reduced. . This is because a bond substrate after use can be reused for manufacturing an SOI substrate by performing a regeneration process on the bond substrate after the single crystal silicon layer is separated.

JP 2004-87606 A

A bond substrate used for the ion implantation separation method has an edge roll-off (EDRO) region due to a chemical mechanical polishing (CMP) process at the periphery. The region is formed by polishing the edge of the bond substrate with a polishing cloth. In the edge roll-off region of the bond substrate, the surface is curved, and the thickness is smaller than that of the central region of the bond substrate.

When an SOI substrate is manufactured using an ion implantation separation method, a bond substrate and a base substrate are bonded to each other. However, since the bonding is based on an intermolecular force or van der Waals force, the bonding is performed. Predetermined flatness is required for the mating surfaces. In the edge roll-off region where the flatness of the surface cannot be ensured, naturally, the bonding substrate and the base substrate are not bonded together.

For this reason, in the bond substrate after the single crystal silicon layer is separated, the single crystal silicon layer that has not been bonded to the base substrate remains as a protrusion at the peripheral edge where the edge roll-off region exists. . And the said convex part becomes a problem in the step of the reproduction | regeneration processing of a bond substrate. The height difference between the convex portion and the other region (a region where bonding is appropriately performed) is only about several hundred nm. However, in order to remove the convex portion by surface polishing by CMP treatment and regenerate as a new bond substrate, the substrate must be removed about 10 μm in the thickness direction, and the number of times the bond substrate is regenerated and used is sufficient. It has a problem that it cannot be secured.

In order to reduce the cost of the bond substrate in manufacturing the SOI substrate, it is desired to increase the number of times of reproduction and use of one bond substrate. In order to increase the number of times of regeneration and use for one bond substrate, it is desired to reduce the surface polishing amount of the substrate in the regeneration process. The surface of the bond substrate is preferably highly flat.

Therefore, an object of one embodiment of the present invention is to provide a method for regenerating a semiconductor substrate, in which a substrate with high surface flatness can be obtained with a small amount of polishing. Another object of one embodiment of the present invention is to provide a method for manufacturing a recycled semiconductor substrate, which can obtain a substrate with high surface flatness at low cost using the method for recycling a semiconductor substrate. Another object of one embodiment of the present invention is to provide a method for manufacturing an SOI substrate with low cost using the recycled semiconductor substrate.

The semiconductor substrate after the single crystal semiconductor layer is separated has a damaged semiconductor region that is damaged by ion addition treatment or the like in the manufacturing process of the SOI substrate and includes many crystal defects and voids. Due to the difference in crystallinity and the content of impurities such as carbon, the properties of the damaged semiconductor region are non-uniform. Therefore, in the damaged semiconductor region, the susceptibility of the semiconductor material to oxidation is not uniform.

In one embodiment of the present invention, a damaged semiconductor region (first damaged semiconductor region) in which a semiconductor material is easily oxidized is removed in the first step, the semiconductor material is hardly oxidized, and an undamaged semiconductor region has a polishing rate. After the different damaged semiconductor region (second damaged semiconductor region) is removed in the second step, a third step which is a polishing process is performed.

According to another aspect of the present invention, there is provided a method for regenerating a semiconductor substrate, in which a first damaged semiconductor region that is easily oxidized is formed on a semiconductor substrate including a first damaged semiconductor region and a second damaged semiconductor region that are easily oxidized. A first step of selectively removing using an acidic solution, and a second step of removing, using an alkaline solution, a second damaged semiconductor region that is less likely to be oxidized than the first damaged semiconductor region. And a third step of polishing the surface from which the first damaged semiconductor region and the second damaged semiconductor region have been removed. In one embodiment of the present invention, in the first step, the first damaged semiconductor region is oxidized, and the oxidized first damaged semiconductor region is removed.

Specifically, according to one embodiment of the present invention, a substance that oxidizes a semiconductor material included in a semiconductor substrate with respect to a semiconductor substrate including an undamaged semiconductor region, a first damaged semiconductor region, and a second damaged semiconductor region; Etching using a liquid mixture containing a substance that dissolves the oxidized semiconductor material and a substance that controls the oxidation rate of the semiconductor material and the dissolution rate of the oxidized semiconductor material is performed on the undamaged semiconductor region. A semiconductor which performs a first step of selectively removing the damaged semiconductor region, a second step of removing the second damaged semiconductor region using an alkaline solution, and a third step which is a polishing process A method for regenerating a substrate.

In the first step, the first damaged semiconductor region is removed by oxidizing the semiconductor material contained in the first damaged semiconductor region and dissolving the oxidized semiconductor material. In this step, since the etching rate is different between the undamaged semiconductor region and the first damaged semiconductor region, it is possible to suppress the unnecessary removal of a region that is not required to be removed (undamaged semiconductor region). Therefore, the amount of reduction in the thickness of the semiconductor substrate in one regeneration process can be reduced.

The second damaged semiconductor region, which is less likely to be oxidized than the first damaged semiconductor region, is not oxidized in the first step and thus is not dissolved and is not removed from the semiconductor substrate. Therefore, after the first step is finished, the second damaged semiconductor region partially remains on the semiconductor substrate (that is, the second damaged semiconductor region cannot be removed by the first step). It can be said that it is at least part of the semiconductor region).

Here, when the polishing process is performed after the first step, the polishing rate is different between the second damaged semiconductor region and the undamaged semiconductor region, and uniform polishing cannot be performed on the surface of the semiconductor substrate. Accordingly, unevenness (unevenness) corresponding to the partially damaged second damaged semiconductor region is formed on the surface, and it is difficult to obtain sufficient flatness in the reproduction semiconductor substrate. Alternatively, in order to obtain sufficient flatness in the regenerated semiconductor substrate, a large amount of semiconductor must be removed (the amount of polishing of the semiconductor increases), so that the number of times the semiconductor substrate is regenerated and used is reduced.

However, in the above embodiment of the present invention, after the first step, the second damaged semiconductor region is removed using an alkaline solution (second step). By using the alkaline solution, the semiconductor material in the damaged semiconductor region can be removed without oxidizing the semiconductor material. Therefore, in the second step, the first step that could not be removed in the first step. Two damaged semiconductor regions can be removed. Therefore, after the second step is completed, the damaged semiconductor region remaining on the semiconductor substrate is reduced (or there is almost no damaged semiconductor region) than when the first step is completed.

By performing a polishing process (third process) after the second process, it becomes easy to uniformly polish and planarize the surface of the semiconductor substrate. Further, a small amount of semiconductor is removed in order to obtain flatness. Therefore, by applying the semiconductor substrate recycling method of one embodiment of the present invention, a substrate with high surface flatness can be obtained with a small amount of polishing.

In addition, the semiconductor substrate from which the single crystal semiconductor layer has been separated may have an insulating layer on the surface due to formation of an insulating layer in a manufacturing process of the SOI substrate, natural oxidation, or the like. In the method for regenerating a semiconductor substrate of one embodiment of the present invention, a step of removing the insulating layer is performed before the first step.

One embodiment of the present invention includes a step of removing an insulating layer by etching a semiconductor substrate including an undamaged semiconductor region, a first damaged semiconductor region, a second damaged semiconductor region, and an insulating layer, and the semiconductor substrate Etching using a mixed solution containing a substance that oxidizes the semiconductor material to be oxidized, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate of the semiconductor material and the dissolution rate of the oxidized semiconductor material. A first step of selectively removing the first damaged semiconductor region with respect to the damaged semiconductor region, a second step of removing the second damaged semiconductor region using an alkaline solution, and a polishing process 3 is a method for regenerating a semiconductor substrate.

In addition, in the method for regenerating a semiconductor substrate of one embodiment of the present invention, an undamaged semiconductor region, a first damaged semiconductor region, and a second damaged semiconductor region are separated by separating a part as a semiconductor layer through ion irradiation and heat treatment. This is performed on the semiconductor substrate in which the semiconductor region remains.

In particular, when the ion irradiation is performed without mass separation, the method for regenerating a semiconductor substrate of one embodiment of the present invention is preferable.

Damaged semiconductor regions formed on a semiconductor substrate by ion irradiation without mass separation have a large difference in crystallinity, content of impurities such as carbon, etc. is there. In one embodiment of the present invention, a substrate with high surface flatness can be obtained with a small amount of polishing even when a damaged semiconductor region having non-uniform properties is removed.

Further, in the above semiconductor substrate recycling method, nitric acid is used as a substance that oxidizes a semiconductor material constituting the semiconductor substrate, and hydrofluoric acid is used as a substance that dissolves the oxidized semiconductor material. Acetic acid is preferably used as the substance that controls the dissolution rate of the semiconductor material.

By selecting such a material, the damaged semiconductor region (first damaged semiconductor region) is particularly selectively removed with respect to the undamaged semiconductor region, so that there is no need to remove the undamaged semiconductor region. Can be further suppressed. Therefore, the amount of reduction in the thickness of the semiconductor substrate in one regeneration process can be reduced.

Further, in the above semiconductor substrate recycling method, nitric acid is used as a substance that oxidizes a semiconductor material constituting the semiconductor substrate, and hydrofluoric acid is used as a substance that dissolves the oxidized semiconductor material. It is preferable that acetic acid is used as a substance for controlling the dissolution rate of the semiconductor material, the mixed solution further contains nitrous acid, and the concentration of the nitrous acid is 10 mg / l or more and 1000 mg / l or less.

It is preferable that nitrous acid functioning as an autocatalyst is included in the mixed liquid because the etching rate can be stabilized and the processing time can be shortened in the first step.

In addition, the method for regenerating a semiconductor substrate of one embodiment of the present invention is suitable for a case where the method is performed on a semiconductor substrate including a first damaged semiconductor region in a convex portion existing in the peripheral portion. In the first step included in one embodiment of the present invention, since the first damaged semiconductor region can be selectively removed with respect to the undamaged semiconductor region, the region that does not need to be removed when the convex portion is removed. Can be prevented from being removed excessively.

In the method for regenerating a semiconductor substrate, it is preferable to perform a drying process using isopropyl alcohol (IPA) between the second step and the third step.

By replacing water with isopropyl alcohol vapor and drying the semiconductor substrate, the surface can be uniformly dried.

In addition, the method for regenerating a semiconductor substrate of one embodiment of the present invention is suitable for a case where the thickness of a region excluding a defect-free region is 0 to 450 μm, preferably 0 to 100 μm.

By using such a semiconductor substrate and repeatedly performing fabrication of an SOI substrate and regeneration treatment of one embodiment of the present invention, the semiconductor substrate can be reused without performing high-temperature heat treatment for forming a defect-free region. Can be used up to the limit.

Another embodiment of the present invention is a method for manufacturing a recycled semiconductor substrate in which a recycled semiconductor substrate is manufactured from a semiconductor substrate using the above-described semiconductor substrate recycling method.

By applying one embodiment of the present invention, a substrate with high surface flatness can be obtained at low cost.

In one embodiment of the present invention, an embrittlement region is formed by adding ions to a regenerated semiconductor substrate manufactured using the above method for manufacturing a regenerated semiconductor substrate, and the base and the regenerated semiconductor substrate are interposed through an insulating layer. This is a method for manufacturing an SOI substrate in which a semiconductor layer is formed over a base substrate by bonding the substrate and separating the recycled semiconductor substrate by heat treatment.

By applying one embodiment of the present invention, an SOI substrate can be obtained at low cost.

According to one embodiment of the present invention, a method for regenerating a semiconductor substrate can be provided in which a substrate with high surface flatness can be obtained with a small amount of polishing. Further, it is possible to provide a method for manufacturing a regenerated semiconductor substrate, which can obtain a substrate with high surface flatness at low cost, using the method for regenerating a semiconductor substrate. In addition, a method for manufacturing an SOI substrate with low cost using the recycled semiconductor substrate can be provided.

4A and 4B illustrate an example of a method for manufacturing an SOI substrate. The figure which shows an example of the reproduction | regeneration method of a semiconductor substrate. 4A and 4B illustrate an example of a method for manufacturing an SOI substrate. 4A and 4B illustrate an example of a method for manufacturing an SOI substrate. 4A and 4B illustrate an example of a manufacturing process of an SOI substrate. 4A and 4B illustrate an example of a manufacturing process of an SOI substrate. FIG. 11 illustrates an example of a semiconductor device using an SOI substrate. The figure which shows the optical microscope photograph which concerns on an Example.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a method for recycling a semiconductor substrate of one embodiment of the present invention is described. Specifically, a method for regenerating a semiconductor substrate used for manufacturing an SOI substrate will be described.

As a method for manufacturing an SOI substrate, an ion implantation separation method is known. In the case of using an ion implantation separation method, a plurality of SOI substrates can be manufactured from one bond substrate (semiconductor substrate). This is because the bond substrate after use can be used again for manufacturing an SOI substrate by performing a regeneration process on the bond substrate after the semiconductor layer is separated.

The method for regenerating a semiconductor substrate of one embodiment of the present invention can be performed on a bond substrate after the semiconductor layer is separated. The bond substrate after the semiconductor layer is separated has a damaged semiconductor region that is damaged by an ion addition process or the like in the manufacturing process of the SOI substrate and includes many crystal defects and voids.

Note that in a single crystal semiconductor region to which ions are not added or an undamaged semiconductor region, atoms constituting the crystal are spatially regularly arranged. On the other hand, the damaged semiconductor region includes, for example, disorder of the arrangement (crystal structure) of atoms constituting the crystal, crystal defects, or distortion of the crystal lattice due to ion irradiation or the like.

Further, as described above, the properties of the damaged semiconductor region are not uniform due to the difference in crystallinity and the content of impurities such as carbon. Therefore, in the damaged semiconductor region, the susceptibility of the semiconductor material to oxidation is not uniform.

In one embodiment of the present invention, a damaged semiconductor region (first damaged semiconductor region) in which a semiconductor material is easily oxidized is removed in the first step, the semiconductor material is hardly oxidized, and an undamaged semiconductor region has a polishing rate. A different damaged semiconductor region (second damaged semiconductor region) is removed in the second step.

Note that in this specification, the damaged semiconductor region includes a first damaged semiconductor region and a second damaged semiconductor region.

Specifically, according to one embodiment of the present invention, a substance that oxidizes a semiconductor material included in a semiconductor substrate with respect to a semiconductor substrate including an undamaged semiconductor region, a first damaged semiconductor region, and a second damaged semiconductor region; Etching using a liquid mixture containing a substance that dissolves the oxidized semiconductor material and a substance that controls the oxidation rate of the semiconductor material and the dissolution rate of the oxidized semiconductor material is performed on the undamaged semiconductor region. A semiconductor which performs a first step of selectively removing the damaged semiconductor region, a second step of removing the second damaged semiconductor region using an alkaline solution, and a third step which is a polishing process A method for regenerating a substrate.

In the first step, the first damaged semiconductor region is removed by oxidizing the semiconductor material contained in the first damaged semiconductor region and dissolving the oxidized semiconductor material. In this step, since the etching rate is different between the undamaged semiconductor region and the first damaged semiconductor region, it is possible to suppress the unnecessary removal of a region that is not required to be removed (undamaged semiconductor region). Therefore, the amount of reduction in the thickness of the semiconductor substrate in one regeneration process can be reduced.

However, it is difficult to completely remove the second damaged semiconductor region that is less likely to be oxidized than the first damaged semiconductor region by the first step. Further, if it is attempted to remove not only the first damaged semiconductor region but also the second damaged semiconductor region in the first step, the time required for the first step becomes very long, which is not preferable. Therefore, after the first step is completed, the second damaged semiconductor region partially remains on the semiconductor substrate.

Further, the polishing rate is different between the second damaged semiconductor region and the undamaged semiconductor region. Therefore, when the polishing process is performed after the first step, uniform polishing cannot be performed on the surface of the semiconductor substrate, and unevenness (unevenness) corresponding to the second damaged semiconductor region is formed on the surface, and the recycled semiconductor substrate It is difficult to obtain sufficient flatness. Alternatively, in order to obtain sufficient flatness in the regenerated semiconductor substrate, a large amount of semiconductor must be removed (the amount of polishing of the semiconductor increases), so that the number of times the semiconductor substrate is regenerated and used is reduced.

Therefore, in one embodiment of the present invention, the second damaged semiconductor region is removed using an alkaline solution (second step) before the polishing treatment. By using an alkaline solution, the semiconductor material in the damaged semiconductor region can be removed without oxidizing the semiconductor material. Therefore, in the second process, the semiconductor material cannot be removed (or removed in the first process). The second damaged semiconductor region can be easily removed. Therefore, the semiconductor substrate after completion of the first step and the second step has a reduced damaged semiconductor region (or damage) compared to the semiconductor substrate when only the first step is completed. There is almost no semiconductor region).

By performing the polishing process (third process) after the second process, the difference in polishing rate on the surface of the semiconductor substrate can be reduced, so that it becomes easy to uniformly polish and flatten the surface. . Further, a small amount of semiconductor is removed in order to obtain flatness. Therefore, by applying the semiconductor substrate recycling method of one embodiment of the present invention, a substrate with high surface flatness can be obtained with a small amount of polishing.

Note that if the first damaged semiconductor region and the second damaged semiconductor region are both removed in the second step without performing the first step, the etching of the damaged semiconductor region is performed on the undamaged semiconductor region. Since this is not performed selectively, a region that is not required to be removed (an undamaged semiconductor region) is removed excessively. Accordingly, one aspect of the present invention includes both the first step of selectively removing the first damaged semiconductor region and the second step of removing the second damaged semiconductor region that cannot be removed by the first step. The semiconductor substrate recycling method is preferred.

Hereinafter, an example of a method for manufacturing an SOI substrate will be described with reference to FIGS. 1A to 1C, and then a method for regenerating a semiconductor substrate of one embodiment of the present invention will be described with reference to FIGS.

Note that details of a method for manufacturing the SOI substrate will be described later in Embodiment 2 (for example, the description of the process A to the process D illustrated in FIG. 5 can be referred to), and thus only a schematic description is given here.

<Method for Manufacturing SOI Substrate>
First, a base substrate 120 (FIG. 1A) and a semiconductor substrate 100 (FIG. 1B) which is a bond substrate are prepared. In this embodiment, the case where a glass substrate is used as the base substrate 120 and a single crystal silicon substrate is used as the semiconductor substrate 100 is described.

Next, the embrittled region 104 is formed at a predetermined depth from the surface of the semiconductor substrate 100. Then, the base substrate 120 and the semiconductor substrate 100 are attached to each other with the insulating layer 102 and the insulating layer 122 interposed therebetween (FIG. 1C).

The embrittlement region 104 can be formed, for example, by irradiating the insulating layer 102 formed on the semiconductor substrate 100 with hydrogen ions and adding hydrogen ions to the semiconductor substrate 100.

The insulating layer 102 and the insulating layer 122 function as a bonding layer. In order to suppress bonding failure, the bonding layer preferably has a smooth surface. The bonding layer may be omitted if not necessary. Further, only the insulating layer 122 over the base substrate 120 may be included as the bonding layer, or only the insulating layer 102 over the semiconductor substrate 100 may be included as the bonding layer. The insulating layer 102 and the insulating layer 122 include a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, and a hafnium oxide film, respectively. An insulating film such as a single layer or a stacked layer can be formed. These films can be formed using a thermal oxidation method, a CVD method, a sputtering method, or the like.

Note that in this specification and the like, the term “oxynitride” refers to a composition whose oxygen content (number of atoms) is higher than that of nitrogen. For example, silicon oxynitride refers to oxygen at 50 atomic% or more and 70 It includes atoms in a range of not more than atomic%, nitrogen not less than 0.5 atom% and not more than 15 atom%, silicon not less than 25 atom% and not more than 35 atom%, and hydrogen not less than 0.1 atom% and not more than 10 atom%. In addition, a nitrided oxide indicates a composition whose nitrogen content (number of atoms) is higher than that of oxygen. For example, silicon nitride oxide refers to an oxygen content of 5 atomic% to 30 atomic% and nitrogen content. It includes 20 atomic% to 55 atomic%, silicon in a range of 25 atomic% to 35 atomic%, and hydrogen in a range of 10 atomic% to 30 atomic%. However, the above ranges are those measured using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering Spectrometer (HFS). Further, the total content ratio of the constituent elements does not exceed 100 atomic%.

Next, heat treatment or the like is performed to separate the semiconductor substrate 100 into the semiconductor layer 124 and the separated semiconductor substrate 121 in the embrittled region 104, whereby the semiconductor layer 124 is formed over the base substrate 120 (FIG. 1 ( D)). The separated semiconductor substrate 121 includes an insulating layer 125 (a part of the insulating layer 102). The separated semiconductor substrate 121 becomes a recycled semiconductor substrate by a semiconductor substrate recycling method of one embodiment of the present invention, which will be described later, and can be used again for manufacturing an SOI substrate. Although not shown in FIG. 1, there are convex portions on the peripheral edge of the semiconductor substrate 121 after separation.

In the case where heat treatment is performed, atoms implanted by ion irradiation are deposited in the minute holes formed in the embrittled region 104 by the heat treatment, and the pressure inside the minute holes is increased. The increase in pressure causes a crack in the embrittled region 104, so that the semiconductor substrate 100 is separated in the embrittled region 104. Since the insulating layer 122 and the insulating layer 123 are bonded to each other, the insulating layer 122 (a part of the insulating layer 102) and the semiconductor layer 124 separated from the semiconductor substrate 100 through the insulating layer 123 are formed over the base substrate 120. Remains.

Thereafter, the surface of the semiconductor layer 124 is planarized by performing a surface treatment or the like. Examples of the surface treatment include laser beam irradiation treatment, polishing treatment such as etching treatment, and CMP treatment.

Through the above steps, an SOI substrate in which the semiconductor layer 124 is provided over the base substrate 120 with the insulating layer 122 and the insulating layer 123 provided therebetween can be obtained (FIG. 1E).

<Method for Regenerating Semiconductor Substrate of One Aspect of the Present Invention>
Next, a regeneration process of the separated semiconductor substrate 121 to which one embodiment of the present invention is applied is described with reference to FIGS.

At the peripheral edge of the semiconductor substrate 121, there is a protrusion 110 (FIG. 2A). The protrusion 110 includes an insulating layer 125, an unseparated semiconductor region 126, and a semiconductor region 127 to which ions are added.

The unseparated semiconductor region 126 and the semiconductor region 127 to which ions are added are included in the damaged semiconductor region, and are damaged by an ion addition process in the manufacturing process of the SOI substrate, and include many crystal defects and voids. It is out.

The protrusion 110 includes a region called an edge roll-off region of the semiconductor substrate. The edge roll-off region is generated due to the surface treatment (CMP treatment) of the semiconductor substrate. In the CMP process, due to its principle, polishing of the peripheral edge of the semiconductor substrate tends to proceed faster than the central portion. As a result, the peripheral portion of the semiconductor substrate has a region (edge roll-off region) having a smaller thickness than the central portion of the semiconductor substrate. ) Is formed. The thickness in the vicinity of the edge roll-off region is thinner than the thickness of the central portion of the semiconductor substrate before the semiconductor layer is separated, and the edge roll-off region is bonded when the SOI substrate is manufactured. This is an area where no operation is performed. As a result, the protrusion 110 remains in the edge roll-off region of the semiconductor substrate 121.

Note that a semiconductor region 129 to which ions are added exists in a region other than the convex portion 110 of the semiconductor substrate 121 (particularly, a region surrounded by the edge roll-off region). The semiconductor region 129 to which ions are added is formed in such a manner that a region to which ions are formed in the manufacturing process of the SOI substrate remains in the semiconductor substrate 121 after the semiconductor layer is separated. The semiconductor region 129 to which ions are added is sufficiently thinner than the semiconductor regions (the semiconductor region 126 and the semiconductor region 127) in the convex portion 110. The semiconductor region 129 is also included in the damaged semiconductor region, is damaged by an ion addition process, and includes many crystal defects.

FIG. 2B is a schematic diagram in which the convex portion 110 is enlarged. The convex portion 110 includes a region corresponding to the edge roll-off region and a region corresponding to the chamfered portion. In the present embodiment, the edge roll-off region refers to a region in which points where the angle θ formed by the tangent plane on the surface of the convex portion 110 and the reference surface is 0.5 ° or less are gathered. Here, a plane parallel to the front surface or the back surface of the semiconductor substrate is employed as the reference surface.

Further, the chamfered portion may be defined as a region having a distance of less than 0.2 mm from the edge of the substrate, and the edge roll-off region may be defined as a region where the inner side is not bonded. Specifically, a region whose distance from the edge of the substrate is 0.2 mm or more and 0.9 mm or less can be referred to as an edge roll-off region.

Note that since the chamfered portion is not involved in the bonding of the base substrate and the bond substrate, the flatness of the chamfered portion does not cause a problem in the substrate recycling process. On the other hand, the vicinity of the edge roll-off region is involved in the bonding of the base substrate and the bond substrate. Therefore, depending on the flatness of the edge roll-off region, the recycled semiconductor substrate may not be used for the manufacturing process of the SOI substrate. For these reasons, it is extremely important to improve the flatness by removing the convex portions 110 in the edge roll-off region in the semiconductor substrate recycling process.

The semiconductor substrate regeneration process in this embodiment includes a step of removing the insulating layer 125, a first step of removing the first damaged semiconductor region, and a second step of removing the second damaged semiconductor region. And a third step which is a polishing process. These will be described in detail below.

<< Removal of Insulating Layer 125 >>
The insulating layer 125 can be removed by a wet etching process using a solution containing hydrofluoric acid as an etchant (FIG. 2C). As the solution containing hydrofluoric acid, a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (for example, product name: LAL500 manufactured by Stella Chemifa Corporation) or a 5% hydrofluoric acid solution can be used. The wet etching treatment is preferably performed for about 120 seconds to 500 seconds, preferably about 180 seconds to 300 seconds.

Note that wet etching treatment can be performed by immersing the semiconductor substrate 121 in a solution in the treatment tank, and thus a plurality of semiconductor substrates 121 can be collectively treated. For this reason, the efficiency of the reproduction process can be improved.

A dry etching process may be used as the first etching process. Further, a wet etching process and a dry etching process may be used in combination. As the dry etching process, a parallel plate RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) etching method, or the like can be used.

Note that when the insulating layer 125 is not provided over the semiconductor substrate 121 (for example, when the insulating layer 102 (a bonding layer) is not provided over the semiconductor substrate 100 in the manufacturing process of the SOI substrate), the insulating layer 125 is not formed. This step of removing can be omitted. In addition, a natural oxide film may be formed on the semiconductor substrate 100 during an SOI substrate manufacturing process or the like. This step may be performed to remove the natural oxide film.

<< First Step: Removal of First Damaged Semiconductor Region >>
In the first step, a mixture containing a substance that oxidizes the semiconductor material, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate of the semiconductor material and the dissolution rate of the oxidized semiconductor material The first damaged semiconductor region is removed by performing a wet etching process using the liquid as an etchant.

Nitric acid is preferably used as the substance that oxidizes the semiconductor material. Further, hydrofluoric acid is preferably used as the substance that dissolves the oxidized semiconductor material. In addition, acetic acid is preferably used as the substance that controls the oxidation rate of the semiconductor material and the dissolution rate of the oxidized semiconductor material.

The etching process is desirably performed for about 1 minute to 10 minutes, and for example, it is preferable to perform the etching process for about 2 minutes to 8 minutes. The temperature of the mixed solution is desirably about 10 ° C. or higher and 30 ° C. or lower, and for example, 25 ° C. is preferable.

When nitric acid is used as a substance that oxidizes the semiconductor material contained in the mixed solution, it is preferable that the mixed solution contains nitrous acid that functions as an autocatalyst. By including nitrous acid, the etching rate can be stabilized. Further, by containing nitrous acid, the etching rate is increased, and the processing time can be shortened.

The etching process including nitrous acid is preferably performed for 30 seconds or more and 120 seconds or less. For example, when a mixed solution having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid described later of 1: 2: 10 is used, 45 seconds. It is preferable to perform the above for about 105 seconds or less. Moreover, it is preferable that the temperature of a liquid mixture shall be about 10 degreeC or more and 40 degrees C or less, for example, it is suitable to set it as 30 degreeC.

When a mixed solution of nitric acid (concentration: 70% by weight), hydrofluoric acid (concentration: 50% by weight), and acetic acid (concentration: 99.7% by weight) is used as the etchant, the volume of nitric acid is equal to the volume of acetic acid. More than 0.01 times and less than 1 time and more than 0.1 times and less than 100 times the volume of hydrofluoric acid, and the volume of hydrofluoric acid is more than 0.01 times and less than 0.5 times the volume of acetic acid It is preferable that For example, the volume ratio of hydrofluoric acid, nitric acid, and acetic acid is preferably 1: 3: 10. When nitrous acid is included, for example, the volume ratio of hydrofluoric acid, nitric acid and acetic acid is preferably 1: 2: 10 (nitrite concentration of 10 mg / l or more and 1000 mg / l or less).

In the damaged semiconductor region, there are crystal defects and voids formed with the addition of ions, and the etchant easily penetrates. For this reason, in the damaged semiconductor region, etching proceeds not only from the surface but also from the inside.

Specifically, etching proceeds to form deep vertical holes in a direction perpendicular to the substrate plane, and tends to be performed to enlarge the vertical holes. In other words, in the damaged semiconductor region, the etching process proceeds at a higher etching rate than in the undamaged semiconductor region.

Here, “etching rate” refers to the etching amount per unit time (the amount to be etched). That is, “high etching rate” means that etching is easier, and “low etching rate” means that etching is more difficult.

As described above, etching is performed using a mixed liquid containing a substance that oxidizes the semiconductor material, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate of the semiconductor material and the dissolution rate of the oxidized semiconductor material as an etchant. By performing the treatment, the first damaged semiconductor region can be selectively removed with respect to the undamaged semiconductor region.

Note that the thickness of the damaged semiconductor region (semiconductor region 126 and semiconductor region 127) in the convex portion 110 and the thickness of the damaged semiconductor region (semiconductor region 129) in other regions are greatly different. For this reason, the etching selectivity between the convex portion 110 (peripheral portion) and the other region (center portion) is not constant during the first step.

Specifically, it is as follows. First, immediately after the first step is started, the first damaged semiconductor region is etched in the convex portion 110 and other regions, and the etching selectivity is about 1. After the first damaged semiconductor region in the region (semiconductor region 129) other than the convex portion 110 is removed, an undamaged semiconductor region appears in the region. For this reason, the first damaged semiconductor region of the convex portion 110 is preferentially removed, and the etching selectivity is 1.7 or more. When the first damaged semiconductor region of the convex portion 110 (semiconductor region 126, semiconductor region 127) is removed, an undamaged semiconductor region appears in the region, so that the etching selectivity is about 1 again. .

As described above, since the etching selection ratio varies between the first steps, the change in the selection ratio can be used as a guide at the end of etching. For example, the first damaged semiconductor region can be removed while suppressing unnecessary over-etching in the first step by stopping the etching process when the etching selectivity is reduced to less than 1.2. it can.

The etching selection ratio is obtained by comparing the reduction amounts of the film thicknesses of the convex portion 110 (peripheral portion) and the other region (center portion) in a predetermined time (for example, 30 seconds, 1 minute, etc.). It may be a difference value (difference value), or may be a difference value (differential value) obtained by comparing instantaneous film thickness reduction amounts.

As described above, in the first step, since the etching rate is different between the first damaged semiconductor region and the undamaged semiconductor region, an unnecessary region (undamaged semiconductor region) is removed. This can be suppressed.

<< Second Step: Removal of Second Damaged Semiconductor Region >>
In the second step, the damaged semiconductor region (second damaged semiconductor region) that could not be removed in the first step is removed using an alkaline solution.

By using the alkaline solution, the semiconductor material in the damaged semiconductor region can be removed without oxidizing the semiconductor material. Therefore, in the second step, the first step that could not be removed in the first step. Two damaged semiconductor regions can be removed. Therefore, after the second step is completed, the damaged semiconductor region remaining on the semiconductor substrate is reduced (or there is almost no damaged semiconductor region) than when the first step is completed.

The alkaline solution may contain either an inorganic alkali or an organic alkali. Examples of the solution containing an organic alkali include an organic alkali aqueous solution containing TMAH (Tetra Methyl Ammonium Hydroxide), an ammonia hydrogen peroxide solution mixed solution (APM), and the like. Moreover, you may use a commercially available organic alkaline cleaning agent, for example, an alkaline glass substrate cleaning agent etc., Specifically, PK-LCG407 (made by Parker Corporation) etc. can be used.

The alkaline solution preferably has a pH of 9 to 13 and more preferably has a pH of 10 to 12.

The treatment using the alkaline solution is desirably performed for about 1 minute to 10 minutes, and for example, it is preferable to perform for about 5 minutes. The temperature of the alkaline solution is desirably about 10 ° C. or more and 50 ° C. or less, and is preferably 40 ° C., for example.

Note that the surface of the semiconductor substrate on which the third step is performed is preferably uniformly dried. Therefore, it is preferable to perform drying by IPA (Isopropyl Alcohol) (a method of replacing water with isopropyl alcohol vapor) on the semiconductor substrate after the second step is completed and before the third step is performed.

For example, when moisture adheres to a part of the surface of the semiconductor substrate, a reaction product called a watermark is formed, and drying unevenness or unevenness may occur on the surface of the semiconductor substrate. If such unevenness and unevenness occur, it may be difficult to obtain a regenerated semiconductor substrate having sufficient flatness in the third step. Alternatively, in order to obtain a regenerated semiconductor substrate having sufficient flatness, a large amount of semiconductor must be removed (the amount of semiconductor polishing increases). Therefore, it is preferable to dry the semiconductor substrate uniformly.

<< Third step: Polishing process >>
In the third step, a polishing process is performed to planarize the surface of the semiconductor substrate.

Since the second damaged semiconductor region is removed in the second step, it can be said that there are almost no portions with different polishing rates on the surface of the semiconductor substrate when the third step is performed. Therefore, in the third step, uniform polishing can be performed on the surface of the semiconductor substrate 121, and formation of unevenness due to uneven polishing can be suppressed. Further, it is possible to obtain a regenerated semiconductor substrate that suppresses the removal of excess semiconductor and has high flatness.

As the polishing process, a CMP process is preferably performed.

Here, the CMP treatment refers to a method of flattening the surface of an object to be processed by a chemical / mechanical combined action. For example, it is performed by attaching a polishing cloth on the polishing stage and rotating or swinging the polishing stage and the workpiece while supplying slurry (abrasive) between the workpiece and the polishing cloth. . Thus, the surface of the object to be processed is polished by the chemical reaction between the slurry and the surface of the object to be processed and the action of mechanical polishing of the object to be processed by the polishing cloth.

The number of CMP processes may be one or more. When performing the CMP process a plurality of times, for example, it is preferable to perform the first CMP process at a high polishing rate and then perform the second CMP process at a low polishing rate.

The polishing cloth used for the first CMP process is preferably harder than the polishing cloth used for the second CMP process. In addition, the particle size of the slurry used for the first CMP treatment is preferably larger than the particle size of the slurry used for the second CMP treatment.

For example, a polishing cloth containing polyurethane can be used. Moreover, it is preferable that the particle size of the slurry in the first CMP treatment is about 50 nm to 120 nm. The particle size of the slurry in the second CMP treatment is preferably about 45 nm to 75 nm.

In the CMP process, it is preferable to avoid excessive removal of the semiconductor by appropriately setting the slurry flow rate, the polishing pressure, the spindle rotation speed, the table rotation speed, and the processing time. For example, the removal amount of the semiconductor can be suppressed by not increasing the polishing pressure too much or lengthening the processing time.

In addition, by setting the spindle rotation speed and the table rotation speed to different values, it is possible to suppress polishing of only the same region of the semiconductor substrate surface (the region to be polished is biased) and to spread the polishing over the entire surface. Since it can be performed (evenly), it is preferable. Further, it is preferable because it is easy to improve the flatness of the surface included in the convex portion 110 having a particularly low flatness among the surfaces of the semiconductor substrate.

Note that the damaged semiconductor region that could not be removed in the first step and the second step can also be removed in the polishing process.

In the method for regenerating a semiconductor substrate of one embodiment of the present invention, the first damaged semiconductor region is removed in the first step, and the second damaged semiconductor region is removed in the second step. Therefore, even if the flatness of the surface of the semiconductor substrate before the third step is low, the surface has a small difference in polishing rate, so that a reclaimed semiconductor substrate having a highly flat surface can be obtained with a small amount of polishing. Can do.

In addition to the polishing process, a laser beam irradiation process or a lamp light irradiation process may be performed.

Thus, the semiconductor substrate 121 is regenerated, and the regenerated semiconductor substrate 132 is completed as shown in FIG.

As described above, in the semiconductor substrate recycling method of one embodiment of the present invention, the damaged semiconductor region (first damaged semiconductor region) in which the semiconductor material is easily oxidized is removed in the first step, and the semiconductor material is oxidized. After the damaged semiconductor region (second damaged semiconductor region) that is difficult to be damaged and has a polishing rate different from that of the undamaged semiconductor region is removed in the second step, a third step, which is a polishing process, is performed. Therefore, a substrate with high surface flatness can be obtained with a small amount of polishing.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing an SOI substrate will be described with reference to FIGS.

[Step A: Treatment to bond substrate]
In step A shown in FIG. 5, the semiconductor substrate 100 which is a bond substrate is processed. Specifically, preparation for bonding to the base substrate 120 is performed, such as formation of the embrittled region 104 in the semiconductor substrate 100.

<< Step (A-1): Board Preparation >>
First, a semiconductor substrate 100 is prepared as a bond substrate (FIG. 3A). A chamfered portion for preventing chipping and cracking is present at the peripheral portion of the semiconductor substrate 100.

As the semiconductor substrate 100, for example, a single crystal semiconductor substrate made of a group 14 element, such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate, or a polycrystalline semiconductor substrate can be used. A compound semiconductor substrate such as gallium arsenide, gallium arsenide phosphorus, or indium gallium arsenide can also be used. The shape of the semiconductor substrate 100 is not limited, and a circular or rectangular substrate can be used. The semiconductor substrate 100 can be manufactured using a CZ (Czochralski) method or an FZ (floating zone) method.

In the following description, a case where a rectangular single crystal silicon substrate is used as the semiconductor substrate 100 is described.

Note that the surface of the semiconductor substrate 100 is preferably cleaned as appropriate. For cleaning, for example, sulfuric acid hydrogen peroxide mixed solution (SPM), ammonia hydrogen peroxide mixed solution (APM), hydrochloric hydrogen peroxide mixed solution (HPM), dilute hydrofluoric acid (DHF), ozone water, etc. Can be used. Alternatively, the surface of the semiconductor substrate 100 may be cleaned by alternately discharging dilute hydrofluoric acid and ozone water. If necessary, it is preferable to combine ultrasonic cleaning such as megahertz ultrasonic cleaning (megasonic cleaning) or two-fluid jet cleaning. By cleaning, foreign matter and organic contamination on the surface of the semiconductor substrate 100 can be reduced, and the insulating layer 102 can be formed uniformly.

<< Step (A-2): Formation of insulating layer >>
Next, the insulating layer 102 is formed over the semiconductor substrate 100 (FIG. 3B). Since the insulating layer 102 over the semiconductor substrate 100 is not an essential component, the step (A-2) can be omitted.

The insulating layer 102 may be a single insulating film or a stack of a plurality of insulating films. The insulating layer 102 can be formed using an insulating film containing silicon as a composition, such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Alternatively, the material described in Embodiment 1 may be used.

In this embodiment, the case where a silicon oxide film is used as the insulating layer 102 is described as an example.

Note that in FIG. 3B, the insulating layer 102 is formed so as to cover the semiconductor substrate 100; however, one embodiment of the present invention is not limited thereto. When the insulating layer 102 is provided on the semiconductor substrate 100 using a CVD method or the like, the insulating layer 102 may be formed only on one surface of the semiconductor substrate 100.

A silicon oxide film used as the insulating layer 102 uses a mixed gas such as silane and oxygen, or tetraethoxysilane (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ) and oxygen, and is formed by thermal CVD, plasma CVD, atmospheric pressure CVD, or bias. It can be formed by a vapor phase growth method such as ECRCVD. In this case, the surface of the silicon oxide film may be densified by oxygen plasma treatment. Further, the silicon oxide film may be formed by a chemical vapor deposition method using an organosilane gas. Examples of the organic silane gas include tetraethoxysilane (TEOS), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane ( Silicon-containing compounds such as HMDS), triethoxysilane (chemical formula SiH (OC ₂ H ₅ ) ₃ ), and trisdimethylaminosilane (chemical formula SiH (N (CH ₃ ) ₂ ) ₃ ) can be used.

Alternatively, the insulating layer 102 can be formed using a thermal oxide film obtained by thermally oxidizing the semiconductor substrate 100. For the thermal oxidation treatment for forming the thermal oxide film, wet oxidation, virogenic oxidation, or dry oxidation may be used, and a gas containing halogen may be added to the oxidizing atmosphere. As the gas containing halogen, one or a plurality of gases selected from HCl, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ , BCl ₃ , F ₂ , Br _{2, and the} like can be used.

As an example of conditions for forming the thermal oxide film, 700 ° C. or higher and 1100 ° C. or lower (typically, in an atmosphere containing HCl at 0.5 to 10% by volume (preferably 3% by volume) with respect to oxygen (typically, And heat treatment is performed at about 950 ° C. The treatment time may be 0.1 to 6 hours, preferably 0.5 to 1 hour. The thickness of the oxide film to be formed can be 10 nm to 1100 nm (preferably 50 nm to 150 nm), for example, 100 nm.

By such thermal oxidation treatment in an atmosphere containing a halogen element, the oxide film can contain the halogen element. By including a halogen element in the oxide film at a concentration of 1 × 10 ¹⁷ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , heavy metals (eg, Fe, Cr, Ni, Mo, etc.) that are extrinsic impurities Since the oxide film collects, contamination of a semiconductor layer to be formed later can be prevented.

In addition, by including a halogen element such as chlorine in the insulating layer 102, impurities (for example, movable ions such as Na) that adversely affect the semiconductor substrate 100 can be gettered. Specifically, by heat treatment performed after the insulating layer 102 is formed, impurities contained in the semiconductor substrate 100 are deposited on the insulating layer 102 and are captured by reacting with halogen atoms (for example, chlorine atoms). Accordingly, the impurities collected in the insulating layer 102 can be fixed and contamination of the semiconductor substrate 100 can be prevented. In addition, the insulating layer 102 can also function as a film that fixes impurities such as Na contained in glass when bonded to a glass substrate.

In particular, inclusion of a halogen such as chlorine in the insulating layer 102 by heat treatment in an atmosphere containing halogen can cause the semiconductor substrate 100 to be used when the semiconductor substrate 100 is not sufficiently cleaned or is subjected to repeated regeneration treatment. Effective in decontamination.

In addition, since the defects on the surface of the semiconductor substrate 100 are terminated by the halogen element contained in the oxidation treatment atmosphere, the localized level density at the interface between the oxide film and the semiconductor substrate 100 can be reduced.

Further, the halogen element contained in the insulating layer 102 causes distortion in the insulating layer 102. As a result, the moisture absorption rate of the insulating layer 102 is improved, and the moisture diffusion rate is increased. That is, when moisture exists on the surface of the insulating layer 102, moisture present on the surface can be quickly absorbed and diffused into the insulating layer 102.

Further, in the case where a glass substrate containing impurities that reduce the reliability of a semiconductor device such as an alkali metal or an alkaline earth metal is used as the base substrate, the impurities can be prevented from diffusing from the base substrate to the semiconductor layer. It is preferable that the insulating layer 102 includes at least one or more layers. Examples of such a film include a silicon nitride film and a silicon nitride oxide film. When the insulating layer 102 includes such a film, the insulating layer 102 can function as a barrier film (also referred to as a blocking film).

For example, when the insulating layer 102 is formed as a barrier film having a single-layer structure, the insulating layer 102 can be formed using a silicon nitride film or a silicon nitride oxide film with a thickness of 15 nm to 300 nm.

In the case where the insulating layer 102 has a two-layer structure that functions as a barrier film, the upper layer is formed using an insulating film having a high barrier function. The upper insulating film can be formed of, for example, a silicon nitride film or a silicon nitride oxide film having a thickness of 15 nm to 300 nm. These films have a high blocking effect for preventing the diffusion of impurities, but have a high internal stress. Therefore, it is preferable to select a film having an effect of relaxing the stress of the upper insulating film as the lower insulating film in contact with the semiconductor substrate 100. As an insulating film having an effect of relieving the stress of the upper insulating film, there are a silicon oxide film, a silicon oxynitride film, a thermal oxide film formed by thermally oxidizing the semiconductor substrate 100, and the like. The thickness of the lower insulating film can be greater than or equal to 5 nm and less than or equal to 200 nm.

For example, in order to function the insulating layer 102 as a barrier film, a silicon oxide film and a silicon nitride film, a silicon oxynitride film and a silicon nitride film, a silicon oxide film and a silicon nitride oxide film, or a silicon oxynitride film and a silicon nitride oxide film The insulating layer 102 is preferably formed using a combination of films and the like.

<< Step (A-3): Ion Irradiation >>
Next, the semiconductor substrate 100 is irradiated with an ion beam composed of ions accelerated by an electric field through the insulating layer 102 as indicated by an arrow, and an embrittled region is formed in a region at a desired depth from the surface of the semiconductor substrate 100. 104 is formed (FIG. 3C). The depth at which the embrittlement region 104 is formed is approximately the same as the average penetration depth of ions, and this can be adjusted by the acceleration energy of the ion beam and the incident angle of the ion beam. The acceleration energy can be adjusted by the acceleration voltage. The thickness of the semiconductor layer 124 to be separated from the semiconductor substrate 100 later is determined by the depth at which the embrittled region 104 is formed. The depth at which the embrittled region 104 is formed can be, for example, 10 nm or more and 500 nm or less from the surface of the semiconductor substrate 100, and the preferable depth range is 50 nm or more and 300 nm or less, for example, about 200 nm. Note that in this embodiment mode, ion irradiation is performed after the insulating layer 102 is formed; however, the present invention is not limited to this, and ion irradiation may be performed before the insulating layer 102 is formed.

The embrittlement region 104 can be formed by an ion doping process. The ion doping treatment can be performed using an ion doping apparatus. As a typical example of an ion doping apparatus, there is a non-mass separation type apparatus that irradiates an object to be processed disposed in a chamber with an ion beam including all ion species generated by plasma excitation of a process gas. is there. In a non-mass separation type apparatus, ion species in plasma are not subjected to mass separation, and an object to be processed is irradiated with an ion beam containing all the ion species.

In this embodiment, the case where the semiconductor substrate 100 is irradiated with an ion beam including all ion species generated by plasma excitation of a plasma source gas using an ion doping apparatus will be described. As the plasma source gas, a gas containing hydrogen, for example, H ₂ is supplied. A gas containing hydrogen is excited to generate plasma, ions included in the plasma are accelerated without mass separation, and the accelerated ions are implanted into the semiconductor substrate 100.

In the ion beam irradiation treatment, the ratio of H ₃ ^{+ to} the total amount of ion species (H ⁺ , H ₂ ⁺ , H ₃ ⁺ ) generated from hydrogen gas is set to 50% or more. More preferably, the ratio of H ₃ ⁺ is 80% or more. This is because hydrogen ions can be efficiently implanted into the semiconductor substrate 100 by increasing the ratio of H ₃ ^{+ in} the plasma. Since H ₃ ⁺ has a mass three times that of H ⁺ , when one hydrogen atom is implanted at the same depth, the acceleration voltage of H ₃ ⁺ may be three times the acceleration voltage of H ^+. Is possible. As a result, the tact time of the ion beam irradiation process can be shortened, and productivity and throughput can be improved. Further, by implanting ions with the same mass, the ions can be implanted while being concentrated at the same depth of the semiconductor substrate 100.

Since the ion doping apparatus is inexpensive and excellent in large area processing, irradiation with H ₃ ⁺ using the ion doping apparatus significantly improves semiconductor characteristics, increases area, reduces costs, and improves productivity. Effects can be obtained. In addition, when an ion doping apparatus is used, heavy metal may be introduced at the same time. However, contamination of the semiconductor substrate 100 with heavy metal is caused by ion irradiation through the insulating layer 102 containing chlorine atoms. Can be prevented.

The embrittlement region 104 may be formed by ion implantation using an ion implantation apparatus. The ion implantation apparatus mass-separates a plurality of ion species generated by plasma-exciting a source gas from an object to be processed disposed in a chamber, and irradiates the object to be processed with an ion beam containing specific ion species. It is a mass separation type device. In the case of using an ion implantation apparatus, H ⁺ , H ₂ ⁺ , and H ₃ ⁺ generated by exciting hydrogen gas and PH ₃ are mass-separated and any one of these is implanted into the semiconductor substrate 100.

In the ion implantation apparatus, the semiconductor substrate 100 can be irradiated with an ion beam of a single ion, and ions can be implanted while being concentrated at the same depth of the semiconductor substrate 100. For this reason, it is possible to sharpen the peak in the profile of the implanted ions in the depth direction, and it is easy to improve the flatness of the surface of the semiconductor layer to be separated. In addition, the electrode structure is preferable because contamination by heavy metals is relatively small and deterioration of characteristics of the semiconductor layer can be suppressed.

<< Step (A-4): Surface Treatment >>
Next, the semiconductor substrate 100 over which the insulating layer 102 is formed is cleaned. This cleaning step can be performed by ultrasonic cleaning with pure water or two-fluid jet cleaning with pure water and nitrogen. As the ultrasonic cleaning, it is desirable to use megahertz ultrasonic cleaning (megasonic cleaning).

After the above-described ultrasonic cleaning or two-fluid jet cleaning, the semiconductor substrate 100 may be cleaned with ozone water. By washing with ozone water, organic substances can be removed and the surface can be activated to improve the hydrophilicity of the surface of the insulating layer 102.

The surface activation treatment of the insulating layer 102 can be performed by cleaning with ozone water, irradiation treatment with an atomic beam or ion beam, ultraviolet treatment, ozone treatment, plasma treatment, biased plasma treatment, or radical treatment. When an atomic beam or an ion beam is used, an inert gas neutral atom beam such as argon or an inert gas ion beam can be used.

Ozone is generated by irradiating ultraviolet rays in an atmosphere containing oxygen. Ozone is effective in removing organic substances adhering to the surface of the object to be processed. Singlet oxygen is also effective in removing organic substances adhering to the surface of the object to be processed, equivalent to or higher than ozone. Ozone and singlet oxygen are examples of oxygen in an active state, and are collectively referred to as active oxygen. In this specification, the reaction including singlet oxygen is referred to as ozone treatment for convenience. This is because ozone is generated when singlet oxygen is generated, or there is a reaction that generates singlet oxygen from ozone.

[Process B: Processing to base substrate]
In step B shown in FIG. 5, the base substrate 120 is processed as preparation for bonding to the semiconductor substrate 100.

<< Step (B-1): Board Preparation >>
First, the base substrate 120 is prepared. As the base substrate 120, an insulating substrate is preferably used, and various glass substrates used in the electronic industry such as aluminosilicate glass, barium borosilicate glass, aluminoborosilicate glass, quartz substrate, ceramic substrate, sapphire substrate, etc. are used. be able to. In addition, a single crystal semiconductor substrate (for example, a single crystal silicon substrate) or a polycrystalline semiconductor substrate (for example, a polycrystalline silicon substrate) may be used as the base substrate 120.

As the base substrate 120, a substrate having high heat resistance may be used. Examples of the substrate having high heat resistance include a quartz substrate, a sapphire substrate, and a semiconductor substrate (such as a single crystal silicon substrate or a polycrystalline silicon substrate). By using a substrate having high heat resistance, it is possible to raise the upper limit of the temperature of various subsequent heat treatments to the vicinity of the melting point of the substrate.

When a glass substrate is used as the base substrate 120, for example, a mother glass substrate developed for manufacturing a liquid crystal panel is preferably used. By manufacturing an SOI substrate using a large-area mother glass substrate as the base substrate 120, an increase in the area of the SOI substrate can be realized. If an SOI substrate with a large area is realized, a plurality of ICs can be manufactured at one time, and the number of semiconductor devices manufactured from one substrate increases, so that productivity is dramatically improved. Can do.

<< Step (B-2): Formation of insulating layer >>
Next, the insulating layer 122 is formed over the base substrate 120. For example, the base substrate 120 includes a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like that functions as a barrier film, so that an alkali metal or an alkali can be formed from the base substrate 120 to the semiconductor substrate 100. Impurities such as earth metals can be prevented from entering. As described above, the insulating layer 122 is preferably provided over the base substrate 120, but the insulating layer 122 over the base substrate 120 is not an essential component, and thus the step (B-2) can be omitted.

<< Step (B-3): Surface Treatment >>
Then, before bonding, the surface of the base substrate 120 is washed. The surface of the base substrate 120 can be cleaned using cleaning with hydrochloric acid and hydrogen peroxide, megahertz ultrasonic cleaning, two-fluid jet cleaning, cleaning with ozone water, or the like. Similarly to the insulating layer 102, surface activation treatment such as atomic beam or ion beam irradiation treatment, ultraviolet treatment, ozone treatment, plasma treatment, bias application plasma treatment, or radical treatment is performed on the surface of the insulating layer 122. It is preferable to perform the pasting.

[Step C: Form semiconductor layer on base substrate]
In Step C illustrated in FIG. 5, the semiconductor substrate 100 and the base substrate 120 are bonded to each other, and the semiconductor substrate 100 is separated into a semiconductor substrate 121 and a semiconductor layer 124 over the base substrate 120.

<< Step (C-1): Bonding >>
First, the semiconductor substrate 100 that has undergone the process A and the base substrate 120 that has undergone the process B are bonded together (FIG. 4A). Here, the semiconductor substrate 100 and the base substrate 120 are attached to each other with the insulating layer 102 and the insulating layer 122 interposed therebetween, but this is not the case when the insulating layer is not formed.

^{Lamination, 0.1N / cm 2 ~500N / cm} 2 to one part of the edge of the base substrate 120, is preferably realized by applying pressure of about ^{1N / cm 2 ~20N / cm 2} . The semiconductor substrate 100 and the base substrate 120 start to be bonded from the portion where the pressure is applied to the base substrate 120, and the bonding is spontaneously performed on the entire surface, and the bonding between the base substrate 120 and the semiconductor substrate 100 is completed. The bonding is based on the principle of van der Waals force or the like, and a strong bonded state can be formed even at room temperature.

Note that a region called an edge roll-off region exists in the peripheral portion of the semiconductor substrate 100, and the semiconductor substrate 100 (insulating layer 102) and the base substrate 120 (insulating layer 122) may not be in contact with each other in the region. Further, the base substrate 120 and the semiconductor substrate 100 do not come into contact with each other even at the chamfered portion that exists outside the edge roll-off region (near the edge of the semiconductor substrate 100).

When a plurality of semiconductor substrates 100 are bonded to one base substrate 120, it is desirable to apply pressure to each semiconductor substrate 100. This is because the semiconductor substrate 100 that is not in contact with the base substrate 120 may be generated due to the difference in thickness of the semiconductor substrate 100. Note that even when the thickness of the semiconductor substrate 100 is slightly different, when the semiconductor substrate 100 and the base substrate 120 can be brought into close contact with each other by bending of the base substrate 120, bonding can be performed well. This is not the case because it is possible.

<< Step (C-2): Heat treatment >>
After the semiconductor substrate 100 is bonded to the base substrate 120, it is desirable to perform heat treatment for strengthening the bonding. The temperature of the heat treatment is preferably a temperature at which cracks are not generated in the embrittled region 104, for example, 200 ° C. or higher and 450 ° C. or lower. In addition, the same effect can be obtained by bonding the semiconductor substrate 100 to the base substrate 120 while being heated in this temperature range. Note that the above-described heat treatment is desirably performed continuously in an apparatus or a place where bonding is performed. This is because peeling of the substrate due to the conveyance of the substrate before the heat treatment can be prevented.

Note that when the semiconductor substrate 100 and the base substrate 120 are bonded to each other, if particles or the like adhere to the bonding surface, the bonding is not performed on the bonded portion. In order to prevent adhesion of particles, it is preferable that the semiconductor substrate 100 and the base substrate 120 be bonded to each other in a processing chamber in which airtightness is ensured. Furthermore, when the semiconductor substrate 100 and the base substrate 120 are bonded to each other, the processing chamber may be in a reduced pressure state (for example, about 5.0 × 10 ⁻³ Pa) to clean the bonding process atmosphere. .

<< Step (C-3): Separation >>
Next, by performing heat treatment, the semiconductor substrate 100 is separated in the embrittled region 104, the semiconductor layer 124 is formed over the base substrate 120, and the semiconductor substrate 121 is formed (FIG. 4B). In the region other than the edge roll-off region and the chamfered portion, the semiconductor substrate 100 and the base substrate 120 are bonded to each other, and thus the semiconductor layer 124 separated from the semiconductor substrate 100 is fixed on the base substrate 120. Will be.

Here, the temperature of the heat treatment for separating the semiconductor substrate 100 is set so as not to exceed the strain point of the base substrate 120. The heat treatment can be performed using an RTA (Rapid Thermal Anneal) apparatus, a resistance heating furnace, a microwave heating apparatus, or the like. The RTA apparatus includes a GRTA (Gas Rapid Thermal Anneal) apparatus and an LRTA (Lamp Rapid Thermal Anneal) apparatus. When the GRTA apparatus is used, the temperature can be set to 550 ° C. or higher and 650 ° C. or lower, and the treatment time can be set to 0.5 minutes or longer and within 60 minutes. In the case of using a resistance heating furnace, the temperature can be 200 ° C. or more and 650 ° C. or less, and the treatment time can be 2 hours or more and 4 hours or less.

The heat treatment may be performed by irradiation with microwaves or the like. Specifically, for example, the semiconductor substrate 100 can be separated by irradiating a microwave of 2.45 GHz at 900 W for about 5 to 30 minutes.

A semiconductor region 129 and a semiconductor region 133 that are damaged by ion beam irradiation treatment or the like remain at the interface related to the separation of the semiconductor layer 124 and the semiconductor substrate 121. This region corresponds to (corresponds to) the embrittled region 104 in the semiconductor substrate 100 before separation. For this reason, the semiconductor region 129 and the semiconductor region 133 contain a lot of hydrogen and contain a lot of crystal defects and voids.

Further, the convex portion 110 exists in a region where the semiconductor substrate 121 is not bonded (specifically, a region corresponding to the edge roll-off region and the chamfered portion of the semiconductor substrate 100). The convex portion 110 includes a semiconductor region 127 to which ions are added, an unseparated semiconductor region 126, and an insulating layer 125. Since the semiconductor region 127 is a part of the embrittled region 104 like the semiconductor region 129 and the like, it contains a lot of hydrogen and a lot of crystal defects and voids. In addition, the semiconductor region 126 has a smaller hydrogen content than the semiconductor region 127 or the like, but has crystal defects caused by implantation of ions or the like.

[Step D: Treatment of semiconductor layer]
In Step D shown in FIG. 5, the surface of the semiconductor layer 124 bonded to the base substrate 120 is planarized to recover crystallinity.

<< Step (D-1): Planarization >>
In the semiconductor region 133 over the semiconductor layer 124 that is in close contact with the base substrate 120, crystal defects are formed due to the formation of the embrittlement region 104 and the separation of the semiconductor substrate 100 in the embrittlement region 104, and flatness is impaired. Therefore, the semiconductor region 133 may be removed by polishing, etching, or the like, and the surface of the semiconductor layer 124 may be planarized (FIG. 4C). Although planarization is not essential, planarization can improve the characteristics of the interface between the semiconductor layer and a layer (eg, an insulating layer) formed later over the semiconductor layer.

Polishing can be performed, for example, by CMP or liquid jet polishing. Here, when the semiconductor region 133 is removed, the semiconductor layer 124 is also polished, and the semiconductor layer 124 may be thinned.

Etching is, for example, reactive ion etching (RIE) method, ICP etching method, ECR (Electron Cyclotron Resonance) etching method, parallel plate type (capacitive coupling type) etching method, magnetron plasma etching method, dual frequency plasma An etching method or a dry etching method such as a helicon wave plasma etching method can be used. Note that the semiconductor region 133 may be removed by using both polishing and etching, and the surface of the semiconductor layer 124 may be planarized.

Further, the surface of the semiconductor layer 124 can be planarized by polishing and etching, and the semiconductor layer 124 can be thinned to an optimum thickness for a semiconductor element to be formed later.

<< Step (D-2): Laser irradiation >>
In addition, the semiconductor region 133 and the semiconductor layer 124 may be irradiated with a laser beam in order to reduce crystal defects and improve flatness.

Note that in the case where the semiconductor region 133 is removed by dry etching before the laser beam irradiation and the surface of the semiconductor layer 124 is planarized, a defect may occur near the surface of the semiconductor layer 124. However, such defects can be repaired by irradiation with the laser beam.

In the laser beam irradiation step, the temperature rise of the base substrate 120 can be reduced, so that a substrate with low heat resistance can be used as the base substrate 120. It is desirable that the semiconductor region 133 be completely melted and the semiconductor layer 124 be partially melted by irradiation with the laser beam. This is because when the semiconductor layer 124 is completely melted, the semiconductor layer 124 is recrystallized due to disordered nucleation in the semiconductor layer 124 in a liquid phase, and the crystallinity of the semiconductor layer 124 is lowered. By partially melting the semiconductor layer 124, crystal growth proceeds from a solid phase portion that is not melted, crystal defects in the semiconductor layer 124 are reduced, and crystallinity is recovered. Note that the semiconductor layer 124 being completely melted means that the semiconductor layer 124 is melted to the interface with the insulating layer 123 to be in a liquid state. On the other hand, the partial melting of the semiconductor layer 124 means that a part (here, the upper layer) of the semiconductor layer 124 is melted to become a liquid phase, and another part (here, the lower layer) maintains the solid phase.

After the laser beam irradiation, the surface of the semiconductor layer 124 may be etched. Note that in this case, the semiconductor region 133 may or may not be etched before the laser beam irradiation. By the etching, the surface of the semiconductor layer 124 can be planarized and the semiconductor layer 124 can be thinned to an optimum thickness for a semiconductor element to be formed later.

<< Step (D-3): Heat treatment >>
After the laser beam irradiation, the semiconductor layer 124 is preferably subjected to heat treatment at 500 ° C. to 650 ° C. By this heat treatment, defects in the semiconductor layer 124 can be further reduced and distortion of the semiconductor layer 124 can be reduced. For the heat treatment, an RTA apparatus, a resistance heating furnace, a microwave heating apparatus, or the like can be used. For example, when a resistance heating furnace is used, heat treatment may be performed at 600 ° C. for about 4 hours.

Note that in the case where a highly heat-resistant substrate is used as the base substrate, it is preferable to perform heat treatment at high temperature in Step D to reduce crystal defects and improve surface flatness. The heat treatment is desirably performed at a temperature of 800 ° C. to 1300 ° C., typically 850 ° C. to 1200 ° C. By performing heat treatment under such a relatively high temperature condition, crystal defects can be sufficiently reduced and surface flatness can be improved.

For the heat treatment, an RTA apparatus, a resistance heating furnace, a microwave heating apparatus, or the like can be used. For example, when a resistance heating furnace is used, heat treatment may be performed at 950 ° C. to 1150 ° C. for 1 minute to 4 hours. Note that the heat treatment for separating the semiconductor substrate can be performed at a high temperature to replace the heat treatment.

The semiconductor layer may be irradiated with a laser beam before or after the heat treatment. Irradiation with a laser beam can repair crystal defects that cannot be repaired by heat treatment. The above description can be referred to for details of laser beam irradiation.

Further, before or after the heat treatment, the semiconductor region above the semiconductor layer may be removed by polishing or etching, and the surface may be planarized. By the planarization treatment, the surface of the semiconductor layer can be further planarized. The above description can be referred to for polishing and etching.

[Step E: Reprocessing of semiconductor substrate]
In step E shown in FIG. 5, the semiconductor substrate 121 is subjected to a regeneration process to produce a recycled semiconductor substrate. Note that Embodiment 1 can be referred to for details of this step.

[Process F: Semiconductor device manufacturing process]
In Step F illustrated in FIG. 5, various semiconductor devices can be manufactured using the SOI substrate obtained through the above-described steps (Step A to Step D).

As described above, the semiconductor substrate 121 is regenerated into the regenerated semiconductor substrate 132. The obtained recycled semiconductor substrate 132 can be reused as the semiconductor substrate 100 in the process A.

As described in this embodiment, the cost for manufacturing an SOI substrate can be reduced by repeatedly using a semiconductor substrate which has been subjected to the regeneration treatment process of one embodiment of the present invention.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a method for manufacturing an SOI substrate including a regeneration treatment step in the case where a semiconductor substrate is repeatedly used as a bond substrate is described. FIG. 6 shows a flowchart of a method for manufacturing an SOI substrate of this embodiment mode.

A bond substrate (semiconductor substrate) used for manufacturing the SOI substrate preferably has a wide defect-free region (DZ).

In the present embodiment, first, a new semiconductor substrate (which has never been used for manufacturing an SOI substrate) is subjected to heat treatment in a non-oxidizing atmosphere (corresponding to step S2 described later). This heat treatment is performed in order to diffuse the oxygen in the semiconductor substrate outward and make the vicinity of the surface a defect-free region. In addition, by this heat treatment, supersaturated oxygen is precipitated as an oxide inside the semiconductor substrate to generate minute crystal defects. Such minute defects due to oxygen precipitates are called BMD (Bulk Micro Defect). The BMD formed inside the semiconductor substrate can function as a gettering sink for a metal element in the manufacturing process of the SOI substrate.

In this specification, the defect-free region (DZ) is not a complete defect-free region, but is used to mean a region where no BMD exists.

By forming a defect-free region in a new semiconductor substrate, the semiconductor substrate can be used a plurality of times without performing high-temperature heat treatment for each regeneration process. Therefore, since the number of high-temperature heat treatments is reduced, it is possible to suppress a decrease in mechanical strength of the semiconductor substrate. In addition, the manufacturing cost of the SOI substrate can be reduced and productivity can be improved. In addition, the semiconductor film of the SOI substrate can be formed from a defect-free region in which oxygen is reduced as compared with the initial semiconductor substrate. Therefore, in the process of manufacturing a semiconductor device such as a transistor from an SOI substrate, generation of BMD in the semiconductor film is suppressed, so that a highly reliable semiconductor device can be manufactured.

Next, the fabrication of the SOI substrate and the regeneration of the semiconductor substrate are repeated (corresponding to steps S4 to S6 described later). Then, after the SOI substrate is manufactured N times, heat treatment in a non-oxidizing atmosphere is performed again (corresponding to step S7 described later).

The number of times that the semiconductor substrate can be reused without high-temperature heat treatment depends on the temperature and time of the heat treatment, the thickness of the defect-free region, the polishing treatment conditions in the regeneration treatment, and the like. For example, when a semiconductor substrate in which a defect-free region has a thickness of about 100 nm is used and the semiconductor substrate regeneration method of one embodiment of the present invention is applied, the polishing amount of the semiconductor substrate in one regeneration process is 1.4 μm. Since the amount of reduction in the thickness of the semiconductor substrate in one regeneration process can be 2.0 μm or less, at least 50 commercially available MCZ single crystal silicon wafers can be obtained without performing the high-temperature heat treatment in step S7. Can be used twice (N ≧ 50).

Hereinafter, a method for manufacturing the SOI substrate of this embodiment mode is specifically described.

<< Step S1: Preparation of Semiconductor Substrate >>
First, a semiconductor substrate to be a bond substrate is prepared. In this embodiment, a silicon substrate is used.

<< Step S2: Heat treatment in non-oxidizing atmosphere >>
Prior to manufacturing the SOI substrate (step S4), the semiconductor substrate is heat-treated in a non-oxidizing atmosphere (step S2).

In order to more reliably form a defect-free region in the surface region of the semiconductor substrate in step S2, it is preferable to prepare a semiconductor substrate having a low oxygen concentration in step S1.

When the concentration of oxygen contained in the semiconductor substrate is low, generation of crystal defects due to oxygen near the surface of the semiconductor substrate is suppressed, so that the defect-free region can be more reliably formed in step S2 and the defect-free region is thickened. It becomes easy. The reliable formation of the defect-free region leads to an improvement in the yield of the SOI substrate. Further, increasing the thickness of the defect-free region leads to reducing the number of times of high-temperature heat treatment for the regeneration process and shortening the processing time with respect to the number of times the semiconductor substrate is reused.

In addition, the BMD in the semiconductor substrate may grow due to repeated heat treatment on the semiconductor substrate, resulting in crystal defects such as dislocations and stacking faults. Therefore, reducing the oxygen concentration of the semiconductor substrate can suppress the generation of crystal defects due to BMD, leading to an increase in the number of times the semiconductor substrate is used and improvement in the quality of the semiconductor film of the SOI substrate.

Specifically, in step S1, it is preferable to prepare a semiconductor substrate whose oxygen concentration does not exceed 2 × 10 ¹⁸ atoms / cm ³ . An example of such a semiconductor substrate is a commercially available CZ single crystal wafer. Further, the oxygen concentration of the semiconductor substrate is preferably 1.8 × 10 ¹⁸ atoms / cm ³ or less, and more preferably 1.4 × 10 ¹⁸ atoms / cm ³ or less. Examples of the semiconductor substrate having an oxygen concentration of 1.4 × 10 ¹⁸ atoms / cm ³ or less include an MCZ single crystal silicon wafer.

The oxygen concentration of the semiconductor substrate can be measured by SIMS (secondary ion mass spectrometry) or infrared spectroscopy (Infrared Absorption Spectroscopy). For example, in infrared spectroscopy, the oxygen concentration may be calculated using a conversion factor of 4.81 × 10 ¹⁷ / cm ² .

The heat treatment in step S2 can be performed in a batch-type heating furnace (including a diffusion furnace). A batch-type heating furnace can process a plurality of substrates at a time and has good temperature controllability.

Specifically, the heat treatment temperature in step S2 is a temperature at which oxygen outward diffusion occurs, preferably 1100 ° C. or higher, and more preferably 1200 ° C. or higher. The upper limit of the heating temperature is a temperature at which the semiconductor substrate is not deformed, and the heat treatment temperature is preferably 1100 ° C. or higher and 1300 ° C. or lower, more preferably 1200 ° C. or higher and 1300 ° C. or lower in consideration of the melting point of silicon of 1415 ° C.

The processing time in the heating furnace (the time for maintaining the temperature of the object to be processed at the processing temperature) is at least 1 hour. This is because when the heating time is short, the outward diffusion of oxygen is not sufficiently performed, and the oxygen concentration in the vicinity of the semiconductor substrate surface becomes high. Considering the effect of heat treatment and productivity, the treatment time is suitably 1 hour or more and 24 hours or less, more preferably 6 hours or more and 20 hours or less.

Further, as the processing gas, a rare gas such as helium or argon, hydrogen, or a mixed gas of a rare gas and hydrogen can be used. From the viewpoint of cost, safety, and controllability of the atmosphere, it is preferable to use argon gas as the processing gas. By using the above-described processing gas, the processing chamber is made a non-oxidizing atmosphere. The flow rate of the aforementioned gases, the more 5 SLM 20 SLM less (8.35atm · ^cm 3 / s or more ^{3.34 × 10 2 atm · cm 3} / s). SLM (standard liter / min) refers to a flow rate (liter) per minute at 1 atm and 0 ° C.

Further, it is preferable that the processing gas does not contain impurities such as nitrogen, carbon, and water. For example, the purity of the processing gas introduced into the heating furnace is 7N (99.99999) or higher, preferably 8N (99.99999999%) or higher, more preferably 9N (99.9999999%) or higher (that is, the impurity concentration is 100 ppb). Hereinafter, it is preferably 10 ppb or less, more preferably less than 1 ppb. The concentration of water contained in the non-oxidizing atmosphere is 0.01 ppb or more and 1% or less, preferably 0.1 ppb or more and 300 ppb or less. By reducing the concentration of impurities contained in the non-oxidizing atmosphere, it is possible to suppress the formation of a non-uniform natural oxide film due to the reaction between the impurities and the semiconductor substrate during heat treatment. The average surface roughness of the surface can be reduced.

The non-oxidizing atmosphere may contain oxygen in an amount of 0.1 ppb to 1%. By performing heat treatment on the semiconductor substrate in such a non-oxidizing atmosphere, an oxide film can be uniformly formed on the semiconductor substrate. The thickness of the oxide film (natural oxide film) formed on the semiconductor substrate is preferably several nm or more and 40 nm or less. If the thickness of the natural oxide film is less than a few nm, the surface of the semiconductor substrate may be roughened during the heat treatment, and if it exceeds 40 nm, the outward diffusion of oxygen from the semiconductor substrate is not efficiently performed. is there. For example, when heat treatment is performed at 1200 ° C. for 16 hours in an argon atmosphere containing 300 ppb of water, a natural oxide film of about 1 to 2 nm is formed on the surface of the semiconductor substrate. When heat treatment is performed at 1200 ° C. for 2 hours in an argon atmosphere containing 1% oxygen gas, an oxide film of about 40 nm is formed on the surface of the semiconductor substrate. If the thickness of the oxide film (natural oxide film) is within the above range, the outward diffusion of oxygen from the semiconductor substrate can be promoted.

<< Step S3: k = 0 >>
In the flowchart of FIG. 6, k indicates the number of times that the SOI substrate manufacturing process is performed using the semiconductor substrate prepared in steps S1 and S2 (k is an integer of 0 or more and N or less, and N is an integer of 2 or more). . Therefore, k = 0 in step S3. In FIG. 6, the semiconductor substrate is heat-treated as a regeneration process once every N times for the manufacturing process of the SOI substrate to reduce crystal defects near the surface of the semiconductor wafer.

<< Step S4: Production of SOI Substrate and Regeneration of Semiconductor Substrate >>
An SOI substrate is manufactured (step A to step D in FIG. 5) and a semiconductor substrate to which one embodiment of the present invention is applied (step E in FIG. 5) is described as an example in the above embodiment.

<< Step S5: Add 1 to k >>
Since step S4 is completed, 1 is added to k in step S5. For example, when the first SOI substrate fabrication is completed in step S4, k = 1 in step S5.

<< Step S6: Has Step S4 been performed N times? >>
The next process differs depending on whether step S4 (production of the SOI substrate) is performed N times (k = N).

When k is smaller than N, there is no crystal defect in the vicinity of the surface of the semiconductor wafer at this time, which causes a defect of the SOI substrate, so that it is not necessary to perform a high-temperature heat treatment for reducing defects as a regeneration process. . Therefore, step S4 is performed after step S6.

Steps S4 to S6 are repeated until k = N in Step S6 (until the SOI substrate is manufactured N times).

If k = N in step S6 (the SOI substrate is manufactured N times), the process proceeds to step S7.

In step S6, the necessity of the heat treatment in step S7 may be determined depending on the thickness of the defect-free region of the semiconductor wafer. The thickness of the defect-free region of the semiconductor wafer can be evaluated by measuring crystal defects formed in the semiconductor wafer. Any method for measuring crystal defects formed on a semiconductor wafer may be used as long as the crystal defects of the semiconductor wafer can be evaluated nondestructively. For example, infrared absorption spectroscopy, infrared interferometry, Raman spectroscopy, cathodoluminescence, and photoluminescence. And a microwave optical transmission attenuation method.

<< Step S7: Heat Treatment in Non-oxidizing Atmosphere >>
The heat treatment in step S7 is a heat treatment for eliminating crystal defects (BMD) due to oxygen precipitates in the semiconductor wafer. By repeating step S4, BMD is generated inside the semiconductor wafer, and the defect-free region of the semiconductor wafer becomes gradually thinner. Therefore, if step S4 is repeated, the vicinity of the surface of the semiconductor wafer cannot be made a semiconductor film of the SOI substrate due to an increase in crystal defects.

Therefore, in step S7, the semiconductor wafer is heat-treated at 1100 ° C. or higher and 1300 ° C. or lower in a non-oxidizing atmosphere. This heat treatment is performed under the condition of outward diffusion of oxygen in the semiconductor wafer, and can be performed in the same manner as in step S2. Therefore, the description of step S2 applies mutatis mutandis for the heat treatment in step S7. Note that the heat treatment in step S2 and step S7 need not be under the same conditions. Moreover, when performing step S7 several times, those heat processing does not need to be the same conditions.

And after performing step S7, it returns to step S3. Here, the number k of manufacturing steps of the SOI substrate is reset to zero. Then, after the SOI substrate is manufactured N times, the heat treatment in step S7 is performed. As long as the semiconductor wafer can be reused, steps S3 to S7 are repeated.

Note that the value of N is not particularly limited. The value of N can be determined by the concentration of oxygen contained in the semiconductor wafer, the thickness of the defect-free region formed in the semiconductor wafer, or the like after the heat treatment shown in step S2 or step S7. Also, the value of N may be different each time step S7 is performed. For example, the first heat treatment in step S7 can be performed after the SOI substrate manufacturing process is repeated 6 times, and then the second heat treatment in step S7 can be performed after the SOI substrate manufacturing process is repeated 4 times.

As described above, heat treatment in a non-oxidizing atmosphere is performed before manufacturing an SOI substrate, and a defect-free region is formed in the semiconductor substrate. The substrate can be used multiple times. Therefore, since the number of high-temperature heat treatments is reduced, it is possible to suppress a decrease in mechanical strength of the semiconductor substrate.

In particular, when the semiconductor substrate regeneration method of one embodiment of the present invention is applied, the amount of polishing in one regeneration process can be reduced, so that a defect-free region can be formed with respect to the number of reuses of a semiconductor substrate. The number of high-temperature heat treatments can be reduced. Therefore, the processing time can be shortened.

For example, when the semiconductor substrate regeneration method of one embodiment of the present invention is applied, the amount of polishing of the semiconductor substrate in one regeneration process is 1.4 μm or less (the amount of reduction in the thickness of the semiconductor substrate in one regeneration process). 2.0 μm or less), depending on the thickness of the defect-free region to be formed and the thickness of the semiconductor substrate, the semiconductor substrate can be used to the limit where it cannot be reused without performing the high-temperature heat treatment in step S7. Is also possible.

Specifically, an SOI substrate is manufactured and a regeneration process of one embodiment of the present invention is repeatedly performed using a semiconductor substrate in which a thickness of a region excluding a defect-free region is 0 μm or more and less than 450 μm, preferably 0 μm or more and less than 100 μm. Thus, the semiconductor substrate can be used to the limit where it cannot be reused without performing the high-temperature heat treatment in step S7.

Here, as the bond substrate, it is preferable to use an MCZ wafer that has been heat-treated in a non-oxidizing atmosphere and has a low oxygen concentration and a wide defect-free region. By adopting such a wafer, step S2 in the present embodiment can be omitted. Then, by applying the semiconductor substrate regeneration method of one embodiment of the present invention, the amount of polishing in the regeneration process can be reduced. Therefore, the semiconductor substrate cannot be reused without performing the high-temperature heat treatment in step S7. Can be used to the limit. That is, a heat treatment process in a non-oxidizing atmosphere is not necessary.

Employing such a wafer and applying one embodiment of the present invention is preferable because capital investment for performing heat treatment in a non-oxidizing atmosphere can be reduced.

As the above-mentioned wafer, for example, an ECAS-Z wafer (product name: EZ-WF, manufactured by Covalent Silicon Corporation), which is a silicon single crystal wafer, is preferably used. The ECAS-Z wafer is an MCZ wafer annealed in an argon atmosphere, and has a low oxygen concentration (0.9 to 1.1 × 10 ⁻¹⁸ atoms / cm ³ ) and a wide defect-free region (100 μm or more). With defective areas).

As described above, by applying one embodiment of the present invention, the amount of polishing of a semiconductor substrate in one regeneration process can be reduced. Therefore, the number of times of regeneration and use of the semiconductor substrate can be increased. it can. In addition, by applying one embodiment of the present invention to a semiconductor substrate which has a defect-free region and the thickness of the region excluding the defect-free region is greater than or equal to 0 μm and less than 450 μm, the defect-free region can be formed. The semiconductor substrate can be used to the limit where it cannot be reused without performing high-temperature heat treatment.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 4)
FIG. 7 illustrates an example of a semiconductor device using the SOI substrate manufactured in the above embodiment.

The semiconductor device illustrated in FIG. 7 includes a transistor 280 which is an n-channel thin film transistor and a transistor 281 which is a p-channel thin film transistor.

The transistor 280 and the transistor 281 are formed over the base substrate 120 with the insulating layer 123 and the insulating layer 122 interposed therebetween. Various semiconductor devices can be formed by combining such a plurality of thin film transistors (TFTs).

Hereinafter, a method for manufacturing the semiconductor device illustrated in FIGS.

First, an SOI substrate is prepared. As the SOI substrate, the SOI substrate manufactured in the above embodiment can be used.

Next, the semiconductor layer is separated by etching to form an island-shaped semiconductor layer 251 and an island-shaped semiconductor layer 252. The semiconductor layer 251 constitutes an n-channel TFT, and the semiconductor layer 252 constitutes a p-channel TFT.

After the insulating layer 254 is formed over the semiconductor layers 251 and 252, the gate electrode 255 is formed over the semiconductor layer 251 through the insulating layer 254, and the gate electrode 256 is formed over the semiconductor layer 252.

Note that an impurity element serving as an acceptor such as boron, aluminum, or gallium or an impurity element serving as a donor such as phosphorus or arsenic is added to the semiconductor layer in order to control the threshold voltage of the TFT. desirable. For example, an impurity element serving as an acceptor is added to a region where an n-channel TFT is formed, and an impurity element serving as a donor is added to a region where a p-channel TFT is formed.

Next, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251, and a p-type high concentration impurity region 259 is formed in the semiconductor layer 252. Specifically, first, the semiconductor layer 252 is covered with a resist mask, an impurity element is added to the semiconductor layer 251, and an n-type low-concentration impurity region 257 is formed in the semiconductor layer 251. As an impurity element to be added, phosphorus, arsenic, or the like may be used. By using the gate electrode 255 as a mask, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251 in a self-aligning manner. Further, a region of the semiconductor layer 251 that overlaps with the gate electrode 255 becomes a channel formation region 258. Next, after the mask covering the semiconductor layer 252 is removed, the semiconductor layer 251 is covered with a resist mask. Then, an impurity element is added to the semiconductor layer 252. As the impurity element to be added, boron, aluminum, gallium, or the like may be used. Here, the gate electrode 256 functions as a mask, and a p-type high concentration impurity region 259 is formed in the semiconductor layer 252 in a self-aligning manner. A region overlapping with the gate electrode 256 of the semiconductor layer 252 becomes a channel formation region 260. Although the method of forming the p-type high-concentration impurity region 259 after forming the n-type low-concentration impurity region 257 has been described here, the p-type high-concentration impurity region 259 may be formed first. it can.

Next, after the resist mask covering the semiconductor layer 251 is removed, an insulating layer having a single-layer structure or a stacked structure including a nitride such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like. Then, the sidewall insulating layer 261 and the sidewall insulating layer 262 in contact with the side surfaces of the gate electrode 255 and the gate electrode 256 are formed by applying vertical anisotropic etching to the insulating layer. Note that the insulating layer 254 is also etched by the anisotropic etching.

Next, the semiconductor layer 252 is covered with a resist mask, and an impurity element is added to the semiconductor layer 251 with a high dose. Thus, the n-type high concentration impurity region 267 is formed using the gate electrode 255 and the sidewall insulating layer 261 as a mask.

After the impurity element activation treatment (heat treatment), an insulating layer 268 containing hydrogen is formed. After the insulating layer 268 is formed, heat treatment is performed at a temperature of 350 ° C. to 450 ° C., so that hydrogen contained in the insulating layer 268 is diffused in the semiconductor layer 251 and the semiconductor layer 252. The insulating layer 268 can be formed by depositing silicon nitride or silicon nitride oxide by a plasma CVD method with a process temperature of 350 ° C. or lower. By supplying hydrogen to the semiconductor layer 251 and the semiconductor layer 252, defects that become trapping centers in the semiconductor layer 251, the semiconductor layer 252, or an interface between them and the insulating layer 254 are effectively compensated. Can do.

After that, an interlayer insulating layer 269 is formed. The interlayer insulating layer 269 may have a single-layer structure or a stacked structure using an insulating film containing an inorganic material such as silicon oxide or BPSG (Boron Phosphorus Silicon Glass), or an insulating film containing an organic material such as polyimide or acrylic. it can. After a contact hole is formed in the interlayer insulating layer 269, a wiring 270 is formed. For the formation of the wiring 270, for example, a conductive film having a three-layer structure in which a low-resistance metal film such as an aluminum film or an aluminum alloy film is sandwiched between barrier metal films can be used. The barrier metal film can be formed using molybdenum, chromium, titanium, or the like.

Through the above steps, a semiconductor device having an n-channel TFT and a p-channel TFT can be manufactured. An SOI substrate used for the semiconductor device of this embodiment can be manufactured at low cost as described in the above embodiment. Therefore, the cost for manufacturing a semiconductor device can be reduced.

Note that in this embodiment, the semiconductor device and the manufacturing method thereof according to FIGS. 7A to 7C are described; however, the structure of the semiconductor device according to one embodiment of the present invention is not limited thereto. The semiconductor device may include a capacitor, a resistor, a photoelectric conversion element, a light-emitting element, and the like in addition to the TFT.

Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

In this example, a result of performing a regeneration process of one embodiment of the present invention on a semiconductor substrate (bond substrate) after a semiconductor layer is separated in manufacturing an SOI substrate is shown.

First, the semiconductor substrate used in this example will be described.

In this embodiment, a rectangular single crystal silicon substrate of 5 inches square is used as the semiconductor substrate. First, the semiconductor substrate was subjected to thermal oxidation treatment in an HCl atmosphere to form a thermal oxide film having a thickness of 100 nm on the substrate surface. The thermal oxidation treatment was performed at 950 ° C. for 9 hours in an atmosphere containing HCl at 3 volume% with respect to oxygen.

Next, the semiconductor substrate was irradiated with an ion beam from the surface of the thermal oxide film using an ion doping apparatus. In this embodiment, plasma is generated by exciting hydrogen gas, ions contained in the plasma are accelerated without mass separation, and the embrittled region is formed in the semiconductor substrate by implanting the accelerated ions into the semiconductor substrate. Formed. The ion doping conditions were an acceleration voltage of 50 kV and a dose of 2.7 × 10 ¹⁶ ions / cm ² .

And the semiconductor substrate was bonded together to the glass substrate through the thermal oxide film. After that, heat treatment at 200 ° C. was performed for 120 minutes, and heat treatment at 600 ° C. was further performed for 120 minutes to separate the thin single crystal silicon layer from the semiconductor substrate in the embrittled region. Thus, an SOI substrate was manufactured and a semiconductor substrate having a convex portion at the peripheral edge was manufactured.

Next, processing for the above-described semiconductor substrate will be described. Hereinafter, three semiconductor substrates subjected to the regeneration process of one embodiment of the present invention are samples A to C, and four semiconductor substrates subjected to a regeneration process different from the regeneration process of one embodiment of the present invention are comparative samples D. This will be described as ~ G.

(Processing performed on samples A to C)
≪Removal of insulating layer≫
First, in order to remove the insulating layer formed so as to cover the semiconductor substrate, the semiconductor substrate was subjected to a wet etching process using a 5% hydrofluoric acid solution. At this time, the liquid temperature was room temperature and the etching time was 300 seconds. The etching amount in this step was 0.1 μm.

≪First step≫
Next, wet etching treatment was performed on the semiconductor substrate from which the insulating layer had been removed using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid in a volume ratio of 1: 2: 10 as an etchant. The nitrite concentration of the etchant was 80 mg / l to 100 mg / l. The nitrous acid concentration was evaluated using a semi-quantitative ion test paper (QUANTOFFIX Nitrite and Nitrite 3000). In the etchant used in this example, hydrofluoric acid has a concentration of 50% by weight (manufactured by Stella Chemifa), nitric acid has a concentration of 70% by weight (manufactured by Wako Pure Chemical Industries, Ltd.), and acetic acid has a concentration of Of 99.7% by weight (manufactured by Kishida Chemical Co., Ltd.) was used. The liquid temperature of the etchant was 30 ° C., and the etching time was 75 seconds. The etching amount in the first step was 0.3 μm.

≪Second process≫
Next, the semiconductor substrate was immersed in PK-LCG407 (manufactured by Parker Corporation), which is an alkaline chemical solution, using a batch type cleaning machine. The liquid temperature was 40 ° C. and the treatment time was 300 seconds.

Then, after immersing and washing in a washing tank filled with pure water, IPA (Isopropyl Alcohol) drying was performed.

≪Third process≫
Then, a CMP process was performed. As the CMP process, a first CMP process with a high polishing rate and a second CMP process with a low polishing rate were performed in this order. The polishing amount in the third step was 1.2 μm.

In the first CMP treatment, polishing cloth, SUBA800M3 (SUBA is a registered trademark) manufactured by Nita Haas Co., Ltd., and silica-based slurry (NP6601, manufactured by Nitta Haas Co., Ltd., diluted 100 times) were used. The slurry flow rate was 185 ml / min, the polishing pressure was 0.01 MPa, the spindle rotation speed was 39 rpm, the table rotation speed was 35 rpm, and the processing time was 160 seconds.

In the second CMP treatment, a polishing cloth, supreme manufactured by Nitta Haas Co., Ltd., and a silica-based slurry (NP8020 manufactured by Nitta Haas Co., Ltd., diluted 20 times) were used. The slurry flow rate was 185 ml / min, the polishing pressure was 0.01 MPa, the spindle rotation speed was 39 rpm, the table rotation speed was 35 rpm, and the processing time was 160 seconds.

(Comparative example)
First, similarly to the configuration example, the removal of the insulating layer and the first step were performed. However, the etching time in the first step was 105 seconds.

Next, it was washed with pure water and dried with a rinser dryer.

Then, the 3rd process was performed like the example of composition. That is, in the comparative example, the second step is not performed.

The reproduction semiconductor substrates of Samples A to C and Comparative Samples D to F manufactured by the above method were observed with an optical microscope.

Moreover, observation with the optical microscope performed photography of the board | substrate peripheral part using optical microscope MX61L by Olympus Corporation. The optical micrograph was taken as a Nomarski image with a magnification of 50 times.

Optical micrographs of the regenerated semiconductor substrates of Samples A to C are shown in FIGS. 8A to 8C, respectively. Moreover, the optical microscope photograph of the reproduction | regeneration semiconductor substrate of comparative sample DG is shown to FIG. 8 (D-1) (D-2) thru | or (F-1) (F-2). Two optical micrographs are shown for one recycled semiconductor substrate as a comparative sample. Specifically, FIGS. 8D-1 and 8D-2 show the results of the comparative sample D. Similarly, FIGS. 8E-1 and E-2 show the comparative sample E and FIG. -1) (F-2) is the result of the comparative sample F and FIGS. 8 (G-1) and (G-2) are the results of the comparative sample G.

Further, the number of unevenness on the regenerated semiconductor substrate was counted by observing with an optical microscope.

The number of unevennesses in the recycled semiconductor substrates of Samples A to C was zero. On the other hand, the number of unevennesses in the recycled semiconductor substrates of Comparative Samples D to G was 20, 19, 22, and 19, respectively.

From the above results, it has been found that a recycled semiconductor substrate manufactured by applying one embodiment of the present invention has very little polishing unevenness and unevenness on the surface of the semiconductor substrate and has good flatness.

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 102 Insulating layer 104 Embrittlement area 110 Convex part 120 Base substrate 121 Semiconductor substrate 122 Insulating layer 123 Insulating layer 124 Semiconductor layer 125 Insulating layer 126 Semiconductor region 127 Semiconductor region 129 Semiconductor region 132 Reproduction semiconductor substrate 133 Semiconductor region 251 Semiconductor layer 252 Semiconductor layer 254 Insulating layer 255 Gate electrode 256 Gate electrode 257 Low concentration impurity region 258 Channel forming region 259 High concentration impurity region 260 Channel forming region 261 Side wall insulating layer 262 Side wall insulating layer 267 High concentration impurity region 268 Insulating layer 269 Interlayer Insulating layer 270 Wiring 280 Transistor 281 Transistor

Claims (4)

To the semiconductor substrate having a damaged area, the first step, a second step and the third step the semiconductor substrate playback method for performing,
The first step includes
A mixture comprising a substance that oxidizes a semiconductor material constituting the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls an oxidation rate of the semiconductor material and a dissolution rate of the oxidized semiconductor material by etching using a liquid, comprising the step of selectively removing the prior destruction wound area,
The second step includes
Using an alkaline solution, and a step of removing the damaged wound area before that were not removed in the first step,
The third step includes
A method for reclaiming a semiconductor substrate, comprising polishing treatment. In claim 1,
The method for reclaiming a semiconductor substrate, wherein the polishing treatment is performed in order of a high polishing rate treatment and a low polishing rate treatment. In claim 1 or claim 2,
The method for regenerating a semiconductor substrate, wherein the mixed solution further contains nitrous acid . In the semiconductor substrate which is reproduced through a reproducing method of a semiconductor substrate according to claims 1 to 3, to form an embrittled region by adding ions,
Via an insulating layer, bonding the said semi-conductor substrate and the base substrate,
By heat treatment, the separated semi conductor substrate, the method for manufacturing an SOI substrate forming the semiconductor layer on the base substrate.