KR19980075848A - Manufacturing method of capacitor using overlay pattern for measuring alignment - Google Patents

Abstract

The present invention relates to a method of manufacturing a capacitor using an overlay pattern for measuring alignment, preparing a semiconductor substrate, forming a first insulating film having a first contact hole at a predetermined interval on the semiconductor substrate, and Selectively removing the first insulating layer between the first contact holes to form a second contact hole, forming a first conductive layer on the entire surface of the semiconductor substrate including the first and second contact holes; Forming a second insulating film having a predetermined interval on the first conductive layer so as to overlap the second contact hole, and forming sidewalls of the second conductive layer on both sides of the second insulating film and on both sides of the first insulating film on which the first contact holes are formed. And removing the second insulating film and forming a dielectric film and a third conductive layer on sidewalls of the first conductive layer and the second conductive layer. All.

Description

Manufacturing method of capacitor using overlay pattern for measuring alignment

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor using an overlay pattern for measuring alignment.

Generally, several masks are needed to make a semiconductor device. After forming a mask on a wafer, it is necessary to check whether the pattern in the lower layer is aligned correctly when exposing using a stepper. need.

An overlay pattern is formed for such confirmation. The overlay pattern forms an overlay measurement pattern in a scribe lane located between main chips on a wafer to measure the degree of alignment of the semiconductor device.

In this way, the Box-In-Box type is often used to measure overlay between two layers. The feature of the box-in-box type is to locate the hollow outer box and the inner box smaller than the outer box in the outer box to measure the alignment accuracy between the two layers.

In addition, there is a method of forming and measuring an inner box on the upper layer of the outer box.

The storage node forming method of the capacitor using the overlay pattern for measuring the degree of alignment may be classified into three types, such as a stack type, a pin type, and a trench type.

When the patterns are patterned by the photo process, KLA's overlay pattern is automatically measured when measuring the overlay between the memory contact hole and the storage node. .

Hereinafter, referring to the accompanying drawings, a conventional method for forming an overlay pattern for measuring alignment is as follows.

1A to 1C are cross-sectional views illustrating a method of forming an overlay pattern for measuring general alignment.

First, as shown in FIG. 1A, a hollow outer box 2 is formed in a predetermined region on the semiconductor substrate 1. In this case, the outer box 2 is a first overlay measurement target for measuring the degree of alignment using the film in the preceding process.

Subsequently, as shown in FIG. 1B, a film 3 is formed on the entire surface of the semiconductor substrate 1 including the outer box 2, and a photoresist is formed on the film 3. 4) Apply.

As shown in FIG. 1C, the photoresist 4 is patterned to have a smaller area than the outer box 2 by an exposure and development process to form an inner box 4a.

Therefore, the overlay pattern for measuring the degree of alignment with the outer box 2 and the inner box 4a is formed.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor using a conventional overlay pattern for measuring alignment.

First, as shown in FIG. 2A, the first oxide film 12 is formed on the semiconductor substrate 11, and the first photoresist 13 is coated on the first oxide film 12, followed by exposure and development. The first photoresist 13 is patterned by the process.

Subsequently, the contact hole 14 is formed by selectively removing the first oxide layer 12 so that the surface of the semiconductor substrate 11 is partially exposed using the patterned first photoresist 13 as a mask.

As shown in FIG. 2B, the first photoresist 13 is removed, and the first polysilicon 15 is formed on the entire surface of the semiconductor substrate 11 including the contact hole 14. The second oxide film 16 is formed on the entire surface of the silicon 15.

Subsequently, after the second photoresist 17 is coated on the second oxide film 16, the second photoresist 17 is patterned by an exposure and development process.

In this case, the patterned second photoresist 17 is an inner box 14a region of the overlay pattern for measuring alignment.

As shown in FIG. 2C, an etch back is formed on the entire surface of the second oxide layer 16 so that the surface of the first polysilicon 15 is exposed using the patterned second photoresist 17 as a mask. The process is performed to form the second oxide film pattern 16a.

In this case, although not shown in the drawing, the second oxide layer 16 remains inside the contact hole 14, and the remaining second oxide layer 16 is an outer box 12 of the overlay pattern for alignment measurement. Area.

As shown in FIG. 2D, the second photoresist 17 is removed, second polysilicon is formed on the entire surface of the semiconductor substrate 11 including the second oxide layer pattern 16a, and an etch back process is performed. The second polysilicon sidewall 18 is formed on both sides of the second oxide layer pattern 16a.

At this time, the second polysilicon sidewall 18 is also formed on the first polysilicon 15 on both sides of the first oxide layer 12 having the contact hole 14 formed therein.

As shown in FIG. 2E, the second oxide layer pattern 16a is removed by a wet etching process to form a storage node of a capacitor including the first polysilicon 15 and the second polysilicon sidewall 18. do.

Since the process is not shown in the drawings, a dielectric film is formed on the entire surface of the semiconductor substrate including the strip node, and a plated electrode is formed on the dielectric film to form a capacitor.

However, in the conventional method of forming an overlay pattern for measuring the degree of alignment, there are the following problems.

That is, the oxide layer is removed by wet etching to form the storage node of the capacitor. At this time, when the polysilicon is formed on the entire surface of the oxide film or the etchback process so that the polysilicon remains only on both sides of the oxide film, it is dropped to the polysilicon during the wet etching of the oxide to cause particles.

An object of the present invention is to provide a method of manufacturing a capacitor using an overlay pattern for measuring the degree of alignment so that polysilicon has adhesion to a substrate during oxide wet etching.

1A to 1C are cross-sectional views of a process of forming a pattern for measuring a general alignment degree

2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor using a conventional alignment measurement pattern.

3A to 3E are cross-sectional views illustrating a method of manufacturing a capacitor using a pattern for measuring alignment according to the present invention.

* Description of the symbols for the main parts of the drawings *

21 semiconductor substrate 22 first oxide film

23: first photoresist 24: first contact hole

25: second contact hole 26: first polysilicon

27: second oxide film 28: second photoresist

29: second polysilicon sidewall

According to an aspect of the present invention, there is provided a method of manufacturing a capacitor using an overlay pattern for measuring alignment, according to an embodiment of the present invention, comprising: preparing a semiconductor substrate, and a first insulating layer having a first contact hole at a predetermined interval on the semiconductor substrate. Forming a second contact hole by selectively removing a first insulating film between the first contact holes, and forming a second contact hole on the entire surface of the semiconductor substrate including the first and second contact holes. Forming a second insulating film having a predetermined gap on the first conductive layer so as to overlap the second contact hole, and forming both sides of the second insulating film and both sides of the first insulating film having the first contact hole formed thereon. Forming a second conductive layer sidewall, and removing the second insulating layer and forming a dielectric layer and a third conductive layer on the sidewalls of the first and second conductive layers. It is characterized by forming.

Hereinafter, a method of manufacturing a capacitor using an overlay pattern for measuring alignment according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are cross-sectional views illustrating a method of manufacturing a capacitor using an overlay pattern for measuring alignment according to the present invention.

As shown in FIG. 3A, the first oxide film 22 is formed on the semiconductor substrate 21, and the first photoresist 23 is coated on the first oxide film 22. The first photoresist 23 is patterned.

Subsequently, the first oxide layer 22 is selectively removed so that the surface of the semiconductor substrate 21 is exposed using the patterned first photoresist 23 as a mask to form first and second contact holes 24 and 25. ).

In this case, the widths of the first and second contact holes 24 and 25 are different from each other, and the width of the first contact hole 24 is wider than that of the second contact hole 25.

As shown in FIG. 3B, the first photoresist 23 is removed, and the first polysilicon 26 is disposed on the entire surface of the semiconductor substrate 21 including the first and second contact holes 24 and 25. The second oxide layer 27 is formed on the entire surface of the first polysilicon 26.

At this time, since the second contact hole 25 is narrow, the first polysilicon 26 is completely filled.

Subsequently, after the second photoresist 28 is coated on the second oxide layer 27, the second photoresist 28 is patterned to overlap the second contact hole 25 by an exposure and development process.

In this case, the patterned second photoresist 28 is an inner box region of the overlay pattern for measuring alignment.

As shown in FIG. 3C, an etch back is formed on the entire surface of the second oxide layer 27 to expose the surface of the first polysilicon 26 using the patterned second photoresist 28 as a mask. The process is performed to form the second oxide film pattern 27a.

In this case, although not shown in the drawing, a second oxide layer 27 remains inside the first contact hole 24, and the remaining second oxide layer 27 is an outer box region of the overlay pattern for measuring alignment. to be.

As shown in FIG. 3D, the second photoresist 28 is removed, second polysilicon is formed on the entire surface of the semiconductor substrate 21 including the second oxide layer pattern 27a, and an etch back process is performed. Thus, second polysilicon sidewalls 29 are formed on both side surfaces of the second oxide layer pattern 27a.

At this time, a second polysilicon sidewall 29 is also formed on the first polysilicon 26 on both sides of the first oxide layer 23 on which the first contact hole 24 is formed.

As shown in FIG. 3E, the second oxide layer pattern 27a is removed by a wet etching process to form a storage node of a capacitor including the first polysilicon 26 and the second polysilicon sidewall 29. do.

Since the process is not shown in the drawings, a dielectric film is formed on the entire surface of the semiconductor substrate including the strip node, and a plated electrode is formed on the dielectric film to form a capacitor.

As described above, in the method of manufacturing the capacitor using the overlay pattern for measuring alignment according to the present invention, a contact hole is formed at the lower end of the inner box, and polysilicon is formed inside the contact hole, thereby contacting the substrate. When the oxide film is wet etched, it is possible to prevent the polysilicon and the substrate from falling off.

Claims (5)

Preparing a semiconductor substrate; Forming a first insulating film having a first contact hole at regular intervals on the semiconductor substrate; Selectively removing a first insulating layer between the first contact holes to form a second contact hole; Forming a first conductive layer on an entire surface of the semiconductor substrate including the first and second contact holes; Forming a second insulating film having a predetermined interval on the first conductive layer so as to overlap the second contact hole; Forming sidewalls of the second conductive layer on both sides of the second insulating layer and on both sides of the first insulating layer on which the first contact holes are formed; And removing the second insulating film and forming a dielectric film and a third conductive layer on sidewalls of the first conductive layer and the second conductive layer, wherein the second insulating layer is formed. Way. The method of claim 1, When the first conductive layer is formed on the entire surface of the semiconductor substrate including the first and second contact holes, the first conductive layer is completely filled in the second contact hole. Method of manufacturing a capacitor. The method of claim 1, The second insulating film is a manufacturing method of a capacitor using the overlay pattern for measuring the alignment level, characterized in that the inner box area in the overlay pattern for measuring the alignment. The method of claim 1, And a second insulating film also remains inside the first contact hole when the second insulating film is formed, so that the second insulating film is an outer box region in the overlay pattern for measuring alignment. The method of claim 1, A method of manufacturing a capacitor using an overlay pattern for alignment measurement, characterized in that the width of the second contact hole is smaller than the first contact hole.