KR19980075614A - Phase Extraction Device for Orthogonal Frequency Division Multiplexing Receiving System - Google Patents

Abstract

The present invention relates to an OFDM system, and more particularly to an OFDM system in which an OFDM transmission signal is transmitted by IFFT-transforming only an information signal without inserting a synchronous signal separately, and an orthogonal frequency division The present invention relates to a phase detection apparatus of a multiple reception system, and more particularly, to a phase detection apparatus of a multiple reception system, in which N complex symbols subjected to FFT processing are input in parallel and absolute values of real and imaginary components Im and Im of the complex symbol are obtained, A value calculation unit 60; A delay register (62) for delaying the parallel output absolute values by a predetermined number of clocks and outputting them in parallel; A subtractor 64 for subtracting the output value of the absolute value calculator 60 from the output value of the delay register 62 and outputting it in parallel; And an adder 66 for adding all the N values output from the subtracter 64 in parallel and outputting a sum value PS. The present invention monitors the sum value PS by FFT processing The phase synchronization can be extracted and the recovered signal can be obtained by tracking until the sum value (PS) becomes zero, so that the waste can be solved due to a significant subchannel occupied by the synchronization signal. In addition, there is an effect that the synchronization acquisition processing time can be shortened by parallel processing of symbol signals in units of blocks.

Description

Phase Extraction Device for Orthogonal Frequency Division Multiplexing Receiving System

The present invention relates to an Orthogonal Frequency Division Multiplexing (OFDM) system, and more particularly to an OFDM system in which only an information signal is subjected to inverse fast fourier transform (IFFT) The present invention relates to a phase extraction apparatus for an orthogonal frequency division multiplexing (OFDM) receiving system that transmits a transmission signal and detects a synchronization after a fast fourier transform (FFT) is performed in a receiving system.

In general, the transmission signal of the high definition television (HDTV) of the ground simultaneous broadcasting system uses the VHF / UHF band of strong directivity. Therefore, not only direct waves from the transmission side arrive at the reception side, but also multi-channel transmission, in which delayed reflected waves due to buildings nearby are also reached, occurs. In particular, as the delay time of the reflected wave is larger than the transmission period of the symbol, the interference phenomenon between adjacent symbols occurs severely. Such inter-symbol interference is known to greatly increase the detection error rate in decoding. So far, several researches have been made to prevent interference between symbols, and the contents are divided into the following two. The first method is to increase the symbol period in the time domain to get rid of the interference, and the second method is a method to make proper channel compensation in the transmitter or receiver. In the former case, there is a merit of simple hardware configuration, but there is a disadvantage in that the symbol rate is reduced, and in the case of digital HDTV broadcasting requiring a high data rate, such a method is not applicable. On the other hand, in the latter case, the system configuration is possible without decreasing the transmission rate, but the complicated channel equalizer must be used at the receiving side.

The orthogonal frequency division multiplexing modulation (OFDM) is a modulation scheme that does not reduce the transmission rate and is less influenced by the multipath transmission. In the OFDM scheme, symbol streams input in series are converted into a parallel form of N blocks, and then each symbol is modulated with mutually orthogonal carriers, and then the symbols are added and transmitted. Accordingly, a plurality of symbols are transmitted at the same time, and the symbol period is increased accordingly. The signal period of OFDM is increased by the number of subchannels through which the symbol is transmitted, thereby reducing inter-symbol interference in multi-channel transmission with delayed signals. Since the OFDM scheme uses a plurality of subcarriers to increase the symbol period, demodulation of the OFDM signal is performed for each subchannel. Therefore, as the number of subchannels increases, the structure of the receiver becomes more complicated than that of the conventional single carrier method, and a technique of simplifying the structure of the OFDM receiver is very important.

On the other hand, the advantage of the OFDM scheme is that the symbol transmission time can be increased by using the multi-carrier, which is relatively insensitive to the multi-path interference signal, and the performance degradation is small for a long time echo signal . Also, since the existing signals have strong characteristics, they have little influence on the cochannel interference. Therefore, a single frequency network (SFN) can be constituted by these characteristics. Here, SFN means that one broadcast broadcasts the whole country at one frequency, and at this time, the same channel interference becomes worse. Therefore, since OFDM is strong in the same channel, it is possible to efficiently utilize limited frequency resources by configuring SFN network. In addition, OFDM can increase the bandwidth efficiency by making the spectrum of the signal close to the square as compared with the conventional digital modulation technique. This is because the data rate of the modulated data is relatively low, so that the spectrum of the signal modulated by each carrier has a very narrow transition bandwidth, and the OFDM signal added thereto can also maintain a narrow transition bandwidth.

As described above, since the OFDM scheme modulates signals in the respective parallel channels and transmits the summed signals, independent sub-carriers corresponding to the number of parallel channels are required. The sub-carriers maintain mutual orthogonality in the frequency domain, Mutual motivation must be achieved. Thus, in an implementation of an OFDM transceiver, an increase in the number of parallel subchannels causes an increase in the hardware complexity of the OFDM transceiver.

However, if the system is digitized, such a decoding process can be implemented in a single Fast Fourier Transform (FFT) structure. Thus, it is possible to implement hardware in a simple manner. Recently, a digital modulation- Broadcasting was adopted as the transmission method of high-definition television.

Here, the OFDM scheme will be described as follows. FIG. 1 is a conceptual diagram for explaining the OFDM modulation principle. The transmitting end is composed of a serial-to-parallel converter 1, a fast Fourier inverse transformer chip (IFFT) 2 and a parallel-to-serial converter 3. N represents the number of carriers. When the transmission data is serially input, the serial-to-parallel conversion unit 1 converts the parallel data into parallel data, and the parallel data is input to the IFFT (2) fh to perform an inverse Fourier transform and the IFFT signal is serial- And transmitted. Here, a protection interval is inserted between consecutive symbols to eliminate intersymbol interference due to multipath.

FIG. 2 is a block diagram of an OFDM modulator. The basic theory of OFDM modulation is to transmit a narrowband signal orthogonal to each other. To give a complex QAM signal to each single carrier, the serial data of length Ts is divided into N signals in the time domain. Each signal forms a complex signal and is modulated by each carrier. That is, in the QAM modulation, each complex symbol ai input in series is parallelized in N stages and multiplied by signals orthogonal to each other, and is expressed by Equation (1).

[Equation 1]

Where T _A is the sampling period of the complex carrier. If the carrier signals are orthogonal to each other, the following equation (2) is satisfied.

&Quot; (2) "

Therefore, considering this fact, the sum signal is expressed by the following equation (3).

&Quot; (3) "

The summed symbol length T _S and the sampling period T _A are selected so as to satisfy the following equation (4).

&Quot; (4) "

Thus, finally, the sum signal of the following equation (5) is obtained.

&Quot; (5) "

Referring to Equation (5), it can be seen that the equation is the same as the N-point IFFT. Therefore, OFDM modulation can be implemented simply by IFFT.

FIG. 3 is a diagram illustrating a time-domain change of a signal to which OFDM is applied. Referring to an OFDM signal in a time domain, N symbol signals transmitted on a single carrier are transmitted on N carriers at a time. Therefore, the transmission time of each symbol is subcarrier (N). The increase of the symbol time has a property of being strong in multipath, but it is difficult to implement the receiving side hardware since N carriers are used. However, as we have seen, the IFFT-modulated signal can be simply demodulated using FFT.

FIG. 4 is a diagram illustrating a frequency domain change of a signal to which OFDM is applied. Referring to an OFDM signal in a frequency domain, each carrier component is summed to show a smooth frequency characteristic, and exhibits sharp characteristics in a side band.

On the other hand, in the OFDM system, the N symbols are subjected to IFFT conversion in units of one block, and the original information is restored by transmitting the block by block and performing FFT conversion on the same block on the receiving side. Therefore, since the conventional synchronous detection method inserts a synchronous signal for each block and transmits the synchronous signal together with the information signal, there is a problem that a significant sub-channel occupied by the synchronous signal wastes resources required for channel and system implementation.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an OFDM receiving system for detecting synchronization by using only OFDM signal characteristics by modulating only valid data without inserting a synchronization signal for each block separately, And to provide a phase extraction apparatus of the present invention.

In order to achieve the above object, the present invention provides a method for extracting a phase by receiving a modulated OFDM reception signal without inserting a synchronization signal in a block unit, the method comprising: receiving N complex symbols FFT- A delay register for delaying a value outputted in parallel from the absolute value calculation section by a predetermined clock and outputting the output value of the absolute value calculation section by subtracting the output value of the absolute value calculation section from the output value of the delay register, And a summation unit for summing up the difference values of the N complex symbols output in parallel from the subtraction unit and outputting the result.

FIG. 1 is a conceptual diagram for explaining a modulation principle of Orthogonal Frequency Division Multiplexing (OFDM)

2 is a block diagram of an OFDM modulator,

3 is a diagram illustrating a time domain change of a signal to which OFDM is applied,

4 is a diagram illustrating a frequency domain change of a signal to which OFDM is applied,

5 is a block diagram of an OFDM receiver,

6 is a block diagram of a phase extraction unit of an OFDM receiver according to the present invention;

7 is a graph showing the output signal of the phase extraction unit of FIG.

Description of the Related Art [0002]

60: absolute value calculation unit 62: delay register

64: subtractor 66: adder

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a description will be given of a method of decoding an OFDM signal in order to facilitate understanding of the present invention. Assuming that the complex symbol a _{i, j} is a symbol transmitted from the i th time slot to the j th subchannel, the OFDM transmission signal Si (t) of the i th time slot can be expressed by Equation (6).

&Quot; (6) "

Where N is the number of subchannels of OFDM and Tsym is the period of one time slot. When this transmission signal is demodulated, the symbol a _{i, j} is detected from Equation (1) using the orthogonality of each subcarrier as shown in Equation (6).

&Quot; (7) "

As shown in Equation (7), since the subcarriers are generated for each subchannel in the OFDM receiver, the subcarriers are complexly multiplied and integrated and decoded. However, if the OFDM reception signal is sampled and the decoding process of Equation (7) is performed by a digital technique, the integration operation can be eliminated and the multiplication operation can also be reduced. Here, the symbol a _{i, j} is detected with the sampling period Tsym / N, as shown in the following equation (8).

&Quot; (8) "

As can be seen from Equation (8), the OFDM reception signal can be sampled and then DFT-transformed to decode the transmission symbol. Therefore, if a receiver is implemented using an FFT chip, the multiplication operation in the reception process can be reduced and orthogonality of each subcarrier can be maintained.

5 is a block diagram of a general orthogonal frequency division multiplexing reception system. The OFDM reception system is composed of a serial-parallel conversion unit 5, an FFT chip 6, and a parallel-to-serial conversion unit 7.

The serial-to-parallel converter 5 receives the OFDM reception signal input as a bit stream and outputs 2N bits in parallel. The FFT chip 6 receives the first input bit as a real component and the second input bit as a The complex S / N converter 7 performs Fourier transform on N complex symbols constituted by constructing one complex symbol by using imaginary components, and the parallel / serial converter 7 receives the N complex symbols inverse Fourier transformed in parallel, do.

Meanwhile, most digital communication systems including digital TVs transmit a series of sync signals together with data for frame synchronization. Since the acquisition of frame synchronization is the first operation performed on data streams in the baseband signal processing, the acquisition of synchronization should be designed to exhibit performance above a certain level even when noise or channel distortion is severe. Generally, the transmission format of the synchronous signal can be divided into a synchronous word system and a frame marker system. The synchronization word is transmitted in the header of the data in the transmission of the data having the non-periodicity such as the burst transmission, while the marker is transmitted in the frame in the frame with the data in the system in which the data is repeatedly transmitted at a constant period. The basic search algorithm used to acquire the synchronous signal includes a threshold based algorithm that determines similarity between the input data and the reference synchronous signal for each sample and determines the synchronous signal as a synchronous signal when the value exceeds a predetermined value, And a compare based algorithm that finds a delay value that maximizes the value in one frame.

First, the principle of synchronous detection of an OFDM signal, which is a core of the present invention, will be described.

In the transmitting side, an information signal having a signal size of +1 or -1 is N complex symbols and the transmitted block is subjected to an FFT from the first symbol of the block on the receiving side, An information signal is obtained. However, if the receiving side regards the symbols other than the first symbol of the time slot as one block and performs FFT processing, a signal of a different size than the original information signal size +1 or -1 is obtained. Thus, if the absolute value of the two symbols is obtained for each block interval, and the difference is 0, the presently recovered signal can be regarded as correct. As shown in Fig.

&Quot; (9) "

In Equation 9 Re _{i, j} is i and the real component of the j-th symbol of the second block, Im _{i, j} is the imaginary component of the j-th symbol of the i-th block, Re _{i-1, j} is i-1 th _{1, j} is the imaginary component of the jth symbol of the (i-1) th block.

If the noise component mixed in the received symbol has a Gaussian distribution, the average of the Gaussian distribution becomes zero, so that it can be expressed as a discrete sum as shown in Equation (9). If the absolute value of each symbol is obtained by extracting the j-th symbol of i-th block and the j-th symbol of i-1-th block, The value will be 0, and if the sync is off, the PS value is probably not zero.

6 is a block diagram of a phase extraction apparatus of the OFDM reception system according to the present invention. The phase extraction apparatus includes an absolute value calculation unit 60, a delay register 62, a subtraction unit 64, 66). The absolute value calculator 60 receives the F complex processed N complex symbols in parallel and obtains the absolute values of the real component Re and the imaginary component Im of the complex symbol and outputs them to the delay register 62. The delay register 62 delays the parallel output absolute values one clock at a time, and outputs the parallel output to the subtractor 64 in parallel. The subtractor 64 subtracts the output value of the absolute value calculator 60 from the output value of the delay register 62 and outputs the subtracted value to the adder 64 in parallel. The adder 66 adds all the N values output in parallel from the subtractor 64 and outputs the sum PS.

Next, the operation and effect of the present invention configured as described above will be described in detail.

The phase detector receives the FFT values of the N complex symbols output from the FFT chip in an absolute value calculator. The first bit of the complex symbol is a real component and the second bit is an imaginary component. The real component and the imaginary component of each complex symbol are obtained as absolute values through respective absolute value calculators. That is, the real component Re, which is the first bit of the complex symbol, is input to the first absolute value calculator 60-1, and after the absolute value is taken, it is delayed by one clock through the first delay register 62-1, (64-1). The imaginary component Im, which is the second bit of the complex symbol, is input to the second absolute value calculator 60-2. After the absolute value is taken, it is delayed by one clock through the second delay register 62-2, And output to the subtractor 64-2. The remaining 2N-2 absolute value calculators and delay registers also obtain the absolute value of each complex symbol, delay it by one clock, and output it to each subtractor.

Then, each of the subtractors 64-1 to 64-2N subtracts the output values of the respective absolute value calculators 60-1 to 60-2N from the output values of the delay registers 62-1 to 62-2N, And outputs the value SYNC obtained by summing the output values of all subtractors through the adder 66. [ Here, the output values of the respective delay registers correspond to the absolute value Re _{i, j} | of the i-th block and the imaginary absolute value Im _{i, j} | _, and the output values of the absolute value calculator correspond to the real number i- Corresponds to the absolute value | Re _{i-1, j} | and the imaginary absolute value Im _{i-1, j} |.

Now, a process of detecting a phase so as to perform FFT processing according to synchronization when data is transmitted only without inserting a synchronization signal will be described.

First, in a 2N information signal having a signal amplitude of +1 or -1 on the transmission side, N first complex symbols are formed by using a real number component as a first bit and an imaginary component as a second bit, And IFFT-processed, and then the OFDM modulated signal is transmitted by serial conversion. On the receiving side, when the FFT is performed from the first symbol of the block to the block, the original information signal having the size of +1 or -1 can be obtained. But. If FFT processing is performed from a symbol other than the first symbol of the block, a signal having a size different from that of the original information signal is obtained.

Here, a description will be made of a process of detecting phase, for example, in a case where FFT processing is performed in an unsynchronized manner.

[Table 1]

The transmission stream on the transmitting side

The first block symbol The second block symbol ... a _1,1 a _1,2 a _1,3 ... a _{1, N-1} a _{1, N} a _2,1 a _2,2 a _2,3 a _2,4 ... a _{2, N} ...

The transmission symbol a _{i, j} subjected to IFFT processing on the transmitting side is an inverse Fourier transformed symbol with two bits of data as one symbol. The transmission symbols a _1,1 ~ a _{1, N} of the first block are transmitted and the transmission symbols a _2,1 ~ a _{2, N} of the second block are subsequently transmitted without a synchronization signal for distinguishing the blocks. Let this time, the two symbols of the first transport block during a _{1,1 1,2} ~a that two symbols are transmitted to the receiving side from a Loss _1,3. Then, the receiving side performs the FFT processing on a block-by-block basis, so that N complex symbols, that is, a _1,3 to a _2,2 are regarded as one block, and a _{2, 3} , Errors that are regarded as blocks. Therefore, in the absolute value calculation unit, a _1,3 to a _2,2 are input in parallel, and the absolute values of the real and imaginary components are obtained and outputted, and then the next block a _{2, 3} , And outputs it in parallel. When the real / imaginary components of a _1,3 to a _{2,2 that} are input first through the delay register 62 are delayed by one clock and outputted, the subtractor 64 subtracts the output of the delay register 62 from a It subtracts the _1,3-real / imaginary absolute value of the output value of a _{2,3 3,2} ~a the absolute value calculation unit 60 from the real / imaginary absolute value of a _2,2, respectively. The value (PS) obtained by summing the 2N values thus subtracted will have a value larger than '0' as well. Because the exact block is not set, the FFTed complex symbol is Value. ≪ / RTI > Here, if a sum PS (PS) is plotted according to how many symbols are out of the block, the result is as shown in FIG.

As shown in FIG. 7, when the block is composed of N symbols and the synchronization is the same and the reception side sets the same block as the transmission side block, the sum value is '0'. However, since the synchronization does not coincide, the receiver has an A value when it is out of the N / 4 symbol, a B value which is the highest value when the N / 2 symbol is out, and a C value when it is out of the 3N / 4 symbol. That is, it continues to increase until it deviates from the N / 2 symbol of the block, and has the highest value when the N / 2 symbol goes off.

Therefore, the sum value can be monitored to find out how much the synchronization phase is distorted.

As described above, instead of a method of inserting a sync signal for each block, an OFDM signal transmitted by IFFT processing only an information signal is stored in a memory, FFT processing is performed on symbols as much as a block size, and the sum value (PS) Since it is possible to acquire the recovered signal from the correct sync by tracking until the sum value (PS) reaches 0, it is possible to solve the waste due to the significant subchannel occupied by the sync signal, The symbol acquisition processing time can be shortened.

Claims (4)

An orthogonal frequency division multiplexing (OFDM) system for transmitting an OFDM signal by performing inverse fast Fourier transform (IFFT) on an information signal only without inserting a synchronization signal, and detecting a synchronization using a signal obtained by a fast Fourier transform In the system, An absolute value calculator 60 for receiving N FFT-processed complex symbols in parallel and obtaining absolute values of a real component Re and an imaginary component Im of the complex symbol and outputting them in parallel; A delay register (62) for delaying the parallel output absolute values by a predetermined number of clocks and outputting them in parallel; A subtractor 64 for subtracting the output value of the absolute value calculator 60 from the output value of the delay register 62 and outputting it in parallel; And an adding unit (66) for adding all the N values output from the subtracting unit (64) in parallel and outputting a summation value (PS). 2. The phase extraction apparatus of claim 1, wherein the absolute value calculator (60) comprises 2N absolute value calculators (60-1 to 60-2N) connected in parallel. The delay register according to claim 1, wherein the delay register (62) delays the input data by one clock while the 2N registers (62-1 to 62-2N) are arranged in parallel, System phase extraction device. The phase extraction apparatus of claim 1, wherein the subtractor (64) comprises 2N subtractors in parallel.