KR100230847B1 - Orthogonal frequency division multiplexing receiving system - Google Patents

Abstract

The present invention relates to an OFDM system, comprising: a serial-to-parallel converter (50) for receiving an OFDM modulated signal that is modulated for each block consisting of N symbols and inputted in series and converted in parallel; A first FFT chip (51) which receives a first group (D _{1 to} D _N ) in parallel from the serial-to-parallel conversion unit (50) and obtains a phase value (y) by performing N-point FFT processing; A first phase extractor 52; A first signal converter 53; A _N- point FFT process is performed on the N / 2 group (D _{N / 2 to} D _{N / 2 + (N-1)} ) in parallel from the serial-to-parallel converter 54 to obtain a reference phase value y '. Two FFT chips 54; A second phase extractor 55 for calculating a reference phase value PS '; A second signal converter 56; A synchronization signal generator 57 for outputting a synchronization detection signal by comparing the phase value y of the first signal converter 53 and the reference phase value y 'of the second signal converter 56; A switching unit (58) which selects and outputs a group compensated by the number of symbols which are twisted according to the synchronization detection signal among a plurality of groups provided from the serial-to-parallel conversion unit (50); According to an embodiment of the present invention, a third FFT chip 59 outputting an OFDM demodulated signal by performing FFT processing on a compensated group provided from the switching unit 58 is performed. After processing, there is an effect of restoring the OFDM received signal by detecting a lost synchronization.

Description

Orthogonal Frequency Division Multiplexing Receiving System

The present invention relates to an orthogonal frequency division multiplexing (OFDM). In particular, only an information signal is inverse fast Fourier transform (IFFT) without inserting a synchronization signal separately in units of blocks. OFDM transmission signal, and the receiving system receives a fast Fourier transform (FFT) to obtain a phase signal and a synchronization detection signal, recovers false synchronization, and restores an OFDM modulation signal. To a receiving system.

In general, a transmission signal of a high definition television (HDTV) of a terrestrial simultaneous broadcasting method uses radio waves in a VHF / UHF band having strong straightness. Therefore, multipath transmission occurs in which not only the direct wave from the transmitting side reaches the receiving side but also the delayed reflected wave by the surrounding buildings or the like. In particular, as the delay time of the reflected wave is larger than the transmission period of the symbol, interference between adjacent symbols occurs more severely. Such interference between symbols is known to greatly increase the detection error rate during decoding. Thus, various studies have been made to prevent the interference between symbols. The contents are divided into the following two types. The first method is to increase the symbol period in the time domain to deviate from the interference, and the second method is a method for appropriate channel compensation in the transmitter or receiver. In the former case, the hardware configuration is simple, but the symbol rate is reduced. In the case of digital HDTV broadcasting requiring a high rate, such a method is difficult to apply. On the other hand, in the latter case, the system configuration can be performed without reducing the transmission rate, but there is a disadvantage in that a complicated channel equalizer must be used at the receiving side.

By taking advantage of this method, it is proposed that the orthogonal frequency division multiplexing (OFDM) is proposed as a modulation technique that does not reduce the transmission rate and is less affected by multipath transmission. The OFDM method converts a serially input symbol string into a parallel form of N blocks, modulates each element symbol into a carrier having mutual orthogonality, and then adds and transmits each element symbol. Therefore, several symbols are transmitted at the same time, thereby increasing the symbol period. The signal period of OFDM may be increased by the subchannel through which symbols are transmitted, thereby reducing interference between symbols in multipath transmission with delayed signals. However, since the OFDM method uses a plurality of subcarriers to increase the symbol period, the demodulation of the OFDM signal is performed for each subchannel. Therefore, as the number of subchannels increases, the structure of the receiver becomes more complicated than the conventional single carrier scheme, and therefore, a technique for simplifying the OFDM receiver structure is very important.

On the other hand, in view of the advantages of the OFDM scheme, the use of multi-carrier can increase the symbol transmission time, which is relatively insensitive to the interference signal by the multi-path, there is little performance degradation for long time echo signal (echo signal) . In addition, the existing signal has a strong property, so there is little influence on co-channel interference, and due to this characteristic it is possible to form a single frequency network (SFN). Here, the SFN means that one broadcast broadcasts the whole country on one frequency, and in this case, co-channel interference becomes severe. Therefore, since OFDM is strong in the same channel environment, if the SFN network is configured, limited frequency resources can be efficiently used. In addition, OFDM can increase the bandwidth efficiency by making the spectrum of a signal closer to a square compared to conventional digital modulation techniques. This is because the transmission rate of the modulated data is relatively low, so that the spectrum of the signal modulated by each carrier has a very narrow transition bandwidth, and the OFDM signal added thereto can also maintain a narrow transition bandwidth.

As described above, since the OFDM scheme modulates each parallel channel and then transmits the sum signal, independent subcarriers are needed as many as parallel channels, and the subcarriers maintain mutual orthogonality in the frequency domain. Mutual motivation must be achieved. Thus, in the implementation of an OFDM transceiver, an increase in the number of parallel subchannels causes an increase in the hardware complexity of the OFDM transceiver.

However, if the system is digitized, such a decoding process can be implemented in one fast Fourier Transform (FFT) structure, so hardware can be easily implemented. Recently, the digital modulation OFDM method is used for European digital audio broadcasting and terrestrial broadcasting. It is adopted as the transmission method of high definition television.

Here, the OFDM scheme is as follows. 1 is a conceptual diagram illustrating the OFDM modulation principle, wherein a transmitting end is composed of a serial-to-parallel converter 1, a fast Fourier inverse transform chip (IFFT) 2, and a parallel-to-parallel converter 3. N represents the number of carriers. When the transmission data is serially input, the serial-to-parallel converter 1 converts the data into parallel data. The parallel data is input to the IFFT 2 to perform inverse Fourier transform, and the IFFT signal is serially transmitted through the parallel-to-serial converter. Is converted and transmitted. Here, a guard interval is inserted between successive symbols to remove intersymbol interference by multiple paths.

FIG. 2 is a block diagram of an OFDM modulator. The basic theory of OFDM modulation is to add a narrowband signal orthogonal to each other and to look like one signal in the time domain. To give a complex QAM signal to each single carrier, serial data of Ts length is divided into N signals in the time domain. Each signal forms one complex signal and is modulated by each carrier. That is, during QAM modulation, each complex symbol a _i input in series is parallelized to N stages, multiplied by a signal perpendicular to each other, and is represented by Equation 1 below.

[Equation 1]

Here, T _A is a sampling period of a complex carrier. If the carrier signals are orthogonal to each other, Equation 2 is satisfied.

[Equation 2]

Therefore, in consideration of this, the sum signal is expressed by Equation 3 below.

[Equation 3]

The sum of the symbol length T _S and the sampling period T _A are selected to satisfy the condition of the following Equation 4.

[Equation 4]

Therefore, finally, the sum signal of the following equation (5) is obtained.

[Equation 5]

Looking at Equation 5, it can be seen that the equation, such as N point IFFT. Thus, OFDM modulation can be simply implemented by IFFT.

FIG. 3 is a diagram illustrating a time-domain change of an OFDM-applied signal. When the OFDM signal is examined in the time-domain, a transmission time of each symbol is transmitted as a subcarrier because N symbol signals sent by a single carrier are loaded on N carriers. ) Will increase by the total number (N). This increase in symbol time is strong in the multipath, but it is difficult to implement the hardware of the receiver because N carriers must be used. However, as noted earlier, the signal modulated by the IFFT can be simply demodulated using the FFT.

On the other hand, in an OFDM system, since the NFT is IFFT-converted by one block unit, and the original information is recovered by transmitting the block-by-block and FFT transforming the same block at the receiving end, the synchronization of the block must be accurately detected. Therefore, in the conventional synchronization detection method, since a synchronization signal is inserted in each block and transmitted together with the information signal, there is a problem of causing a waste of resources required for channel and system implementation due to a significant subchannel occupied by the synchronization signal.

Accordingly, the present invention has been made to solve the above problems, the present invention is to find the wrong position and direction by investigating the phase distribution of the OFDM modulated signal with only the valid data without the synchronization signal is inserted and accordingly the correct block The purpose is to provide an OFDM receiving system that captures synchronization.

In order to achieve the above object, the present invention, in receiving and restoring a modulated OFDM signal without inserting a synchronization signal for each block unit consisting of N symbols, receives a serially inputted OFDM modulated signal and converts it in parallel. A first FFT chip that receives a first symbol group D _{1 to} D _N in parallel from the serial to parallel converter, and outputs an N point FFT from the serial to parallel converter; A first phase extractor for receiving a symbol in parallel and calculating a phase value, a first signal converter for inverting and outputting the sign of the phase value every clock, and an N / 2 symbol group (D) _{N / 2-} D _{N / 2 + (N-1)} ) A second FFT chip that receives N-point FFTs in parallel and receives N complex symbols processed by the second FFT in parallel to calculate a reference phase value A second phase extractor, the reference phase value A second signal converter which inverts a code every clock and outputs a synchronization signal generator that outputs a synchronization detection signal by comparing a phase value of the first signal converter and a reference phase value of the second signal converter; A switching unit that selects and outputs a block compensated by the number of symbols that are distorted according to the synchronization detection signal among a plurality of blocks provided from the conversion unit, and a third FFT which outputs an OFDM demodulation signal by FFT processing the block provided from the switching unit Characterized in that consists of.

1 is a conceptual diagram illustrating a modulation principle of an orthogonal frequency division multiplexing (OFDM) system;

2 is a block diagram of an OFDM modulator,

3 is a view illustrating a time domain change of a signal to which OFDM is applied;

4 is a block diagram of an OFDM receiver,

5 is a block diagram of an OFDM receiver according to the present invention;

FIG. 6 is a circuit diagram illustrating the series-parallel converter of FIG. 5;

7 is a circuit diagram illustrating a phase extraction unit of FIG. 5;

8 is a graph illustrating a phase distribution output from the phase extractor of FIG. 7;

9 is a circuit diagram illustrating a signal converter of FIG. 5;

10 is a graph illustrating a phase distribution output from the signal changer of FIG. 9;

FIG. 11 is a diagram for describing a method of detecting a distorted position and direction according to the phase distribution of FIG. 9; FIG.

FIG. 12 is a circuit diagram illustrating a sync signal generator of FIG. 5.

Explanation of symbols on the main parts of the drawings

50: serial-to-parallel converter 51: first FFT 52: first phase extractor

53: first signal converter 54: second FFT 55: second phase extractor

56 second signal converter 57 sync signal generator 58 switching unit

59: third FFT 70: absolute value calculator 72: delay register

74: subtraction section 76: addition section 90: linearization section

90-1, 90-4: Adder 90-2: Square root processor 90-3: Multiplier

95: inversion processing unit 95-1: multiplexer 95-2: multiplier

95-3: Exclusive logic gate 95-4: D flip-flop 110: Absolute value calculator

120: memory 130: control unit 131: multiplier

132: comparator 140: detection signal selector 141: ROM

142: adder 143: multiplexer

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

First, to help understand the present invention, a method of decoding an OFDM signal will be described. If the complex symbol a _{i, j} is a symbol transmitted from the i th block to the j th subchannel, the OFDM transmission signal Si (t) of the i th block may be expressed as in Equation 6 below.

[Equation 6]

Here, N is the number of subchannels in OFDM, and Tsym represents a period of one block. When the transmission signal is demodulated, the symbols a _{i, j} are detected from Equation 1 from Equation 1 using the orthogonality of each subcarrier.

[Equation 7]

As shown in Equation 7, it is complicated because the OFDM receiver generates a subcarrier for each subchannel and then decodes the result by performing multiplication and integration operation. However, when the OFDM reception signal is sampled and the decoding process of Equation 7 is performed by the digital technique, the integral operation can be eliminated and the number of multiplication operations can be reduced. Here, the detection of the symbol a _{i, j} with the sampling period Tsym / N is shown in Equation 8 below.

[Equation 8]

As can be seen from Equation (8), if the OFDM received signal is sampled and then DFT transformed, the transmission symbol can be decoded. Therefore, the implementation of the receiver using the FFT chip can reduce the multiplication operation in the reception process, and also maintain the orthogonality of each subcarrier.

Fig. 4 is a block diagram of a general orthogonal frequency division multiplexing receiving system, wherein the OFDM receiving system is composed of a serial to parallel converter 5, an FFT chip 6, and a parallel to serial converter 7. The serial-to-parallel converter 5 receives the OFDM reception signal input as a bit stream and outputs 2N bits in parallel. The FFT chip 6 converts the first input bit into a real component and the second input bit. N complex symbols composed of imaginary components and composed of one complex symbol are Fourier-transformed and output, and the parallel-to-serial converter 7 receives N complex symbols inversely Fourier-transformed in parallel and outputs them in series. do.

Next, the present invention will be described in detail by detecting the correct block on the receiving side by OFDM modulation without inserting a synchronization signal.

First, the principle of phase extraction is as follows. An information signal whose signal size is +1 or -1 at the transmitting side forms N complex symbols and IFFTs the transmitted block. You get an information signal. However, when the receiving side performs FFT processing by considering a block from a symbol other than the first symbol of a predetermined block, a signal having a size other than the original information signal size +1 or -1 is obtained. As described above, since the size of the information signal restored from the correct block due to synchronization is equal to +1 or -1, the absolute value of the two symbols is obtained for each block interval considered by the receiver, and if the difference is "0", the current recovered signal is obtained. The signal may be regarded as accurate, and may be represented as shown in Equation 9.

[Equation 9]

In Equation 9, Re _{i, j} is a real component of the j-th symbol of the i-th block, Im _{i, j} is an imaginary component of the j-th symbol of the i-th block, Re _{i-1, j} is i-1 The real component of the j-th symbol of the block, and Im _{i-1, j} is the imaginary component of the j-th symbol of the i-1th block.

If the noise component mixed with the received symbol has a Gaussian distribution, the average of the Gaussian distribution becomes "0", so that it can be expressed as a discrete sum as shown in Equation (9). If the value is restored from the correct synchronization and has a value of +1 or -1, PS is extracted from the jth symbol of the i block and the jth symbol of the i-1 block to obtain the absolute value of each symbol, and then add the difference. The value will be "0", and it is clear that the PS value is not "0" if out of sync. Therefore, by applying Equation (9), it is possible to monitor the sum value to obtain synchronization.

5 is a block diagram of an OFDM receiving system according to the present invention, in which the present invention provides a serial-to-parallel converter 50, a first FFT chip 51, a first phase extractor 52, and a first signal. The converter 53, the second FFT chip 54, the second phase extractor 55, the second signal converter 56, the synchronization signal generator 57, the switch 58, and the third FFT The chip 59 is comprised.

The serial-to-parallel converter 50 receives OFDM modulated signals input in series and converts them in parallel to output in block units.

The first FFT chip 51 receives the first symbol group D ₁ -D _N in parallel from the serial-to-parallel conversion unit 50 and performs N-point FFT processing, and the N complex symbols processed by the first FFT are processed. Is input in parallel to the first phase extractor 52 to calculate a phase value. The phase value is outputted as a phase value having an alternating sign between a positive value and a negative value every clock through the first signal converter 53.

The second FFT chip 54, the second phase extractor 55, and the second signal converter 56 may include the first FFT chip 51, the first phase extractor 52, and the first signal converter. It operates in the same structure as that of the unit 53, except that the input symbol is N symbols with a symbol D _{N / 2} separated by N / 2 symbols from the first symbol of the block input to the first FFT as the first symbol. The N / 2 symbol group D _{N / 2 to} D _{N / 2 + (N-1)} consisting of the inputs are processed in parallel. The phase value output from the second signal converter 56 is referred to as a reference phase value y 'for convenience, and this value is compared with the phase value y output from the first signal converter 53 and is distorted. Used to determine the number of symbols.

The synchronization signal generator 57 compares the phase value y with the reference phase value y 'and determines how out of sync the blocks currently regarded as temporary are detected to compensate for the number of symbols that are out of order. The signal is output to the switching unit 58.

The switching unit 58 receives a plurality of symbol groups, a first group of symbols (D ₁ ~D _N) to the N-th symbol group (D _N ~D _2N-1) from the serial-to-parallel conversion section 50, the The corresponding one group is selected from the plurality of groups according to the synchronization detection signal and input to the third FFT chip. The selected group is composed of the same symbols as the block determined at the time of transmission, so that the block synchronization can be restored and accurate restoration can be performed without separately inserting the block synchronization signal.

Next, embodiments of the present invention will be described in detail with reference to detailed circuit diagrams of the above components. This embodiment is implemented as an OFDM receiver in which 64 symbols constitute one block.

FIG. 6 is an exemplary circuit diagram of the serial to parallel converter of FIG. 5, wherein the serial to parallel converter 50 receives an OFDM received signal in series and outputs a plurality of groups in parallel in units of block lengths. R127). Here, the first group consists of the output symbol D _{1 of the} flip-flop No. ₁ to the output symbol D ₆₄ of the flip-flop No. 64, by grouping data output in parallel from the serial / parallel shift register in units of block lengths. The output symbols D _{2 of the} flip-flop No. ₂ to the output symbols D ₆₅ of the flip-flop No. 65 are output in parallel in 64 groups. As will be described below, the first group D _{1 to} D ₆₄ is provided to the first FFT chip 51, and the thirty-second group D _{32 to} D ₉₅ is provided to the second FFT chip 54. And all groups (first to sixty-sixth groups) are provided to the switching unit 58.

7 is a circuit diagram showing the phase extractor of FIG. 5, wherein the phase extractor 52 is an absolute value calculator 70, a delay register 72, a subtractor 74, and an adder 76. Consists of. The phase extractor receives N symbols in parallel by applying Equation 9 to obtain a difference value of an absolute value with N symbols of a previous clock, and outputs a difference between blocks as a phase value PS.

The absolute value calculation unit 70 receives N FFT-processed N complex symbols in parallel, obtains the absolute values of the real component Re and the imaginary component Im of the complex symbol, and outputs them to the delay register 72. The delay register 72 delays the absolute values outputted in parallel by one clock, and outputs them in parallel to the subtractor 74. The subtractor 74 subtracts the output value of the absolute value calculator 70 from the output value of the delay register 72 and outputs the parallel value to the adder 74. The adder 76 adds all N values output in parallel from the subtractor 74 and outputs the sum value as a phase value.

8 is a graph illustrating the phase distribution output from the phase extraction unit of FIG. 7. As shown in Fig. 8, when the block is composed of 64 (= N) symbols, when the synchronization is identical and the reception side is set to the same block as the transmission side block, the sum value PS is '0'. However, if the synchronization does not match, the receiver receives A value when it leaves 16 (= N / 4) symbols, has a B value when it leaves 32 (= N / 2) symbols, and 48 (= 3N / 4). ) Has a C value outside the symbol. In other words, it shows a nonlinear semi-elliptic trajectory that continues to increase until it leaves the N / 2 symbol and then leaves the N / 2 symbol.

Next, FIG. 9 is a circuit diagram illustrating the phase signal converter of FIG. 5, wherein the phase extractor receives a phase signal PS having the distribution as shown in FIG. 7 and shifts the phase by 180 ° every clock to invert and synchronize the signal. In addition to converting the signal into a convenient signal to obtain, it converts the nonlinear phase value into a linear phase value to implement a simpler hardware. The signal converter 53 converts a phase value PS having a non-linear distribution into a phase value LS having a linear distribution, and converts the linearized phase value LS into a code for each block. It consists of an inversion process part 95 which inverts and outputs the final determined phase value y.

Here, the linearization process will be described using an elliptic formula.

As the above-mentioned semi-elliptic curve to give a phase signal (PS) distribution of block length N in Fig. 8, the center is (2 / N, 0) which indicates the non-linear distributions, where the x ₁ axis 2 / N value, If a 'and the y _1- axis value of the semi-elliptic curve PS when x ₁ = a are b, the following equation (10) can be obtained.

[Equation 10]

이고, x₁=a 부터 x₁=N 까지의 직선 방정식은

이다. 여기서, 상기 수학식 10의 (ii)식에 두 직선의 방정식을 대입해 주면, 반 타원 곡선을 직선으로 선형화 할 수 있으며, 그때의 직선 방정식은 하기 수학식 11과 같다.And the linear equation from x ₁ = 0 to x ₁ = a is

Where the linear equation from x ₁ = a to x ₁ = N

to be. Here, by substituting the equation of two straight lines into the equation (ii) of Equation 10, the semi-elliptic curve can be linearized into a straight line, and the straight line equation at that time is as shown in Equation 11 below.

[Equation 11]

값이 바로 비선형 위상값이며, 이 값은 상기 위상 추출부로부터 제공된 비선형 위상값(PS)에 해당한다. 비선형 위상값

을 상기 수학식 11을 통해 얻은

값이 바로 선형화된 위상값(LS)이다.In Equation 11

The value is a nonlinear phase value, and this value corresponds to the nonlinear phase value PS provided from the phase extraction section. Nonlinear Phase Value

Obtained through Equation 11

The value is the linearized phase value LS.

As shown in FIG. 9, the linearizer 90 has two adders 90-1 for converting the nonlinear phase value PS into a linear phase value LS by applying Equation 11 and a square root processor ( 90-2) and a multiplier 90-3. In addition, the values provided as operands of each hardware are constant values obtained as a result of the simulation. The signal value output from the last stage adder 90-4 of the linearization unit 90 is a linearized phase value. The distribution forms a triangular wave with a block length, and always has a positive value. Therefore, the inversion processing unit 95 which inverts the signal value at every period and converts the phase so as to easily synchronize is connected.

Now, the inversion processor 95 receives the multiplexer 95-1 which alternately outputs '1' or '-1' every clock and the linearized phase value LS of the linearizer 90. And a multiplier 95-2 which receives the output value of the multiplexer 95-1, multiplies the result, and inverts the phase by 180 degrees every clock to output the final phase value y.

And an exclusive logic gate 95-3 and a delay register 95-4 for providing a control signal of the multiplexer 95-1. The exclusive logic gate 95-3 exclusively combines the clock signal and the output of the previous delay register 95-4 and outputs the exclusive logic sum to the delay register 95-4. The delay register 95-4 is configured as a D flip-flop, and delays the input signal by one clock to feed back to the exclusive logic gate 95-3.

In this way, the delay register 95-4 alternately outputs '1' and '0' for each clock, and the multiplexer 95-1 receiving the '1' and '0' as a control signal receives the output signal. According to the control signal, '1' and '-1' are alternately outputted every clock. Therefore, the linearized signal having only the positive value input to the multiplier 95-2 is multiplied by the output value of the multiplexer to convert the positive value and the negative value alternately every clock.

10 is a graph illustrating a phase distribution output from the signal changer of FIG. 9, (a) is a distribution of sum values provided from the phase extractor, and (b) is input from a linearizer of the signal converter. (C) is a phase distribution obtained by inverting a signal by shifting the signal (b) 180 degrees every clock by the inversion processor of the signal converter.

However, even if it has the distribution as shown in (c), since the number of twisted symbols corresponds to one phase value because it has a symmetrical distribution at the point of N / 2 symbol twisting with the N block length, the number of symbols is off. It is necessary to determine whether or not to generate a sync detection signal to compensate.

Next, FIG. 11 is a diagram for describing a method of detecting a misaligned position and direction according to the phase distribution of FIG. 9. FIG. 11 is a distribution of the phase value finally output from the signal converter, and assumes that the block length is an OFDM signal having 64 symbols, and shows the phase value output according to the number of distorted symbols. In case of demodulating the correct block at the time of reception, the phase value is '0' and the values at that time are represented as "Ref1", "Ref2", "Ref3", Have Because of this, if the wrong position is out of 12 symbols, the phase value (A) and the wrong position is out of 52 symbols, the phase value (A ') will have the same value (A = A'). .

Here, let C be the phase value of the 32 symbol out of the 12 symbol out of position and C 'the phase value of the 32 symbol out of the 52 symbol out of position. Then, while A> 0 and C> 0, while A '> 0 and C' <0, multiplying two phase values A and C related to the case where 12 symbols are out of order results in a positive value (A · C> 0). And multiplying the two phase values A 'and C' related to the case out of 52 symbols, it can be seen that they have a negative value (A 'C' <0).

Accordingly, the direction in which the phase is shifted is multiplied by the phase value of the block output from the signal converter and the phase value of the block that is 32 symbols further apart from each other, and if the multiplied value is "positive value (+)", it is left from the center. The value at is equal to or less than the N / 2 symbol, and if the product is "negative", it is off the center to the right, which is greater than the N / 2 symbol. Accurate synchronization can be detected by accurately detecting the number of wrong symbols found and compensating for the number of wrong symbols.

12 is a circuit diagram of the synchronization signal generator of FIG. 5, wherein the synchronization signal generator 57 includes an absolute value calculator 110, a memory 120, a controller 130, and a detection signal selector 140. Consists of

The absolute value calculator 110 calculates an absolute value of the linear phase value y output from the signal converter 53 and provides the absolute value to the read address of the memory 120. The memory 120 stores the number of symbols corresponding to the wrong position, receives the output of the absolute value calculator 110 as a read address, and outputs the number of symbols. The controller 130 outputs a control signal by determining a misaligned direction by receiving the linear phase value y and the reference phase value y '. Here, the reference phase value y 'is a phase value obtained from the block starting from a symbol previously received by 32 symbols from the first symbol of the block corresponding to the linear phase value. This reference phase value was provided from the second FFT chip 54, the second phase extractor 55, and the second signal converter 56. The detection signal selector 140 selects a displaced position and direction according to the number of symbols provided from the memory 120 and the control signal provided from the controller 130 and outputs the number of symbols to be compensated as a synchronization detection signal. .

The controller 130 receives the linear phase value y and the reference phase value y 'and multiplies the two values and outputs the multiplier 131 and the output value of the multiplier 131. And a comparator 132 which outputs the result as a control signal in comparison with " 0 ". The memory 120 stores only the number of symbols corresponding to half of the block length, that is, 0 to 32 (= N / 2) symbols. The detection signal selecting unit 140 stores the memory 120 from the ROM 141 storing the number of symbols “64 (= N)” corresponding to the block length and the value of the ROM (64 = N). An adder 142 for subtracting and outputting the number of symbols provided from the plurality of symbols; ) Is configured to include.

The synchronizing signal generator 57 configured as described above takes the absolute value of the phase value y output from the first signal converter 53 and provides it to the read address of the memory 120. In the memory 120, a predetermined number K of symbols is output according to a read address, and the first number K is provided to an input terminal of the multiplexer 83-3 and the adder 83. -2). The adder 83-2 subtracts the first symbol number K from the total block length 64 = N to provide the second symbol number N-K to the first input terminal of the multiplexer 143. Meanwhile, the controller 130 multiplies the phase value y by the reference phase value y 'and compares the multiplied value Z with "0" through the comparator 132, where the multiplied value is 0. If smaller, the control signal 1 level is output. If the multiplied value is greater than or equal to 0, the control signal 0 level is output and provided as the selection control signal of the multiplexer 143 of the detection signal selector.

Therefore, when the block length is 64 symbols, when the phase value exists at the position where the phase value is 0 to 32 symbols, since the sign of the phase value y and the reference phase value y 'is the same, the control signal has 0 level, The multiplexer 143 selects the number of symbols K: 0 to 32 provided from the memory as it is and uses it as a synchronization detection signal.

In addition, when the phase value exists at the position of 33 to 64 symbols, since the sign of the phase value y and the reference phase value y 'is opposite, the control signal has one level, and the multiplexer 143 The number of symbols 64-K subtracted from the original block length 64 by the number of symbols K provided from the memory is selected and used as the synchronization detection signal.

The synchronization detection signal generated by the synchronization signal generator thus represents the wrong number of symbols. Accordingly, if the number of the incorrect symbols is zero because the synchronization is correct, the switching unit 58 first group D _{1 to} D ₆₄ . in the selection, and the number of twisted symbol 1 if the switching unit 58 in the second group, select (D ₂ ~D _65), and the number of symbols if the two twisted the switching unit 58, the third group (D ₃ resetting the block in accordance with a twisted number of symbols, such as selecting a ~D ₆₆₎ and outputs it to the FFT 3 chip (59). As such, the third FFT chip 59 recovers the OFDM modulated signal by performing FFT conversion on a block basis obtained at the exact synchronization.

Although the invention has been described herein only in connection with specific embodiments, those skilled in the art will be able to make various modifications without departing from the spirit and scope of the invention as defined in the following claims.

As described above, the OFDM modulated signal of only the information data is detected on the receiving side without inserting the synchronization signal for each block, thereby recovering the synchronization to the block to be restored.

Claims (23)

In receiving and restoring a modulated OFDM signal without inserting a synchronization signal every block unit consisting of N symbols, A serial-to-parallel converter 50 which receives the OFDM-modulated signals input in series and converts them in parallel; A first FFT chip 51 receiving the first group D _{1 to} D _N in parallel from the serial-to-parallel converter 50 to perform N point FFT processing; A first phase extracting unit 52 for receiving the first FFT processed N complex symbols in parallel and calculating a phase value PS; A first signal converter 53 for inverting the sign of the phase value PS every clock and outputting a phase value y; A second FFT chip (54) configured to receive N-point FFTs in parallel from an N / 2 group (D _{N / 2 to} D _{N / 2 + (N-1)} ) from the serial-to _- parallel converter 54; A second phase extracting unit 55 for receiving the N F symbols processed in parallel with the second FFT and calculating a reference phase value PS 'in parallel; A second signal converter 56 for inverting the sign of the reference phase value PS 'every clock to output a reference phase value y'; A synchronization signal generator 57 for outputting a synchronization detection signal by comparing the phase value y of the first signal converter 53 and the reference phase value y 'of the second signal converter 56; A switching unit 58 which selects and outputs a group compensated by the number of symbols which are distorted according to the synchronization detection signal among a plurality of groups provided from the serial-to-parallel conversion unit 50, and And a third FFT chip (59) for FFT processing the compensated group provided from the switching unit (58) to output an OFDM demodulated signal. [4] The apparatus of claim 1, wherein the serial-to-parallel converter 50 includes serial-to-parallel shift registers R1 to R127 each of which is a D flip-flop for receiving an OFDM modulated signal in series and outputting a plurality of groups in parallel. Orthogonal Frequency Division Multiplexing Receiving System. 3. The method of claim 2, wherein the plurality of groups are grouped in block length units and N groups are output, and the i group is an output symbol D of flip-flop _i from i + (N-1) to i-group (i-1). Orthogonal frequency division multiplexing receiving system, characterized in that N symbols consisting of up to _{i + (N-1)} . The method of claim 1, wherein the first phase extractor 52 receives N complex symbols subjected to the first FFT in parallel to obtain absolute values of the real component Re and the imaginary component Im of the complex symbol, respectively. An absolute value calculator 70 for outputting in parallel; A delay register 72 for delaying the absolute values outputted in parallel by one clock and outputting them in parallel; A subtraction unit 74 for subtracting the output values of the absolute value calculation unit 70 from the output values of the delay register 72 and outputting them in parallel; And an adder (76) for adding all N values output in parallel from the subtractor (74) to output a sum value (PS). The orthogonal frequency division multiplexing receiving system according to claim 4, wherein the absolute value calculator (70) has 2N absolute value calculators (70-1 to 70-2N) connected in parallel. 5. The orthogonal frequency division multiplexing reception according to claim 4, wherein the delay register (72) has 2N registers (72-1 to 72-2N) configured in parallel and delays the input data by one clock. system. The orthogonal frequency division multiplexing receiving system according to claim 4, wherein the subtractor (74) comprises 2N subtractors in parallel. The linearization method of claim 1, wherein the first signal converter 53 converts a phase value PS having a non-linear distribution obtained from the first phase extractor 52 into a phase value LS having a linear distribution. Section 90; And an inversion processor (95) for inverting the sign of the linearized phase value (LS) for every clock and outputting a final phase value (y). The method of claim 8, wherein the linearization unit 90 is

Is composed of two adders 90-1, a square root processor 90-2, and a multiplier 90-3 for converting the nonlinear phase value PS = y ₁ into a linear phase value LS. Orthogonal frequency division multiplexing receiving system, characterized in that. 10. The apparatus of claim 8, wherein the inversion processor (95) comprises: a multiplexer (95-1) for alternately outputting '1' or '-1' every clock; Receives the linearized phase value LS of the linearization unit 90, multiplies the output value of the multiplexer 95-1, and inverts the phase by 180 ° every clock to output the phase value y. Multiplier 95-2; The inversion processing unit 95 includes an exclusive logic gate 95-3 for exclusively combining the clock signal with the previous output and outputting the exclusive logic gate; Orthogonal frequency, characterized in that it comprises a delay register (95-4) for receiving and delaying the signal output from the exclusive logic gate (95-3) to feed back to the exclusive logic gate (95-3) Division Multiplexing Reception System. 11. The orthogonal frequency division multiplexing receiving system according to claim 10, wherein the multiplexer (95-1) of the inversion processing unit uses the output signal of the delay register (95-4) as a control signal. The method of claim 1, wherein the second phase extractor 55 receives N complex symbols subjected to the second FFT in parallel to obtain the absolute values of the real component Re and the imaginary component Im of the complex symbol, respectively. An absolute value calculator 70 for outputting in parallel; A delay register 72 for delaying the absolute values outputted in parallel by one clock and outputting them in parallel; A subtraction unit 74 for subtracting the output values of the absolute value calculation unit 70 from the output values of the delay register 72 and outputting them in parallel; And an adder (76) for adding all N values output in parallel from the subtractor (74) to output a sum value (PS). 13. The orthogonal frequency division multiplexing receiving system according to claim 12, wherein the absolute value calculator (70) has 2N absolute value calculators (70-1 to 70-2N) connected in parallel. 13. The orthogonal frequency division multiplexing reception according to claim 12, wherein the delay register (72) has 2N registers (72-1 to 72-2N) configured in parallel and delays the input data by one clock. system. 13. The orthogonal frequency division multiplexing receiving system according to claim 12, wherein the subtractor (74) comprises 2N subtractors in parallel. 2. The reference signal value PS 'of claim 1, wherein the second signal converter 56 converts the reference phase value PS ′ having a non-linear distribution from the second phase extractor 55 into a phase value LS ′ having a linear distribution. A linearization unit 90 for changing; And an inversion processor (95) for inverting the sign of the linearized reference phase (LS ') for every clock and outputting a final reference phase (y'). The method of claim 16, wherein the linearization unit 90 is

Two adders 90-1, a square root processor 90-2, and a multiplier 90-3 for converting the nonlinear reference phase value PS '= y ₁ to a linear reference phase value LS' by applying Orthogonal frequency division multiplexing receiving system characterized in that consisting of. 17. The apparatus of claim 16, wherein the inversion processor (95) comprises: a multiplexer (95-1) for alternately outputting '1' or '-1' every clock; The linearized phase value y of the linearization unit 90 is input, the output value of the multiplexer 95-1 is input and multiplied, and the phase is reversed by 180 ° every clock so that the final reference phase value y 'is obtained. Multiplier (95-2) An exclusive logic gate 95-3 configured to output an exclusive logic sum of the clock signal and the previous output; Orthogonal frequency, characterized in that it comprises a delay register (95-4) for receiving and delaying the signal output from the exclusive logic gate (95-3) to feed back to the exclusive logic gate (95-3) Division Multiplexing Reception System. 19. The orthogonal frequency division multiplexing receiving system according to claim 18, wherein the multiplexer (95-1) of the inversion processing unit uses the output signal of the delay register (95-4) as a control signal. 2. The apparatus of claim 1, wherein the synchronization signal generator (57) comprises: an absolute value calculator (110) for calculating an absolute value of the linear phase value (y) output from the first signal converter (53); A memory 120 for receiving the output of the absolute value calculator 110 as a read address and outputting the number of symbols corresponding to a misaligned position; A controller 130 for determining a misaligned direction by receiving the linear phase value y and the reference phase value y 'output from the second signal converter 56 and outputting a control signal; And a detection signal selector 140 for outputting the number of symbols to be compensated by selecting a displaced position and direction according to the number of symbols provided from the memory 120 and the control signal provided from the controller 130. Orthogonal frequency division multiplexing receiving system. 21. The apparatus of claim 20, wherein the controller (130) comprises: a multiplier (131) for receiving the linear phase value (y) and the reference phase value (y ') and outputting a value (Z) multiplied by two values; And a comparator (132) for receiving the output value (Z) of the multiplier (131) and comparing the result with "0" and outputting the result as a control signal. 21. The orthogonal frequency division multiplexing receiving system according to claim 20, wherein the memory (120) stores from 0 to N / 2 symbols. 21. The apparatus of claim 20, wherein the detection signal selector 140 comprises: a ROM 141 for storing a symbol number "N" corresponding to a block length; An adder (142) for subtracting and outputting the number of symbols provided from the memory (120) from the ROM value (N); Orthogonal frequency division multiplexing receiving system characterized in that it comprises a multiplexer 143 for selectively outputting the output of the adder 142 or the output of the memory 130 in accordance with a control signal provided from the controller 130 .

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