KR19980073943A - Capacitance element - Google Patents

Abstract

A capacitance element is disclosed in which the capacitance of a capacitor remains constant with respect to the voltage to which it is applied. The capacitance element according to the present invention includes a semiconductor substrate, a first material layer, impurity implantation regions, a gate insulating film, and a poly gate layer. The semiconductor substrate is formed of a material of the first conductivity type. The first material layer is formed on the semiconductor substrate and is made of a second conductivity type material. The impurity implantation regions are formed as materials of the second conductivity type at predetermined positions on the first material layer, respectively. The gate insulating film is formed between the second material layer on the first material layer. The poly gate layer is formed on the gate insulating film. According to the present invention, the capacitance of the capacitor does not change in accordance with the applied voltage has the effect of being kept constant.

Description

Capacitance element

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to capacitance devices, and more particularly to capacitance devices in which the capacitor capacity does not change with the applied voltage.

1 shows a cross-sectional view of a conventional capacitance element.

Referring to FIG. 1, a conventional capacitance device may include a semiconductor substrate 100, a P type well 110, impurity implantation regions 122 and 124, a gate insulating layer 130, a poly gate layer 140, and an oxide layer 150. And contact hole regions 162 and 164.

The semiconductor substrate 100 is made of a P-type material.

The P type well 110 is formed at a predetermined position on the semiconductor substrate 100 to form a capacitance element.

The impurity implantation regions 122 and 124 are formed at predetermined positions for the drain region and the source region on the P-type well 110, respectively. The impurity implantation regions 122 and 124 are formed by ion implanting N-type high concentration impurities at predetermined positions for the drain region and the source region, respectively, by ion implantation techniques.

The gate insulating layer 130 is formed between the impurity implantation regions 122 and 124 on the P-type well 110.

The poly gate layer 140 is a poly silicon layer formed on the gate insulating layer 130. The poly gate layer 140 is connected to the gate electrode VG.

The oxide film 150 is formed at a predetermined position on the semiconductor substrate 100, the P type well 110, the impurity implantation regions 122 and 124, and the poly gate layer 140.

The contact hole regions 162 and 164 are formed at predetermined positions on the impurity implantation regions 122 and 124 to form electrodes of the drain region and the source region. The contact hole region 162 forms a drain electrode and the contact hole region 164 forms a source electrode. The contact hole regions 162 and 164 are connected to the source-drain electrode VDS.

The charge layer formed under the gate insulating layer 130 is divided into an accumulation layer, a depletion layer, and an inversion layer according to a voltage applied to the gate electrode VG.

FIG. 2 illustrates an accumulation layer 111 formed under the gate insulating layer 130 as a voltage is applied to the source-drain electrode VDS and the gate electrode VG in FIG. 1. That is, FIG. 2 illustrates an accumulation layer formed under the gate insulating layer 130 by applying a constant voltage, for example, 5V, to the source-drain electrode VDS, and applying a negative voltage to the gate electrode VG. The Accumulation Layer 111 is shown schematically. 2 uses the same reference numerals as in FIG. 1.

If the voltage applied to the gate electrode VG has a negative value, that is, VG0, a negative charge 141 is charged to the poly gate layer 140 through the gate electrode VG. The negative charge 141 attracts holes existing in the P-type well 110 to form a positive charge layer, that is, an accumulation layer 111, below the gate insulating layer 130. To form. Therefore, the poly gate layer 140 and the accumulation layer 111 may operate as if a parallel plate capacitor is formed between the gate insulating layer 130. The capacitance of the capacitor formed under the gate insulating layer 130 by the accumulation layer 111, that is, the capacitance of the gate capacitor by the gate insulating layer 130 is expressed as follows.

[Equation 1]

here, Denotes the capacitance of the gate capacitor by the gate insulating film 130, Represents a natural dielectric constant, Represents a dielectric constant of the gate insulating layer 130, Denotes the area of the poly gate layer 140.

3 illustrates a depletion layer 112 formed under the gate insulating layer 130 as a voltage is applied to the source-drain electrode VDS and the gate electrode VG in FIG. 1. That is, FIG. 3 shows a gate insulating film as a constant voltage, for example, 5V is applied to the source-drain electrode VDS, and a voltage having a positive value lower than the threshold voltage Vt is applied to the gate electrode VG. A depletion layer 112 formed under the 130 is schematically illustrated. 3 uses the same reference numerals as in FIG. 1.

When the voltage applied to the poly gate layer 140 through the gate electrode VG has a positive value smaller than the threshold voltage value Vt, the depletion layer 112 may form the gate insulating layer 130. It is formed at the bottom. That is, the holes in the lower portion of the gate insulating layer 130 are pushed away from the poly gate layer 140 by the voltage of the gate electrode VG having a positive value, and the lower portion of the gate insulating layer 130 is filled with negative ions. A depletion layer 112 is formed. In this case, the gate capacitor becomes as if the capacitor by the depletion layer 112 and the capacitor by the gate insulating layer 130 are connected in series.

The capacitance of the capacitor by the depletion layer 112 is represented by the following equation.

[Equation 2]

here, Represents the capacitance of the capacitor by the depletion layer 112, Denotes the dielectric constant of silicon constituting the P-type well 110.

Therefore, the gate capacitor capacity when the depletion layer 112 is formed is expressed by the following equation.

[Equation 3]

FIG. 4 illustrates an inversion layer 113 formed under the gate insulating layer 130 when voltage is applied to the source-drain electrode VDS and the gate electrode VG in FIG. 1. That is, FIG. 3 illustrates applying a constant voltage, for example, 5V, to the source-drain electrode VDS and applying a voltage having a positive value higher than the threshold voltage Vt to the gate electrode VG. Therefore, the inversion layer 113 formed under the gate insulating layer 130 is schematically illustrated. 4 uses the same reference numerals as in FIG. 1.

When the voltage applied to the poly gate layer 140 through the gate electrode VG has a positive value greater than the threshold voltage Vt, the second material of the material constituting the P-type well 110 is formed. Electrons, which are conductive carriers, are attracted under the gate insulating layer 130 to form an inversion layer 113. Since the inversion layer 113 is a layer having high conductivity, the capacitance of the gate capacitor when the inversion layer 113 is formed is the capacitance of the capacitor by the gate insulating layer 130. sign, Will be equal to.

5 is a graph illustrating a change in capacitance of a gate capacitor according to a voltage applied to the poly gate layer 140 through the gate electrode VG. Here, the vertical axis represents the capacitance of the gate capacitor, and the horizontal axis represents the voltage applied to the gate electrode VG.

Referring to FIG. 5, it can be seen that the capacity of the gate capacitor in the sufficiently low frequency region is temporarily reduced near the threshold voltage value Vt as described above.

As described above, the conventional capacitance element causes a temporary decrease in the capacitor capacity near the threshold voltage value Vt, thereby causing a problem in implementing an analog circuit requiring a constant capacitor capacity.

Accordingly, it is an object of the present invention to provide a capacitance element in which a capacitance is kept constant without changing the capacitor capacity according to the applied voltage.

1 is a cross-sectional view of a conventional capacitance element.

FIG. 2 is a cross-sectional view for describing a case in which an accumulation layer is formed below the gate insulating film in FIG. 1.

3 is a cross-sectional view for describing a case in which a depletion layer is formed under a gate insulating film in FIG. 1.

4 is a cross-sectional view for describing a case in which an inversion layer is formed under a gate insulating film in FIG. 1.

FIG. 5 is a graph showing capacitor capacitance according to a voltage applied in a conventional capacitance device.

6 is a cross-sectional view of a capacitance element according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view for describing a case where a depletion layer is formed under the gate insulating layer in FIG. 6.

FIG. 8 is a cross-sectional view for describing a case in which an inversion layer is formed under a gate insulating film in FIG. 6.

FIG. 9 is a graph illustrating capacitor capacitance according to a voltage applied in FIG. 6.

10 is a cross-sectional view viewed from the side of a capacitance device according to another embodiment of the present invention.

FIG. 11 is a cross-sectional view for describing a case where a depletion layer is formed under a gate insulating film in FIG. 10.

FIG. 12 is a cross-sectional view for describing a case in which an inversion layer is formed below a gate insulating layer in FIG. 10.

FIG. 13 is a graph illustrating capacitor capacitance according to a voltage applied in FIG. 10.

* Explanation of symbols for the main parts of the drawings

VDS: source-drain electrode, VG: gate electrode,

n +, p +: impurity implantation regions, p-well: P type well region,

n-well: N-type well region, p-sub: P-type semiconductor substrate,

n-sub: N-type semiconductor substrate.

In order to achieve the above object, a capacitance element according to the present invention includes a semiconductor substrate of a first conductivity type; A first material layer of a second conductivity type formed at a predetermined position on the substrate; Impurity implantation regions of a second conductivity type formed at a predetermined position on the first material layer; A gate insulating layer formed between the impurity implantation regions on the first material layer; A poly gate layer formed on the gate insulating layer; An oxide film formed at a predetermined position on the first material layer, the impurity implantation regions, and the poly gate layer; And contact holes formed on the impurity implantation regions, respectively.

Next, a specific embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 is a sectional view seen from the side of a capacitance element according to an embodiment of the present invention.

Referring to FIG. 6, the capacitance device according to the embodiment of the present invention may include a semiconductor substrate 200, an N-type well 210, impurity implantation regions 222 and 224, a gate insulating layer 230, and a poly gate layer 240. , An oxide film 250, and contact hole regions 262 and 264.

The semiconductor substrate 200 is made of a P-type material.

The N type well 210 is formed at a predetermined position on the semiconductor substrate 200 to form a capacitance element.

The impurity implantation regions 222 and 224 are formed at predetermined positions for the drain region and the source region on the N type well 210, respectively. The impurity implantation regions 222 and 224 are formed by ion implantation of high concentrations of N-type impurities at predetermined positions for the drain region and the source region, respectively, by ion implantation techniques.

The gate insulating layer 230 is formed between the impurity implantation regions 222 and 224 on the N type well 210.

The poly gate layer 240 is a poly silicon layer formed on the gate insulating layer 230. The poly gate layer 240 is connected to the gate electrode VG.

The oxide film 250 is formed at a predetermined position on the semiconductor substrate 200, the N type well 210, the impurity implantation regions 222 and 224, and the poly gate layer 240.

The contact hole regions 262 and 264 are formed at predetermined positions on the impurity implantation regions 222 and 224 to form the electrodes of the drain region and the source region. The contact hole region 262 forms a drain electrode and the contact hole region 264 forms a source electrode. The contact hole regions 262 and 264 are connected to the source-drain electrode VDS.

The charge layer formed under the gate insulating layer 230 is classified into a depletion layer and an inversion layer according to the voltage applied to the gate electrode VG.

7 is a depletion layer formed under the gate insulating layer 230 by applying a negative voltage to the source-drain electrode VDS and the gate electrode VG in FIG. 6. (211) is shown. That is, FIG. 7 illustrates a depletion layer formed under the gate insulating layer 230 by applying a constant voltage, for example, 5V, to the source-drain electrode VDS and applying a negative voltage to the gate electrode VG. 211 is schematically shown. 7 uses the same reference numerals as in FIG. 6.

If the voltage applied to the poly gate layer 240 through the gate electrode VG has a negative value, that is, VG0, a depletion layer 211 is formed under the gate insulating layer 230. That is, electrons existing in the N-type well 210 under the gate insulating film 230 are pushed away from the poly gate layer 240 by the voltage of the gate electrode VG having a negative value. A positive depletion layer 211 is formed below the 230. In this case, the gate capacitor becomes as if the capacitor by the depletion layer 211 and the capacitor by the gate insulating film 230 are connected in series. The capacitance of the capacitor by the depletion layer 211 is represented by the following equation.

[Equation 4]

here, Denotes the capacitance of the capacitor by the depletion layer 211, Denotes the dielectric constant of silicon constituting the N-type well 210.

Therefore, the gate capacitor capacity when the depletion layer 211 is formed is expressed by the following equation.

[Equation 5]

FIG. 8 is an inversion layer formed under the gate insulating layer 230 by applying a positive voltage to the source-drain electrode VDS and the gate electrode VG in FIG. 6. (212) is shown. That is, FIG. 8 illustrates an inversion layer formed under the gate insulating layer 230 by applying a constant voltage, for example, 5V, to the source-drain electrode VDS and applying a positive voltage to the gate electrode VG. 212 is shown schematically. 7 uses the same reference numerals as in FIG. 6.

When the voltage applied to the poly gate layer 240 through the gate electrode VG has a positive value, electrons, which are first conductive carriers of a material constituting the N type well 210, are formed of electrons. ) Is dragged under the gate insulating layer 230 to form an inversion layer 212. Since the inversion layer 212 is a layer having high conductivity, the capacitance of the gate capacitor when the inversion layer is formed is the capacitance of the capacitor by the gate insulating film 230, Will be equal to.

9 is a graph illustrating a change in capacitance of a gate capacitor according to a voltage applied to the gate electrode VG. Here, the vertical axis represents the capacitance of the gate capacitor, and the horizontal axis represents the voltage applied to the gate electrode VG.

Referring to FIG. 9, it can be seen that the capacity of the gate capacitor in the sufficiently low frequency region is always constant without changing as described above with respect to a voltage having a positive value.

As such, by forming the highly concentrated N-type impurity implantation regions 222 and 224 on the N-type well 210, it is possible to prevent the capacitance of the gate capacitor from being changed near the threshold voltage Vt. Therefore, the present invention can be applied to an analog circuit requiring a capacitance element having a constant capacitor capacity according to the applied voltage.

10 is a cross-sectional view viewed from the side of a capacitance device according to another embodiment of the present invention.

Referring to FIG. 10, a capacitance device according to another embodiment of the present invention may include a semiconductor substrate 300, a P-type well 310, impurity implantation regions 322 and 324, a gate insulating layer 330, and a poly gate layer 340. ), An oxide film 350, and contact hole regions 362 and 364.

The semiconductor substrate 300 is made of an N-type material.

The P type well 310 is formed at a predetermined position on the semiconductor substrate 300 to form a capacitance element.

Impurity implantation regions 322 and 324 are formed at predetermined positions for the drain region and the source region, respectively, on the P-type well 310. The impurity implantation regions 322 and 324 are formed by ion implanting high concentrations of P-type impurities at predetermined positions for the drain region and the source region, respectively, by ion implantation techniques.

The gate insulating layer 330 is formed between the impurity implantation regions 322 and 324 on the P-type well 310.

The poly gate layer 340 is a poly silicon layer formed on the gate insulating layer 330. The poly gate layer 340 is connected to the gate electrode VG.

The oxide film 350 is formed at a predetermined position on the semiconductor substrate 300, the P type well 310, the impurity implantation regions 322 and 324, and the poly gate layer 340.

The contact hole regions 362 and 364 are formed at predetermined positions on the impurity implantation regions 322 and 324 to form the electrodes of the drain region and the source region. The contact hole region 362 may form a drain electrode, and the contact hole region 364 may form a source electrode. The contact hole regions 362 and 364 are connected to the source-drain electrode VDS.

The charge layer formed under the gate insulating layer 330 is classified into a depletion layer and an inversion layer according to the voltage applied to the gate electrode VG.

FIG. 11 is a depletion layer formed under the gate insulating layer 330 by applying a positive voltage to the source-drain electrode VDS and the gate electrode VG in FIG. 10. (211) is shown. That is, FIG. 11 illustrates a depletion layer formed under the gate insulating layer 330 by applying a constant voltage, for example, 5V, to the source-drain electrode VDS and applying a positive voltage to the gate electrode VG. 311 is shown schematically. 11 uses the same reference numerals as in FIG. 10.

If the voltage applied to the poly gate layer 340 through the gate electrode VG has a positive value, that is, VG0, a depletion layer 311 is formed under the gate insulating layer 330. That is, the holes in the P-type well 310 under the gate insulating layer 330 are pushed away from the poly gate layer 340 by the voltage of the gate electrode VG having a positive value. A negative depletion layer 311 is formed below the 330. In this case, the gate capacitor is as if the capacitor by the depletion layer 311 and the capacitor by the gate insulating film 330 are connected in series. The capacitance of the capacitor by the depletion layer 311 is represented by the following equation.

[Equation 6]

here, Denotes the capacitance of the capacitor by the depletion layer 311, Denotes the dielectric constant of silicon constituting the P-type well 310.

Therefore, the gate capacitor capacity when the depletion layer 311 is formed is expressed by the following equation.

[Equation 5]

12 is an inversion layer formed under the gate insulating layer 330 by applying a negative voltage to the source-drain electrode VDS and the gate electrode VG in FIG. 10. 312 is shown. That is, FIG. 12 illustrates an inversion layer formed under the gate insulating layer 330 by applying a constant voltage, for example, 5V, to the source-drain electrode VDS and applying a negative voltage to the gate electrode VG. 312 is schematically shown. 12 uses the same reference numerals as in FIG. 10.

When the voltage applied to the poly gate layer 340 through the gate electrode VG has a positive value, holes, which are first conductive carriers of a material constituting the P-type well 310, are formed. ) Is dragged under the gate insulating layer 330 to form an inversion layer 312. Since the inversion layer 312 is a layer having high conductivity, the capacitance of the gate capacitor when the inversion layer 312 is formed is the capacitance of the capacitor by the gate insulating film 330, Will be equal to.

FIG. 13 is a graph illustrating a change in capacitance of a gate capacitor according to a voltage applied to the gate electrode VG. Here, the vertical axis represents the capacitance of the gate capacitor, and the horizontal axis represents the voltage applied to the gate electrode VG.

Referring to FIG. 13, it can be seen that the capacitance of the gate capacitor in the sufficiently low frequency region is always constant without change as described above with respect to a voltage having a positive value.

As such, by forming the high concentration P-type impurity implantation regions 322 and 324 on the P-type well 310, it is possible to prevent the capacitance of the gate capacitor from changing near the threshold voltage Vt. Therefore, the present invention can be applied to an analog circuit requiring a capacitance element having a constant capacitor capacity according to the applied voltage.

According to the present invention, in a capacitance device having a MOS transistor structure, a high concentration of impurity regions forming a source and a drain are formed on a well made of a material of the same conductivity type, so that it is not changed depending on the value of the voltage applied to the gate electrode. It has the effect of having a capacitor capacity. Therefore, it has an effect that can be applied to an analog circuit requiring a capacitance element having a constant capacitor capacity according to the applied voltage.

Claims (12)

In the capacitance element, A semiconductor substrate of a first conductivity type; A first material layer of a second conductivity type formed at a predetermined position on the substrate; Impurity implantation regions of a second conductivity type formed at a predetermined position on the first material layer; A gate insulating layer formed between the impurity implantation regions on the first material layer; And And a poly gate layer formed on said gate insulating film. The capacitance element according to claim 1, wherein the insulating layer is a silicon oxide film. The capacitance device of claim 1, wherein the gate electrode is a polysilicon layer. The capacitance device of claim 1, wherein the impurity implantation regions are formed by ion implanting a high concentration of a second conductivity type material. In the capacitance element, P-type semiconductor substrate; An N-type well formed at a predetermined position on the substrate; N-type impurity implantation regions formed in a predetermined position on the N-type well; A gate insulating film formed between the N-type impurity implantation regions on the N-type well; And And a poly gate layer formed on said gate insulating film. The capacitance element according to claim 5, wherein the insulating layer is a silicon oxide film. 6. The capacitance device of claim 5, wherein said gate electrode is a polysilicon layer. 6. The capacitance device of claim 5, wherein the N-type impurity implantation regions are formed by ion implanting a high concentration of an N-type material. In the capacitance element, An N-type semiconductor substrate; A P-type well formed at a predetermined position on the substrate; P-type impurity implantation regions formed at predetermined positions on the P-type well; A gate insulating film formed between the P-type impurity implantation regions on the P-type well; And And a poly gate layer formed on said gate insulating film. The capacitance element according to claim 9, wherein the insulating layer is a silicon oxide film. 10. The capacitance device of claim 9, wherein the gate electrode is a polysilicon layer. 10. The capacitance device of claim 9, wherein the P-type impurity implantation regions are formed by ion implantation of a high concentration of P-type material.