KR19980073687A - Optional Circuits for Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to an option circuit of a semiconductor memory device. SUMMARY OF THE INVENTION In accordance with an aspect of the present invention, an optional circuit of a semiconductor memory device having a memory chip block and a first and a second sense amplifiers may be configured to form first and second lead paths through the memory chip block, first and second sense amplifiers. And converting each other into a second product having a different number of data output bits, and having first and second control signal generation circuits for generating a sense amplifier enable signal for enabling each of the sense amplifiers. .

Description

Optional Circuits for Semiconductor Memory Devices

The present invention relates to a semiconductor memory device, and more particularly to a product option circuit of the semiconductor memory device.

In general, byte wide is a continuing trend. In general, when designing a product, it is common to use one product as a mother version and to allow multiple products by using a metal option. In other words, an optional product is made by using a product having an input / output of 36 as a mother version and removing a part of the input / output, such as 18, 9, and the like. 1 is a block diagram showing the lead path of a x18 product. Referring to FIG. 1, a memory cell array, a sense amplifier, and the like are largely divided into two groups in consideration of efficiency of address decoding or layout. It is divided into two groups of × 9, making it easy to switch to the × 9 product. The signals BSAEN1 and BSAEN2 are control signals for enabling the block sense amplifiers, and the signal MSAEN1 is control signals for enabling the main sense amplifiers. Since BSAEN1 and BSAEN2 are now × 18 products, they are both enabled / disabled at the same time, but if they are × 9 products, only one of them should be enabled. Fig. 2 is a block diagram when Fig. 1 is replaced with a x9 product. Referring to FIG. 2, signals BSAEN1 and BSAEN2 always have one address added so that only one of them is enabled. Nine of the main sense amplifiers are eliminated and permanently deselected using the Metal Option. Most circuits change from × 18 to × 9 by changing the control signal while still using it. 3 is a detailed circuit diagram illustrating a sense amplifier enable circuit for generating a control signal of a parent product according to an embodiment of the prior art. 4 is a detailed circuit diagram illustrating a sense amplifier enable circuit for generating a control signal of an optional product according to an embodiment of the prior art. Referring to FIGS. 3 and 4, the signal BSAENP is a signal generated internally mainly by a write enable signal. When the write cycle is performed, the signal BSAENP becomes a logic low and a read cycle. In this case, the logic high is used to disable / enable the sense amplifiers. In FIG. 3, since the NAND gates are fixed to a power supply voltage Vdd, that is, a logic high, one input terminal is the same as an inverter. Thus, signals BSAEN1 and BSAEN2 become the same signal and only delay with MSAEN1. This delay is intentionally made to enable the sense amplifiers sequentially because there is a time difference between the block sense amplifier and the main sense amplifier in the flow of data, and there should be no change. In Fig. 4, since the address signals AE and AEB for the optional products are applied to the inputs of the NAND gate, only one of them is always enabled when the signals BSAEN1 and BSAEN2 are enabled, and the signal MSAEN1 must also be enabled after a certain delay. . In FIG. 3, since all three output signals originate from one input signal, it is easy to adjust or locate the difference in the enable timing between the block sense amplifier and the main sense amplifier. In FIG. 4, the signal BSAENP is a write enable signal. Since the signal AE / AEB is an address signal, skew may occur between the two signals and a possibility of change due to a path difference is included. That is, signal MSAEN1 may be enabled before signals BSAEN1 and BSAEN2. This creates a problem that can cause serious errors in performance or chip operation.

An object of the present invention is to provide an option circuit of a semiconductor memory device that can reduce the skew between data by dividing the lead path into two.

Another object of the present invention is to provide an option circuit of a semiconductor memory device for optimizing chip operation by changing lead paths by mutually switching sense amplifiers on each lead path.

1 is a block diagram showing the lead path of a typical x18 product.

Fig. 2 is a block diagram when Fig. 1 is replaced with a x9 product.

Figure 3 is a detailed circuit diagram showing a sense amplifier enable circuit for generating a control signal of a parent product according to an embodiment of the prior art.

Figure 4 is a detailed circuit diagram showing a sense amplifier enable circuit for generating a control signal of an optional product according to an embodiment of the prior art.

5 is a detailed circuit diagram of a sense amplifier enable circuit for generating a control signal of a mother product according to one embodiment of the present invention;

6 is a detailed circuit diagram of a sense amplifier enable circuit for generating a control signal of an optional product according to an embodiment of the present invention.

According to an exemplary embodiment of the inventive concept, in an optional circuit of a semiconductor memory device having a memory chip block and a first and second sense amplifiers, the memory chip block, the first and second sense amplifiers may be selected. Forming first and second lead paths through each other to switch the first product to a second product having a different number of data output bits, and generating a sense amplifier enable signal for enabling each of the sense amplifiers. And a second control signal generating circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings.

5 is a detailed circuit diagram of a sense amplifier enable circuit for generating a control signal of a mother product according to one embodiment of the present invention. 6 is a detailed circuit diagram of a sense amplifier enable circuit for generating a control signal of an optional product according to an embodiment of the present invention. 5 and 6, the fundamental difference from FIGS. 3 and 4 is that the main sense amplifier enable signal is generated by the block sense amplifier enable signal. FIG. 5 is a case of the parent product, and as a result, there is no big difference from FIG. 3, but FIG. 6 is an option product, so that there is no skew problem that may occur in FIG. In other words, even if skew occurs between the write enable signal and the address signal, the NAND gate is selected by the late signal, and the block sense amplifier enable signal is selected, and the main sense amplifier enable signal and the main sense amplifier enable signal are used again. There can always be a constant delay between signals, and the sense amplifiers can be enabled sequentially as data flows.

According to the present invention, it is possible to reduce the data skew by switching each of the two or more products through each control path from the control signal generation circuit, and at the same time has the effect of optimizing chip operation.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (6)

An optional circuit of a semiconductor memory device having a memory chip block, first and second sense amplifiers, First and second lead paths are formed through the memory chip block and the first and second sense amplifiers, and the respective products are switched to each other, thereby converting the first product to a second product having a different number of data output bits and verifying each of the sense amplifiers. And first and second control signal generation circuits for generating a sense amplifier enable signal for enabling the signal. 2. The method of claim 1, wherein the first and second lead paths amplify data stored in a memory block, and the second sense amplifier amplifies the output, and outputs the same number of data. An optional circuit of a semiconductor memory device, characterized in that. 2. The apparatus of claim 1, wherein the first and second lead paths are grouped into the same group via the same second sense amplifier from the memory pin block to the final data output and the second sense amplifier in the second product. And a second group including a first group to communicate with, and a second group including the unused second sense amplifiers. 4. The option circuit of claim 3, wherein the second product is formed by permanently disabling a second sense amplifier group belonging to the second group from the first product. The method of claim 1, wherein the first control signal generating circuit simultaneously enables a first sense amplifier enable signal belonging to the first group and a first sense amplifier enable signal belonging to a second group, and delays a predetermined delay from both signals. And the second sense amplifier enable signal is enabled later. The method of claim 1, wherein the second control signal generating circuit selectively addresses the first sense amplifier enable signal of the first group and the first sense amplifier enable signal of the second group according to an address signal through an address signal. And the second sense amplifier enable signal is enabled after a predetermined time delay even if only one of the two signals is enabled.