KR19980069908A - A semiconductor device having a multilayer wiring and its manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring in which the wiring layer comprises a laminated structure of a main conductive layer of Ti or A1 alloy and a Ti layer, and provides a semiconductor device having a multilayer wiring having a low resistance value and a long service life. It aims to do it.

The structure of this invention WHEREIN: The semiconductor device which has a multilayer wiring WHEREIN: At least 1 wiring layer of a multilayer wiring is formed in contact with the said main conductive layer and the main conductive layer formed from A1 or A1 alloy, and are formed on or under it, A semiconductor device having a multilayer wiring having a first high melting point metal layer having a thickness of about 2 nm to about 7 nm is provided.

Description

A semiconductor device having a multilayer wiring and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a multilayer structure including a laminated structure of a main conductive layer of a wiring layer A1 or an A1 alloy and a high melting point metal layer such as Ti.

Multilayer wiring is used for a highly integrated integrated circuit device. As the semiconductor element scales down, the wiring width becomes narrower. In order to avoid high resistance of the wiring, the wiring layer may be thickened. In the case where a conformal interlayer insulating layer is formed on the wiring layer, the surface step of the interlayer insulating layer becomes large, and it becomes difficult to form upper wiring.

Thus, the surface of the interlayer insulating layer is planarized. As the planarization technique, reflow, the use of a spin on glass (SOG) layer, chemical mechanical polishing (CMP), or the like is used. After the interlayer insulating layer is planarized, a connection hole (contact hole via hole) leading to the lower wiring layer is formed. When the width of the wiring layer is narrowed, the aspect ratio also increases in the connection hole, and it becomes difficult to fill the upper wiring layer in the connection hole.

Therefore, the conductive plug which fills in the connection hole is formed, and then the upper wiring layer is formed. The plug is formed by selective growth of tungsten, growth of a blanket tungsten layer, and subsequent removal of tungsten by CMP or etching.

According to such a process, a wiring layer is always formed on a flat surface, it can prevent the disconnection of the wiring in a level | step difference part, can raise the grade of photolithography, and can maintain the reliability of wiring high.

It is preferable that the wiring has a sufficiently low resistance value and does not deteriorate even by use. Even if the wiring is formed so as to realize a desired low resistance value, the resistance value of the completed wiring increases, and the resistance value increases with use.

The resistance value of the wiring is influenced not only by the resistivity of each wiring layer but also by the resistivity of the connection member (plug) between the wiring layers, the contact resistance between the wiring members, the electromigration during use, and the like. In the multilayer wiring using the plug, in particular, the electromigration life and the resistance of the contact portion of the plug are problematic.

As described above, in a semiconductor device having a multilayer wiring, a highly reliable multilayer wiring having a low resistance value and a long lifetime is required.

An object of the present invention is to provide a semiconductor device having a low resistance value and having a long lifetime.

Another object of the present invention is to provide a method of manufacturing such a semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view and a graph for explaining an experiment conducted by the present inventors.

2 is a cross-sectional view for explaining an experiment conducted by the inventor.

3 is a plan view and a graph for explaining an experiment conducted by the inventors.

4 is a plan view and a graph for explaining an experiment carried out by the present inventors.

5 is a cross-sectional view and a graph for explaining an experiment conducted by the present inventors.

6 is a sketch of a TEM photograph showing a cross-sectional configuration of a sample obtained as a result of an experiment.

7 is a cross-sectional view for explaining a multilayer wiring according to an embodiment of the present invention.

8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

9 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the embodiment of the present invention.

10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

11 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the embodiment of the present invention.

Fig. 12 is a sectional view schematically showing a projection phenomenon occurring in the A1 wiring in the via hole.

* Description of the symbols for the main parts of the drawings *

9: insulation area

11: Si substrate

12: Si oxide film

13: lower Ti layer

14: lower TiN layer

15: main conductive layer

16: upper Ti layer

17: upper TiN layer

18: A1-Ti reaction layer

19,24,27,32: Si oxide film

20 TiN layer

21: tungsten layer

25: Ti layer

26: A1-Cu conductive layer

28,33: SiN layer

31: p-type Si substrate

34: n-type well

36: field oxide film

38 p-type well

41: gate oxide film

42 polycrystalline Si layer

43: WSi layer

44 Si layer

G: gate electrode

46,47: LDD region

48: side spacers

49,50: high impurity concentration source / drain region

51: silicide layer

52: insulation layer

53: connection hole

54 Ti layer

55 TiN layer

56: tungsten layer

57: interlayer insulating film

58: TiN layer

59: tungsten layer

W1-W4, WT: Wiring Layer

P1-P4: Conductive Plug

H1, H2: Connection port

T-T8: Pad

According to one aspect of the present invention, in a semiconductor device having a multilayer wiring, at least one wiring layer of the multilayer wiring is formed on or under the main conductive layer formed of A1 or A1 alloy and in contact with the main conductive layer. A semiconductor device having a multilayer wiring having a first high melting point metallurgy having a thickness of about 2 nm to about 7 nm is provided.

According to another aspect of the present invention, in the multilayer wiring including a laminated structure in which each of the main conductive layer and the high melting point metal layer of A1 or A1 alloy is laminated in direct contact, the thickness of the high melting point metal layer is a lower layer wiring. There is provided a semiconductor device having a multilayer wiring that monotonically decreases.

According to another aspect of the present invention, there is provided a step of overlapping a plurality of wiring layers including a laminated structure in which the main conductive layer of A1 or A1 alloy and the high melting point metal layer are stacked in direct contact with each other to produce a multilayer wiring, and thus the upper wiring. There is thus provided a method of manufacturing a semiconductor device in which wiring formation conditions are selected to allow a reaction between A1 and a high melting point metal.

It is known that when an A1 (A1 alloy) layer and a high melting point metal layer are contacted and laminated, and heat treatment is applied, an alloy of A1 and a high melting point metal (A1 ₃ Ti when the high melting point metal is Ti) is formed and the resistance is high. To form a barrier layer of high melting point metal nitride on the main conductive layer of A1 (A1 alloy), the surface of the main conductive layer of A1 (A1 alloy) during sputtering of a high melting point metal in an atmosphere containing N ₂ There is a possibility that A1 nitride is formed at.

When A1 nitride is formed on the main conductive layer, the contact resistance of the wiring layer is significantly increased. In order to prevent the formation of A1 nitride, it is effective to form a thin high melting point metal layer before forming the high melting point metal nitride layer. This inevitably results in an Al alloy / high melting metal stack.

According to an experiment conducted by the present inventors, if the thickness of the high melting point metal layer on the main conductive layer of A1 (A1 alloy) is selected to be 4 to 7 nm, it is remarkably effective in preventing the increase in the resistance value in use and extending the life. It was judged.

The reaction of A1 with the high melting point metal consumes A1 to increase the resistance of the wiring layer, but increases the resistance to electromigration. Thus, to some extent, it may be desirable to allow the reaction of A1 with the high melting point metal.

The wiring layer constituting the multilayer wiring receives different thermal history depending on its level.

As the rise wiring becomes, the amount of heat treatment received decreases. In a multilayer wiring having A1 (A1 alloy) / high melting metal stack, when the reaction between A1 and the high melting metal proceeds, the degree of reaction decreases as the upper wiring becomes. By selecting the wiring formation conditions, it is possible to control the reaction between A1 and the high melting point metal.

In order to prevent excessive reaction between A1 and the high melting point metal in the lower layer wiring, the thickness of the high melting point metal layer may be monotonously reduced as the lower layer wiring is formed, or the wiring formation temperature may be monotonously increased as the upper layer is formed. The bad effect by alloying A1 and a high melting point metal can be suppressed, and a good effect can be ensured.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Experiments performed by the present inventors and the results will be described sequentially. Ti was used as the high melting point metal.

The properties of the laminated wirings as shown in FIG. 1A were examined. The sample is composed of an insulating layer 12 such as a field oxide film formed on the surface of the Si substrate 11, and the lower Ti layer 13, the lower TiN layer 14, and A1 serving as a main conductive layer thereon. -The Cu alloy layer 15, the upper Ti layer 16, and the upper TiN layer 17 are laminated. One wiring layer W is formed by laminating five layers from the lower Ti layer 13 to the upper TiN layer 17.

In this configuration, the A1-Cu alloy layer 15 is directly in contact with the upper Ti layer 16, and alloy generation by heat treatment becomes a problem. In the prior art, the upper Ti layer 16 is formed to a thickness of about 20 nm. Although a wiring structure in which the upper Ti layer 16 is not formed is also known, when A1 nitride is formed on the surface of the A1-Cu alloy layer 15 when the upper TiN layer 17 is formed, a plug or the like is formed thereon. The contact resistance of becomes high.

The sample used in the experiment demonstrated below was created on condition of the following.

A thermal oxide film (SiO ₂ ) was grown to a thickness of 100 nm on the Si substrate, and the laminated wiring layer was grown by sputtering thereon. The lower Ti layer 13 and the upper Ti layer 16 were formed at sputtering power of 2 kW and Ar gas pressure of 1 mTorr. The lower TiN side 14 and the upper TiN layer 17 were grown at a sputtering power of 5 kW, an Ar: N gas flow rate ratio of 1: 1, and an atmospheric gas pressure of 3 mTorr. The A1-0.5% Cu alloy layer 15 was grown at a sputtering power of 10 kW and an Ar gas pressure of 3 mTorr. In addition, the sputtering apparatus was used for the multi-chamber system which performs a vacuum conveyance.

As for the resistance of the laminated wiring layer W, the initial sheet resistance was measured immediately after the initial preparation, and after that, a plurality of heat treatments were performed in units of heat treatment at 400 ° C. for 30 minutes, and the sheet resistance was measured each time the heat treatment was performed. The resistance measurement measured 9 points in a wafer by overcurrent, and calculated | required the average.

1B is a graph showing the change in sheet resistance with respect to the recovery of heat treatment. In the figure, the curve R0 forms the lower TiN layer 14 and the A1 alloy layer 15 on the lower Ti layer 13 having a thickness of 20 nm, and does not form the upper Ti layer 16. The sample in which the upper TiN layer 17 was formed is shown. Curve R1 represents a sample in which the upper Ti layer 16 having a thickness of 5 nm is formed on the A1 alloy layer 15. Curve R1 represents a sample in which the upper Ti layer 16 having a thickness of 10 nm is formed on the A1 alloy layer 15. Curve R3 represents a sample in which the upper Ti layer 16 having a thickness of 20 nm is formed on the A1 alloy layer 15.

As can be seen from the figure, the resistance increases as the heat treatment is repeated in each sample. Comparing the characteristics between the samples, the sample R0 without the upper Ti layer 16 has the lowest resistance, and the resistance increases as the thickness of the upper Ti layer 16 in contact with the A1 alloy layer 15 increases. Becomes large. As a result, the upper the Ti layer 16 is, the lower the resistance of the wiring layer is, and the resistance of the wiring layer is lower than that in which the upper Ti layer is not provided than when the upper Ti layer is provided.

FIG. 2: shows the structure of the sample in which the multilayer wiring was formed using the laminated wiring layer as a base unit as shown in FIG. 1A.

On the Si substrate 11, the Si oxide film 12 by plasma TEOS (tetraethoxysilane) was grown 500 nm in thickness. On the Si oxide film 12, the 1st wiring layer W1 was created by the same process as the sample demonstrated with reference to FIG. 1A. The resist pattern was created on the 1st wiring layer W1, and the wiring shape was processed according to the resist pattern by reactive ion etching (RIE).

The silicon oxide film 19 was grown to a thickness of 2000 nm so as to cover the first wiring layer W1, and the surface was flattened by chemical mechanical polishing (CMP). The resist pattern which has the opening corresponding to the wiring layer connection part was created on the surface of the Si oxide film 19, and the connection hole H1 was formed by RIE. After the RF reverse sputter cleaning was performed to wash the inside of the connection hole, the TiN layer 20 was formed by 50 nm thickness sputtering, and then the tungsten layer 21 was formed by 500 nm thickness CVD. Subsequently, the W layer is entirely etched by dry etching, leaving the W region 21 only inside the connection hole H1.

The TiN layer 20 and the tungsten region 21 in the connection hole H1 constitute the conductive plug P1. On the surface of the interlayer insulating layer 19 including the plug P1, a second wiring layer W2 having the same configuration as that of the wiring layer W shown in Fig. 1A was formed. The resist pattern was formed on the 2nd wiring layer W2, and it processed by RIE, and obtained the pattern of the 2nd wiring layer W2. As a result, the first wiring layer W1 and the second wiring layer W2 are electrically connected through the plug P1.

Moreover, 2000 nm of Si oxide films 24 were formed by CVD so that the 2nd wiring layer W2 might be covered, and the surface was planarized by CMP. A connection pattern H2 was formed by forming a resist pattern on the surface of the interlayer insulating layer 24 and performing RIE. The uppermost wiring was formed so as to fill this connection hole. The uppermost layer wiring was performed by growing Ti (25) with a thickness of 30 nm and A1-Cu alloy layer 26 with a thickness of 600 nm after washing the inside of the connection hole by RF reverse sputtering. On the uppermost wiring, a resist pattern was formed, and the uppermost wiring layer was patterned.

A 2000 nm thick Si oxide film 27 was formed by plasma CVD to cover the uppermost wiring layer, and a 500 nm thick SiN film 28 was grown thereon. Pad holes were formed through the SiN film 28 and the Si oxide film 27 to expose a desired region of the uppermost wiring. Thereafter, the back surface of the Si substrate 11 was ground. About the sample thus created, heat treatment at 400 ° C. for 30 minutes was repeated.

3 shows the Ti layer thickness dependency experiment of the via resistance by Kelvin pattern.

3A schematically illustrates the formation of a Kelvin pattern. The first wiring layer W1 is bent at an almost right angle in the middle portion and is connected to the second wiring layer W2 by the plug P in the connection hole at the bent portion. The first wiring layer W1 and the second wiring layer W2 are connected to the pads T1, T2, T3, and T4 at both ends, respectively. The via resistance is measured by allowing a current i to flow from the pad T1 to the pad T3 and measuring the voltage between the pads T2 and T4. Moreover, the width | variety of the wiring layer was 0.54 micrometer, and the via hole was 0.44 micrometer in diameter. The resistance was measured at four points using a normal probe. As a sample, the thickness of the upper Ti layer was changed into 0 nm, 5 nm, 10 nm, and 20 nm, and 108 samples of the same structure were used, respectively.

3B is a graph showing a measurement result. In the figure, the abscissa represents the Kelvin via resistance in units of Ω, and the ordinate represents the cumulative frequency of the appearance of the same Kelvin via resistance in%.

Curves CP0, CP1, CP2, and CP3 represent samples with thicknesses of the upper Ti layer of 0 nm, 5 nm, 10 nm, and 20 nm, respectively. In the figure, the measuring point has a higher resistance toward the right side, and shows a bad result. Further, the lower the slope of the curve, the wider the distribution, and the worse the result. The curve CP0 without the upper Ti layer has a bad resistance and a bad distribution.

The curves CP1, CP2, CP3 in which the upper Ti layer is formed have a significantly lower resistance to the curve CP0 having no upper Ti layer, and the slope of the curve is also abrupt, resulting in a narrower distribution and improved results. Indicates. In addition, the difference by the thickness of the upper Ti layer is not very stable. From this result, in the structure which connects between wiring layers through a plug, it is very preferable to form an upper Ti layer, and it is judged that it is indispensable.

4 shows an experiment of electromigration in a single wiring layer. 4A is a schematic plan view showing a wiring pattern of a sample. The wiring layer W has pads T5 and T6 at both ends, and a current flows from the pad T5 toward the pad T6. The pads T7 and T8 are further connected in the middle of the wiring layer W, and the voltage drop in the wiring layer is measured.

The sample used for this experiment is the structure as shown in FIG. 1A, The Si oxide film 12 of plasma TEOS is grown 500 nm in thickness on the Si substrate 11, and is laminated on it by the process demonstrated with reference to FIG. 1A. The wiring layer W was formed. The thickness of the upper Ti layer was changed to 0 nm, 5 nm, 10 nm, and 20 nm as in the case described above. On this wiring layer, a resist pattern was formed, RIE was performed, and the wiring layer W was patterned. The width of the wiring pattern W was changed to 0.6 micrometer, 2 micrometers, and 8 micrometers. On the wiring layer W, a 2000 nm Si oxide film of plasma TEOS was grown and planarized by CMP to form an insulating film. Openings that penetrated through the insulating film and reached the pads were formed by patterning using a resist pattern and RIE. Thereafter, annealing at 450 ° C. for 30 minutes was performed 10 times.

In the evaluation method in the experiment, current flows through both ends T5 and T6 of the wiring W, and the resistance value is monitored. When the resistance value increases by 20%, the sample is judged to be defective. Twenty samples are tested under the same conditions, and assuming that the number of defects follows the lognormal distribution, 50% failure time t50 where 50% becomes defective is evaluated. Current density was set to 20 MA / cm <2> in common in the sample of each wiring width. That is, when the wiring layer width is wide, much current flowed by that much. The standing temperature of the sample was 250 degreeC.

4B is a graph showing the experimental results. The horizontal axis represents the thickness of the upper Ti layer in unit nm, and the vertical axis represents the 50% defective time t50 in unit time (hrs).

Curve L1 representing a sample having a wiring width of 0.6 μm indicates a maximum value at a thickness of 5 nm of the upper Ti layer, and shows a result of decreasing as the thickness of the second Ti layer becomes thicker. In addition, 50% defective new sheets when not having an upper Ti layer are reduced by one or more orders of magnitude from the maximum value. The curve L2 representing a sample having a wiring width of 2 μm has the shortest 50% failure time when the upper Ti layer is not formed, and the 50% failure time when the upper Ti layer is formed, regardless of its thickness. t50) represents an improved almost constant value.

The curve L3 representing a sample having a wiring width of 8 μm shows a 50% failure time t50 when the upper Ti layer does not have a minimum value, and a 50% failure time as the upper Ti layer becomes 5 nm and 10 nm. t50) is improved.

The result shown in FIG. 4B shows the behavior changed by the wiring width. When the wiring width was wide (2 µm, 8 µm), when the TiN layer was grown directly on the A1 alloy layer, the life was shortened. This is consistent with a generally known fact. When the wiring width is narrow (0.6 mu m), the thickness of the upper Ti layer shows a characteristic maximum around 5 nm. More specifically, the test was conducted for 2853 hours and only 3 out of 20 samples were defective.

5 shows an experiment of length dependence electromigration (LDEM).

5A schematically shows a configuration of a sample. On the Si substrate 11, a Si oxide film 21 having a thickness of 500 nm is formed by plasma TEOS, and the first wiring layers W11, W12, ..., and the second wiring layers W21, W22, ... are formed thereon. The structure which connected the through the plug P1, P2, ... was created. Creation of a wiring structure is the same as the process described with reference to FIG. 2. After back grinding of the Si substrate, heat treatment at 400 ° C. for 30 minutes was performed five times.

The shape of the sample is 0.54 micrometer in wiring width, and the diameter of the connection hole which forms plug P1, P2, ... is 0.5 micrometer. The first wiring layers W11, W12, ... and the second wiring layers W21, W22, ... were alternately connected by plugs P1, P2, ....

The length of the wiring layer is 2 μm (W11) -2 μm (W21) -5 μm (W12) -5 μm (W22) -10 μm (W13) -10 μm (W23) -20 μm (W14) -20 μm ( W24) -50 micrometers (W15) -50 micrometers (W25) -100 micrometers (W16) -100 (W26) -200 micrometers (W17) -200 micrometers (W27) It connected gradually.

The measurement kept the sample in 250 degreeC atmosphere, made the electric current of 2 mA flow through the pattern, and monitored the resistance of the connected wiring every 5 minutes. When the resistor is 20% higher than the initial resistance, the wiring is defined as defective. Twenty samples were evaluated under the same conditions, and 50% failure time t50 was calculated assuming that the defective number was in the lognormal distribution.

5B shows the measurement result. The horizontal axis represents the thickness of the upper Ti layer in unit nm, and the vertical axis represents the 50% defective time t50 in unit time (hrs). Curve L4 shows the LDEM for the connection wiring whose wiring layer tip is 0.54 µm. When the thickness of the upper Ti layer is from 0 nm to 5 nm, the 50% failure time of the LED is slightly improved. As the thickness of the upper Ti layer increases from 5 nm to 10 nm, the 50% failure time t50 of the LEDM decreases rapidly, and then increases more slowly if the thickness of the upper Ti layer is increased.

When the thickness of the upper Ti layer is 20 nm, the maximum value can be used even at 50% defective time, but the margin is small, which is a strict condition for management. When the thickness of the second Ti layer is 10 nm, the service life is slightly longer. In the case where the thickness of the second Ti layer is 5 nm, the service life is significantly long, and very excellent results are obtained.

Even when the upper Ti layer is not prepared, a slightly better result is obtained when the upper Ti layer is 5 nm thick. However, as shown in the experimental result of FIG. 3B, when the upper Ti layer is not used, the value of the via resistance increases, and as shown in the experimental result of FIG. 4B, the 50% failure time in the same wiring layer is lowered.

In summary, in the case of forming a Ti layer in direct contact with the A1 (A1 alloy) layer, it is judged that a critically superior result is obtained by selecting the thickness within the range of 2 nm to 7 nm, more preferably 4 nm to 7 nm. do.

6 shows a sketch of a cross-sectional TEM photograph after heat treatment of a sample in which the thickness of the upper Ti layer is changed. 6A shows the case where the upper Ti layer 16 is 5 nm in thickness. The A1 alloy layer 15 forms crystal grains, and the A1-Ti reactant region 18 which the upper Ti layer and A1 reacted in the grain boundary region which a crystal grain contacts is shown. However, on the A1 crystal grain, the upper Ti layer 16 hardly reacts with A1, and the Ti layer remains as it is.

6B shows a cross-sectional structure of a sample in which the thickness of the upper Ti layer is 10 nm. In this sample, the upper Ti layer disappears even above the grains of the A1 alloy layer 15, and the A1-Ti reactant 18 in which A1 and Ti reacted is formed. The A1-Ti reactant is recognized as Al ₃ Ti, and has a thickness increased from the initial upper Ti layer (thickness 10 nm).

Fig. 6C shows the structure of the sample in the case where the thickness of the upper Ti layer is 20 nm. Even above the grains of the A1 alloy layer 15, the upper Ti layer disappears, and the A1-Ti reactant 18 is formed thicker, and the thickness of the A1 alloy layer 15 becomes thinner.

Although the reason is still unknown, when a thin Ti layer is formed on the A1 (A1 alloy) layer, it is judged that the reaction of A1 and Ti is suppressed even when the heat treatment is performed, and the A1-Ti reaction proceeds only at the grain boundary.

When reaction of A1 and Ti occurs, it is judged that the thickness during reaction is determined according to the thickness of Ti layer. Therefore, the thickness of the A1-Ti reaction layer will be determined by the thickness of the Ti layer and the heat treatment conditions.

In summary, including the results of FIG. 6, in the multilayer wiring structure in which the wiring layers are connected by a plug, it is desirable to form a thin Ti layer on the A1 (A1 alloy) layer, and the thickness of the Ti layer. It is preferable to set it as about 2 nm-about 7 nm, and it is more preferable to set it as about 4 nm-7 nm. It is particularly difficult to produce a Ti layer having a thickness of 2 nm in terms of process management, and considering the ease of manufacturing process management, it is particularly preferable to have a thickness of about 4 nm to about 7 nm.

7 schematically shows a multilayer wiring structure according to an embodiment of the present invention.

The connection region 10 is formed in the Si substrate 11, and the plug P1 is connected thereon.

The first wiring layer W1 is connected to the plug P1 and connected to the plug P2 on the upper surface thereof.

The second wiring layer W2 is connected to the plug P2 and connected to the plug P3 on its upper surface.

The third wiring layer W3 is connected to the plug P3 and connected to the plug P4 on its upper surface.

The fourth wiring layer W4 is connected to the plug P4. These multilayer wirings are insulated from the surroundings by the insulating region 9.

7B shows a laminated structure of wiring layers other than the wiring layer of the uppermost layer. Each wiring layer W has a Ti layer 13 at the bottom, and a TiN layer 14 is formed thereon. An A1 (A1 alloy) layer 15, which is a main conductive layer, is formed on the TiN layer 14, and the Ti conductive layer 16 has a thickness of 2 to 7 nm, more preferably 4 to 7 nm, on the surface of the main conductive layer 15. This is covered. The TiN layer 17 is formed on this Ti layer 16. By setting the thickness of the Ti layer 16 directly in contact with the main conductive layer 15 to 2 to 7 nm, more preferably 4 to 7 nm, the resistance of the wiring layer can be suppressed low and the life can be kept long.

7C shows the laminated structure of the uppermost wiring. The uppermost wiring layer WT is composed of a stack of a Ti layer 13, a TiN layer 14, an A1 or A1 alloy layer 15, and does not have a Ti layer or a TiN layer thereon. Since the uppermost wiring layer does not need to be connected by a plug, the upper Ti layer and the TiN layer are unnecessary.

In addition, electromigration is known to be particularly likely to occur at the A1 grain boundary. When the A1-Ti reaction occurs at the A1 grain boundary, the resistance to electromigration is expected to be improved. For this purpose, it is preferable to cause some A1-Ti reaction.

In the multilayer wirings, the amount of heat treatment decreases as the upper wirings become. In view of this point, in a multilayer wiring in which the multilayer wiring includes a stack of A1 (A1 alloy) layer-Ti layer, it is preferable to make the thickness of the Ti layer thin as much as it goes to the lower wiring.

For example, in the multilayer wiring, the thickness of the Ti layer in direct contact with the A1 (A1 alloy) layer is monotonously increased, such as 5 nm, 10 nm, and 20 nm, from the lower layer to the upper layer. In order to prevent excessive reaction of A1-Ti, you may increase as 5 nm, 10 nm, 20 nm, ... from the lower layer toward the upper layer. Considering the process margin, the change in thickness can be set in various ways.

In addition, when forming a multilayer wiring, as the upper wiring is made using Ti layers of the same thickness, the wiring formation temperature may be made high.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described taking the case of manufacturing a CMOS semiconductor device as an example.

As shown in FIG. 8A, the SiN film pattern 33 is formed on the surface of the p-type Si substrate 31 via the buffer oxide film 32. The SiN film pattern 33 can be used as an oxidation mask in LOCOS (local oxidation of silicon). A region covered with the SiN film pattern 33 becomes an active region, and a field oxide film is formed in the other region.

In order to form an n-type well for forming a p-channel MOSFET, a resist pattern R1 having an opening in an n-type well region is created. Using this resist pattern R1 as a mask, P ions are implanted into the p-type Si substrate 31 through the SiN film 33 and the buffer oxide film 32. Thus, after ion implantation for n type well formation is performed, resist pattern R1 is removed, thermal oxidation is performed in an oxidizing atmosphere, and an oxide film is grown by a LOCOS process.

As shown in Fig. 8B, after forming the field underlayer 36, a resist mask R2 covering the n-type well 34 is formed, and B-ion implantation for p-type well formation is performed. The P type well 38 is formed by B ion implantation. Thereafter, the resist mask R2 and the SiN film pattern 33 are removed. Subsequently, the buffer oxide film on the n-type well 34 and the p-type well 38 is also removed.

As shown in Fig. 8C, a gate oxide film 41 is formed on the exposed active region surface by thermal oxidation. On the gate oxide film 41, the polycrystalline Si film 42 is grown by CVD, and the WSi layer 43 is grown by CVD or PVD as necessary. In addition, as needed, the SiO ₂ film 44 is grown on the WSi layer 43 by CVD.

In addition, when the polycrystalline Si film 42 and the WSi layer 43 are grown, these laminations form the gate electrode layer (G). When the gate electrode layer is formed only of the polycrystalline Si layer, the silicide film is formed on the polycrystalline Si film in the silicide reaction step performed thereafter.

After the lamination structure for the gate electrode is formed, a resist pattern R3 is formed on the lamination, and the gate electrode is patterned. After patterning the laminated structure, the resist mask R3 is removed.

As shown in Fig. 9A, a resist mask R4 having an opening exposing the p-type well 38 is formed, and ion ion is implanted to form the n ⁻ layer 46 for LDD. Thereafter, resist mask R4 is formed. Using the resist mask R5 as a mask, BF ₂ ions are ion implanted to form the p ⁻ region 47 for LDD. Thereafter, the resist mask R5 is removed.

As shown in Fig. 9B, the SiO film is formed on the entire surface of the substrate by covering the gate electrode by CVD, and the gate side well 48 is formed only on the gate electrode sidewall by performing anisotropic etching. The top surface of the gate electrode is also covered with the oxide film 44a.

As shown in Fig. 9C, As is ion-implanted into the p-type well 38 using a resist mask as shown in Fig. 9A, a source / drain region 39 having a high impurity concentration is formed, and the n-type well BF ₂ is implanted into 34 to form source / drain regions 50 of high impurity concentration.

As shown in Fig. 10A, a Ti layer is deposited on the entire surface of the substrate and heat treatment is performed to form a TiSi layer 51 on a region where Si is exposed. After this silicide reaction, the unreacted Ti layer is removed. In addition, CoSi layer may be formed using Co instead of Ti.

In FIG. 8C, when the gate electrode is formed of only the polycrystalline Si layer and no SiO ₂ film 44 is formed, the silicide layer is also formed on the polycrystalline gate electrode layer.

10B shows this case. A TiSi layer 51 is formed on the source / drain regions 49 and 50 and the polycrystalline silicon gate electrode 42 by depositing a Ti layer on the entire surface of the substrate and performing a silicide reaction by performing a heat treatment.

In this manner, after the CMOS structure is formed, the interlayer insulating film 52 is formed on the surface. The interlayer insulating film 52 is a laminate of a silicon oxide layer 52a and an SOG layer 52b by CVD. After the SOG film is formed, the surface is planarized by CMP. Thereafter, the contact hole 53 is formed using a resist mask.

As shown in FIG. 11A, the Ti layer 54 and the TiN layer 55 are deposited on the surface of the insulating layer 52 on which the connection hole 53 is formed and on the inner surface of the connection hole 53. The tungsten layer 56 is grown by CVD to fill the connection holes. Thereafter, the entire surface is etched to remove the tungsten layer 56 on the upper flat surface.

Thereafter, a first wiring layer W1 formed of a stack of a Ti layer 13, a TiN layer 14, an A1 or A1 alloy layer 15, a Ti layer 16, and a TiN layer 17 is formed. Patterning is performed using a resist mask. At this time, the upper Ti layer 16 has a thickness of 2 to 7 nm.

Although the case where the tungsten layer is removed by etching has been described, the tungsten layer on the flat surface may be removed by CMP.

11B shows this case. After the tungsten layer is formed, CMP is performed to expose the flat surface of the insulating layer 52. In the connection hole 53, the Ti layer 54, the TiN layer 55, and the W region 56 remain. Thereafter, the first wiring layer W1 is formed.

As shown in FIG. 11C, after the first wiring layer W1 is formed, an interlayer insulating film 57 is formed to planarize the surface thereof. The connection hole is formed in the interlayer insulating film 57, the TiN layer 58 and the W layer 59 are formed, and the W layer on the flat surface is removed by etching. In this way, a plug penetrating the interlayer insulating film 57 is formed.

The W layer on the flat surface may be removed by CMP in addition to the above-described etching. 11D shows this case. After the tungsten layer is formed, CMP is performed to expose the surface of the interlayer insulating film 57 to form a planarized surface.

Thereafter, the same steps as those shown in FIGS. 11A and 11B are performed to form the second wiring layer. Thereafter, the processes of forming an interlayer insulating film, forming a connection hole, forming a plug, and forming a wiring layer are repeated to obtain a multilayer wiring structure having the required number of layers. In each wiring layer, it is preferable to form a Ti layer with a thickness of 2 to 7 nm on the main conductive layer of A1 or A1 alloy.

In addition, when actively forming an A1-Ti alloy region at the grain boundary of the main conductive layer, the thickness of the Ti layer may be increased. In this case, in consideration of the history of the heat treatment in the multilayer wiring, it is preferable to increase the thickness of the Ti layer toward the upper layer (to decrease the thickness of the Ti layer toward the lower layer). When the thickness of the A1 (A1 alloy) layer is changed according to the level such as becoming thicker as the upper layer, the ratio of the thickness of the Ti layer to the thickness of the A1 (A1 alloy) layer is preferably monotonically reduced as the lower layer. .

As shown in Fig. 12, for several years, a phenomenon has been reported that Al wirings in via holes bulge in the form of protrusions during heat treatment after hole opening. The wiring layer W is formed on the insulating layer 9a, and the surface is covered by the insulating layer 9b. The via hole H which penetrates the insulating layer 9b and reaches the wiring layer W is formed. Thereafter, when heat treatment is performed to form the upper layer wirings, the projections PJ are formed in the via holes H. The parameter for determining this is considered to depend on the heat treatment during growth of the upper layer wiring (for example, the second layer wiring) and the thickness (strength) of TiN / Ti on the upper portion of the lower layer wiring (for example, the first layer wiring).

This phenomenon is explained by the fact that the thermal expansion coefficient is different, and therefore A1 is extruded into the via hole due to the stress from the surrounding insulating film. Therefore, it can be easily imagined that the thicker the TiN / Ti on the A1 phase, the less likely to occur, and the lower the heat treatment during the growth of the upper wiring layer.

However, in the above-described embodiment, in order to improve the reliability, the thickness of Ti and the thickness of the A1-Ti reaction layer are also reduced. When the reaction layer is thin, there is a possibility that protrusion defects tend to occur. In order to prevent the amount of protrusions, it is advantageous to thicken the Ti layer (TiN / Ti) little by little in the second wiring layer even if the Ti of the first wiring layer is thin. If possible, it is more preferable to react A1 and Ti to prevent projection defects. However, if Ti suddenly raises the heat treatment temperature in a thin state, projections occur at that point. Therefore, it is preferable not to react at a low temperature on the first layer, but to perform stepwise strengthening such as slightly thickening from the second layer or raising the temperature to react. Do.

As a general tendency, the thickness of the wiring layer tends to become thicker as it goes to the upper wiring, and considering the sheet resistance, it is advantageous for the defect to be made to react with a relatively thick Ti thickness.

In addition, in consideration of the margin in the manufacturing process, the thickness (or ratio of the thicknesses) of the Ti layer may be the same for all wiring layers. In this case, it is preferable to make the heat processing temperature at the time of wiring layer formation high, so that it goes to an upper layer.

After the uppermost wiring layer is formed, a Si oxide film (PSG or the like), an SOG film, a SiN cover film, or the like is grown as an insulating film. Thereafter, the opening for pad formation is formed by RIE using a resist pattern. Finally, annealing in a hydrogen atmosphere is performed, and back grinding is performed to complete the semiconductor device.

As mentioned above, although the case where Ti is used as a high melting-point metal layer was demonstrated, other high melting metals, such as W, can also be used. In this case, TiN may be a high melting point metal nitride of WN.

Although the present invention has been described in accordance with the above embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, alterations, combinations, and the like are possible.

As described above, according to the present invention, there is provided a semiconductor device having a low-resistance of wiring including contact resistance and having high reliability for electromigration or the like.

Claims (14)

In a semiconductor device having a multilayer wiring, at least one wiring layer of the multilayer wiring is A main conductive layer formed of A1 or A1 alloy; And a first high melting point metal layer formed on or in contact with the main conductive layer and having a thickness of about 2 nm to about 7 nm. The method of claim 1, wherein the first high melting point metal layer is a layer formed on the main conductive layer, and the at least one wiring layer, A first high melting point metal nitride layer formed on the first high melting point metal layer; A second high melting point metal nitride layer formed in contact with said main conductive layer; And a second high melting point metal layer formed under said second high melting point metal nitride layer. The semiconductor device according to claim 2, wherein the multilayer wiring has another wiring layer adjacent to the at least one wiring layer in a stacking direction and having the same laminated structure as the at least one wiring layer. 3. The semiconductor device according to claim 2, wherein the multilayer wirings have the same laminated structure except for the uppermost wiring layer. The semiconductor device according to any one of claims 1 to 4, further comprising a tungsten plug in an adjacent wiring layer of the multilayer wiring. In the multilayer wirings each including a laminated structure in which the main conductive layer of A1 or A1 alloy and the high melting point metal layer are directly connected and laminated, the monolayer decreases as the thickness of the high melting point metal layer becomes the lower layer wiring. A semiconductor device having a multilayer wiring. 7. The semiconductor device according to claim 6, wherein the thickness of the high melting point metal layer with respect to the thickness of the main conductive layer decreases monotonously as it becomes a lower layer wiring. 8. The semiconductor device according to claim 6 or 7, wherein the main conductive layer contains more reaction products of A1 and higher melting point metals in the grain boundaries than in the grain boundaries. Manufacturing a multilayer wiring by stacking a plurality of wiring layers including a laminated structure in which a main conductive layer of an A1 or A1 alloy and a high melting point metal layer are directly contacted, and manufacturing a multilayer wiring. A method for manufacturing a semiconductor device, characterized in that the wiring forming conditions are selected to allow reaction. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the wiring formation conditions monotonically increase the thickness of the high melting point metal layer as the upper layer is formed. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein the wiring formation conditions monotonically increase the ratio of the thickness of the high melting point metal layer to the thickness of the main conductive layer as the upper layer becomes. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the wiring formation conditions monotonically increase the wiring formation temperature as the upper layer becomes. The semiconductor device according to any one of claims 1 to 8, wherein the high melting point metal is Ti and the high melting point metal nitride is TiN. The method for manufacturing a semiconductor device according to any one of claims 9 to 12, wherein the high melting point metal is Ti and the high melting point metal nitride is TiN.