KR19980067903A - Bias voltage generator for liquid crystal display and method thereof - Google Patents

Abstract

A bias voltage generator for a liquid crystal display (LCD) driver and a method thereof.

The voltage divider includes a resistor of the first resistor connected in series and is arranged to form a direct current path having a node. The voltage at each node serves as a bias voltage for the LCD driver, which acts to cause the LCD driver to generate an LCD drive signal. The signal generator is used to generate a switching signal simultaneously with the LCD drive signal. In the switching circuit including the switch, when the switch is closed, the resistance between two adjacent nodes has a small value, which makes a large drive current with the LCD driver. When the switch is opened, the resistance value becomes large, and the amount of lost current flowing out of the DC current path is increased. Is arranged to reduce

Description

Bias voltage generator for liquid crystal display and method thereof

The present invention relates to a liquid crystal display (LCD), and more particularly, to an apparatus and method for generating a bias voltage for a liquid crystal display driver.

Liquid crystal displays are digital displays that are widely used in digital watches, calculators, portable game consoles, and many other electronic devices. 1 shows a circuit structure of a typical liquid crystal display. In FIG. 1, the LCD driver 10 is used to drive the LCD panel 30 together with the voltage divider 20. As shown in FIG. In practice, the LCD driver 10 and the voltage divider 20 are provided in the integrated circuit IC indicated by the dotted line 1. The voltage divider 20 includes a plurality of resistors R for dividing the external voltage Vcc into bias voltages Va, Vb, Vc, Vd, and Ve. This bias voltage is applied to the LCD driver 10 and drives the LCD driver to generate a plurality of LCD drive signals including a common signal via the COM1 to COM8 lines and a segment signal via the SEG1 to SEG40 lines.

In the voltage divider 20, the plurality of resistors R constitute a DC current path through which the DC current Id flows. The resistor has a high resistance of 100 kΩ or 200 kΩ to minimize the current Id flowing through the DC current path. The drawback of using a high resistance resistor is that the resulting drive current used to act on the LCD driver to switch the LCD drive signal may not be sufficient.

In order to cope with this problem, a conventional method is to provide a number of corresponding CAPACOTOR (C) which are externally connected to the voltage divider 20 via the I / O pin in the IC 1. The capacitor C is used for voltage stabilization of the circuit to supply sufficient operating current It to the LCD driver for switching the LCD drive signal.

As mentioned earlier, ICs based on circuit architecture for generating bias voltages include the MSM5238GS, MSM5259GS, and MSM5278, products of Oki Semiconductor Corporation. However, having an externally connected capacitor involves two drawbacks. First, in a low cost portable LCD game machine, the externally connected capacitors and corresponding I / O pins significantly increase the manufacturing cost and increase the chip size as the number of I / O pins on the IC increases. It is to enlarge. Two methods have been used to solve the above drawbacks. The first method is to avoid the use of capacitors and reduce the resistance of resistor R so that the value of DC current Id becomes large. However, this makes the loss current large. For example, assuming that R = 100 kΩ and Vcc = 5 volts in the circuit of Figure 1, Id = 5 / (100 kx5) = 10 μA. However, reducing R = 15kΩ yields Id = 5V / (15kΩx5) = 67μA. ICs require only a small amount of current to operate, so large currents such as 67μA can waste a lot of power.

The second method is to have an embedded capacitor in the IC. However, this increases the chip area and the capacity of such capacitors is several orders of magnitude lower than desired.

It is an object of the present invention to provide a bias voltage generator and method for an LCD driver for supplying sufficient operating current to an LCD driver without the need of an externally connected capacitor.

It is still another object of the present invention to provide a bias voltage generator and method for LCD drivers capable of supplying sufficient operating current even when a resistor having a high resistance is used in a voltage divider.

1 is a block diagram showing a circuit configuration for generating a bias voltage for a conventional liquid crystal display driver.

2 is a block diagram of a bias voltage generator according to the present invention.

3 is a block diagram showing an embodiment of a bias voltage generator according to the present invention.

Figure 4a is a block diagram showing another embodiment of the bias voltage generator according to the present invention.

FIG. 4B is a block diagram of a switching circuit utilized in the bias voltage generator of FIG. 4A.

4C is a circuit diagram equivalent to the switching circuit of FIG. 4B.

5 is a circuit diagram of yet another embodiment of a bias voltage generator according to the present invention.

6 is a waveform diagram of a control signal used in the bias voltage generator according to the present invention.

7 is a waveform diagram of a signal used to drive a liquid crystal display.

In accordance with the above and other objects of the present invention, a new and improved apparatus and method for generating bias voltage for LCD drivers is provided.

An embodiment of the apparatus according to the present invention comprises a voltage divider which forms a DC current path having a plurality of nodes and is composed of a plurality of continuously connected first resistors, a signal generator which generates a switching signal synchronously with the LCD driving signal, And a switching circuit comprising a plurality of switching units connected across the corresponding resistors in the voltage divider. Here, the voltage of each node serves as a bias voltage applied to act on the LCD driver to generate a plurality of LCD driving signals. Each switching unit is closed to connect with a second resistor across the corresponding first resistor when the LCD drive signal is switched, and vice versa, each switching unit is opened.

Another embodiment of the apparatus according to the present invention forms a direct current path with a plurality of nodes and a voltage divider consisting of a plurality of resistors of a first resistor connected in series, and generating a switching signal synchronously with the LCD drive signal. And a switching circuit comprising a signal generator and a plurality of transistor switching units each connected across a corresponding resistor in a voltage divider and having an internal resistor of a second resistor. Here, the voltage of each node serves as a bias voltage applied to act on the LCD driver to generate a plurality of LCD driving signals. Each transistor switching unit is closed to connect internal resistors across corresponding resistors in the voltage divider when the LCD drive signal is switched, and vice versa, each transistor switching unit is opened.

Another embodiment of the device according to the present invention is a voltage divider consisting of a plurality of first and second resistor pairs connected in series and forming a DC current path having a plurality of nodes, and a switching signal synchronously with the LCD driving signal. And a switching circuit including a signal generator for generating a plurality of switching units each connected across a corresponding second resistor in the voltage divider. Here, the voltage of each node serves as a bias voltage applied to act on the LCD driver to generate a plurality of LCD driving signals. Each switching unit is closed to short the corresponding second resistor when the LCD drive signal is switched, and vice versa, each switching unit is opened.

The method according to the invention comprises the following steps.

Generating a switching signal and applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, wherein the voltage divider comprises a plurality of first resistors connected in series and each node corresponding to each other adjacent thereto. Located between the first resistor pair, and opening and closing a plurality of switching units connected in series according to the switching signal, and connecting each second resistor in parallel with a corresponding first resistor when the switching unit is closed. It's a step. In the opening and closing of the switching unit, each switching unit includes a switch and a second resistor, and each switching unit is connected in parallel with one of the corresponding first resistors.

Another method according to the invention comprises the following steps.

Generating a switching signal and applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, wherein the voltage divider includes a plurality of pairs of first and second resistors connected in series and the first And each node at each end of the second resistor pair; opening and closing a plurality of switches continuously connected according to the switching signal, and invalidating the second resistor when the switch is closed. In the opening and closing of the switches, each switch is connected in parallel with one of the corresponding second resistors.

Another method according to the invention comprises the following steps.

Generating a switching signal and applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, wherein the voltage divider comprises a plurality of voltage divider resistors connected in series and each node corresponding to each other adjacent to each other. Located between the voltage divider resistor pairs; and opening and closing a plurality of transistor switching units connected in series according to the switching signal, and connecting each internal resistance in parallel with a corresponding voltage divider resistor when the transistor switching unit is closed. Step. In the opening and closing of the transistor switching unit, each transistor switching unit includes a transistor switch and an internal resistor, and each transistor switching unit is connected in parallel with one of the corresponding voltage divider resistors.

In general, the method of operation applicable to the present invention includes the following steps.

That is, generating a switching signal and applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, wherein the voltage divider includes a plurality of variable resistors connected in series and each node is adjacent to each other. And raising and lowering the resistance value of the variable resistor in accordance with a switching signal for generating a bias voltage for supplying a dynamic current flowing through the voltage divider-and between corresponding pairs of variable resistors.

In Fig. 2, a block diagram of a bias voltage generator 50 according to the present invention is illustrated. The bias voltage generator 50 is connected to an LCD driver 40 for driving the LCD panel 30. The bias voltage generator 50 includes a voltage divider 51 connected to the LCD driver 40, a switching circuit 53 connected to the voltage divider 51, and a system clock signal for generating a switching signal (LCD pulse). And a signal generator 55 for receiving SYSCK). The switching signal LCD pulse is provided to the switching circuit 53.

The signal generator also generates a CLK signal to the LCD driver 40. The LCD driver 40 is used to generate a plurality of LCD driving signals. The LCD driving signal includes a common signal provided to the LCD panel 30 via a COM1-COM8 line, and an LCD panel via a SEG1-SEG40 line. A segment signal provided to 30; The LCD driving signals COM1-COM8 and SGE1-SEG40 are simultaneously generated under the control of the LCD pulse signal and the CLK signal.

According to the invention, the switching circuit 53 is switched so that the resistance between adjacent nodes in the voltage divider 51 is lowered to provide an appropriate starting current during the switching of the COM1-COM8 and SEG1-SEG40 signals. The switching circuit 53 is always in the OFF state in other cases, which is to maintain a constant large value of resistance between adjacent nodes in the voltage divider 51, and the maintenance of the large resistance value is a circuit defined by the voltage divider. This is to minimize the current Id flowing through the path.

Various embodiments of the circuit structure of the bias voltage generator 50 are described next.

First embodiment

In Fig. 3, a circuit diagram of the first embodiment of the bias voltage generator 50 according to the present invention is shown. The voltage divider 51 is composed of a plurality of 100 kΩ resistors connected to the nodes a, b, c, d, e and connected to an external voltage source Vcc. This arrangement makes it possible to provide respective bias voltages Va, Vb, Vc, Vd, Ve at the nodes a, b, c, d, e for driving the LCD driver 40. Logic signal 'connected to node e via inverter 52' 'Is used to control the bias voltage Va, Vb, Vc, Vd, Ve in the manner shown in the following table.

[table]

The bias voltages Va, Vb, Vc, Vd and Ve are used to operate the LCD driver 40 to generate LCD drive signals COM1-COM 8 and SEG1-SEG40.

The switching circuit 53 is composed of a plurality of switching units Sa, Sb, Sc, Sd, Se, each of which is composed of a switch SW and a 10 kΩ resistor connected in series. Furthermore, each switching unit is connected in parallel with a corresponding resistor in the voltage divider 51. The switch SW illustrated in FIG. 3 is in the open position.

The switching signal (LCD pulse) generated by the signal generator 55 is used to control the opening and closing of the switch SW of the switching circuit 53. When the switching signal LCD pulse is logic 1, the switch SW is closed, thereby effectively reducing the corresponding resistance between two adjacent nodes by about 9.09 kΩ by connecting a 10 kΩ resistor and a 100 kΩ resistor. In this way a larger operating current It is produced. The operating current It flows from the nodes a, b, c, d and e to the LCD driver 40 to operate the LCD driver 40 to generate LCD drive signals COM1-COM 8 and SEG1-SEG40. Let's do it.

While the LCD drive signals COM1-COM 8 and SEG1-SEG40 are not switched, the switching signal (LCD pulse) output from the signal generator 55 is logic 0, which turns off the switch SW of the switching circuit 53. Open it. In this situation, nodes a, b, c, d, e are connected only by 100 kΩ resistors. Therefore, the resistance between two adjacent nodes is 100kΩ. ' When Vcc = 5 when '= 1 and Ve = 0, Id = 5V / 500kΩ = 10μA.

Signal controlling voltage Ve of node e 'Is a logic 0 signal when the LCD is in standby mode, otherwise it is a logic level 1. therefore, ' If '= 0, the inverter 52 converts to logic level 1, and the voltage Ve reaches Vcc. At this time, the current Id does not flow.

Second embodiment

4A-4C, a block diagram showing a second embodiment of the bias voltage generator 50 according to the present invention is shown. In this embodiment, the same elements as those in the first embodiment are given the same reference numerals in terms of structure and function, and repetition of description of such elements will be omitted.

The only difference between the second embodiment and the first embodiment is that the switching circuit 53 is composed of a plurality of transistor switches SW each having an internal resistance R ₁ , as schematically illustrated in FIG. 4C. Each transistor switch is connected in parallel with a corresponding 100 kΩ resistor of voltage divider 51.

In FIG. 4B, a preferred transistor switch SW is a long channel transfer gate comprising an NMOS transistor Q1 having a gate G1 controlled by an LCD pulse and a PMOS transistor Q2 having a gate G2 controlled by an LCD pulse. (54). The source S is connected to Vcc and the drain D is connected to the node a.

When the LCD drive signal should be switched, the signal generator 55 generates a signal with the signal LCD pulse = 1, which turns on both the NMOS transistor Q1 and the PMOS transistor Q2. Since the corresponding low resistance R ₁ is hung on the long channel transfer gate 54, the corresponding resistance between Vcc and node a is less than R ₁ , and the current It increases to drive the LCD driver 40.

In other cases, the signal generator 55 generates a signal with the signal LCD pulse = 0, which makes the current path through the NMOS transistor Q1 and the PMOS transistor Q2 an open circuit. In this situation the corresponding resistance between Vcc and node a is 100kΩ, which lowers the current Id.

Third embodiment

In Fig. 5, a block diagram showing a third embodiment of the bias voltage generator 50 according to the present invention is shown. In this embodiment, the same elements as those in the first embodiment are given the same reference numerals in terms of structure and function, and repetition of description of such elements will be omitted.

The third embodiment differs from the embodiments disclosed above by a plurality of 10 kΩ and 90 kΩ resistor pairs in which the voltage divider 51 is connected in parallel, and a switching circuit 53 having a plurality of corresponding switches connected across a 100 kΩ corresponding resistor ( SW).

When the LCD drive signal should be switched, the signal generator 55 generates a signal with the signal LCD pulse = 1, which causes the switches SW to close. As a result, the 90 kΩ resistors are invalidated and the corresponding resistance between the pair of adjacent nodes is 10 kΩ. This low 10kΩ resistance enables the bias voltage generator 50 to supply a large operating current It to the LCD driver 40 so that the LCD driver 40 operates to generate an LCD drive signal.

In other cases, the signal generator 55 generates a signal with the signal LCD pulse = 0, which disconnects the current path passing therebetween by opening the switches SW. In this situation, the corresponding continuous resistance between each pair of adjacent nodes is 10 kΩ-90 kΩ = 100 kΩ. This high 100kΩ resistance greatly reduces the current Id.

It should be noted that the three embodiments include various types of variable resistors, each of which is switched on and off between a low resistance value and a high resistance value according to a switching signal (LCD pulse).

6 shows waveforms of signals CLK, COM1, COM2, LCD pulses and DYNR used in the bias voltage generator 50 according to the present invention.

The CLK signal is generated by the signal generator 55 at time intervals based on the system clock signal SYSCK. As shown, when the common signals COM1 and COM2 are to be generated by the LCD driver 40, the signal generator 55 generates an LCD pulse, which is a switching signal composed of pulses that are continuously synchronized with the common signal. . As a result, the voltage divider 51 is switched to a low resistance, thereby obtaining a large operating current It.

Furthermore, the voltage divider 51 cooperates with the switching circuit 53 to form a dynamic resistor DYNR. While the signal generator 55 generates the LCD pulse signal, the switches SW of the switching circuit 53 are closed, so that the current path is realized and the high resistance of the voltage divider 51 is reduced in the switching circuit 53. And low-resistance Ra. For example, in the first embodiment Ra = (100 x 10) / (100 + 10) = 9.09 kΩ.

In other cases, the switching circuit 53 is open so that adjacent nodes have a high resistance Rb, for example 100 kΩ, and the current Id is lowered.

The operating method of the first embodiment according to the present invention includes the following steps. That is, generating a switching signal (LCD pulse) and bias voltages Va, Vb, Vc, Vd and Ve at each of the plurality of nodes a, b, c, d, and e in the voltage divider 51. Applying a voltage to the voltage divider 51 so as to set a voltage, where the voltage divider 51 includes a plurality of first resistors 100 kΩ connected in series and each node is located between corresponding pairs of first resistors adjacent to each other. And, opening and closing a plurality of switching units (Sa, Sb, Sc, Sd and Se) connected in series in accordance with the switching signal (LCD pulse)-wherein each switching unit is a switch (SW) and the second resistor ( 10 kΩ) and each switching unit (Sa, Sb, Sc, Sd and Se) is connected in parallel with one of the corresponding first resistors—and the switching units (Sa, Sb, Sc, Sd and Se) are Closing each of the second resistors in parallel with the corresponding first resistor.

The operating method of the second embodiment according to the present invention includes the following steps. That is, the step of generating a switching signal (LCD pulse), and the bias voltage (Va, Vb, Vc, Vd and Ve) to each of a plurality of nodes (a, b, c, d and e) in the voltage divider 51 Applying a voltage to the voltage divider 51 to set, where the voltage divider 51 includes a plurality of voltage divider resistors (100 kΩ) connected in series and each node is located between corresponding pairs of voltage divider resistors adjacent to each other. Opening and closing a plurality of transistor switching units connected in series according to a switching signal (LCD pulse), wherein each transistor switching unit includes a transistor switch (SW) and an internal resistor and each transistor switching unit has a corresponding voltage divider resistor. Connected in parallel with one of the two; and connecting the corresponding voltage divider resistor and the respective internal resistance in parallel when the transistor switch SW is closed.

The operating method of the third embodiment according to the present invention includes the following steps. That is, generating a switching signal (LCD pulse) and applying bias voltages Va, Vb, Vc, Vd, and Ve to each of a plurality of nodes a, b, c, d, and e in the voltage divider 5. Applying a voltage to the voltage divider 51 to set the voltage divider 51, wherein the voltage divider 51 is a pair of a plurality of first resistors (10 kΩ) and a second resistor (90 kΩ) connected in series and each of the first and second resistor pairs. And each node at its distal end; and opening and closing a plurality of switches SW connected in series in accordance with a switching signal (LCD pulse), wherein each switch SW is in parallel with one of the corresponding second resistors. And invalidating the second resistor when the switch is closed.

Fig. 7 shows typical waveforms of the common signals COM1, COM2 and COM3 and the segment signal SEGx used to drive the LCD. The LCD driver 40 is driven by the bias voltages Va, Vb, Vc, Vd and Ve at nodes a, b, c, d and e. According to the present invention, the bias voltage generator can dynamically provide a small corresponding resistance between nodes, thereby minimizing the generation of spikes during the switching of the LCD drive signal. In other cases, bias voltage generation can provide a large corresponding resistance between nodes, thereby lowering the leakage of current through the resistor.

As described above, the present invention has been described as a preferred embodiment. However, the scope of the present invention is not limited to the disclosed embodiments, and is intended to cover similar arrangements as various modifications possible within the scope defined in the appended claims. The scope of the claims should be as broad as possible to encompass all such modifications and similar arrangements.

Claims (30)

A signal generator for generating a switching signal, A voltage divider comprising a plurality of nodes positioned between a plurality of first resistors connected in series and an adjacent first resistor; A switching circuit comprising a plurality of switching units connected in series and each connected to the switching unit in parallel with one of the plurality of first resistors corresponding thereto, The switching circuit is responsive to a switching signal for opening and closing a switch, and a second resistor of each switching unit is connected in parallel with a corresponding first resistor when the switch of each switching unit is closed so that a voltage is applied to the voltage divider. A bias voltage generator for a liquid crystal display driver, characterized in that the bias voltage is generated in the. An apparatus according to claim 1, wherein the second resistor of each switching unit has a lower resistance value than the first resistor corresponding to each switching unit. 2. The liquid crystal display driver as claimed in claim 1, further comprising a liquid crystal display driver, wherein the bias voltage enables the liquid crystal display driver to generate a plurality of liquid crystal display drive signals including a common signal and a plurality of segment signals. Device. The method of claim 1, wherein the plurality of first resistors connected in series form a DC current path, the DC current path when the first end is connected to the voltage source and the second end has the same voltage as the voltage source. And the DC current path is responsive to the standby signal such that there is no voltage difference between the first end and the second end. The apparatus of claim 1, wherein the second resistor in each switching unit is connected in series with the switch. 6. The apparatus of claim 5, further comprising a liquid crystal display driver, wherein the voltage at each node is a bias voltage that enables the liquid crystal display driver to generate a plurality of liquid crystal display drive signals when the switch is closed. Device. 2. The apparatus of claim 1, wherein the switch is closed when the switching signal is logic 1 and the switch is opened when the switching signal is logic 0. A signal generator for generating a switching signal, A voltage divider comprising a plurality of nodes between a plurality of continuously connected voltage divider resistors and an adjacent voltage divider resistor, A plurality of continuously connected transistor switching units, each switching unit being connected in parallel with one of the corresponding plurality of voltage divider resistors, the switching unit being composed of a switching circuit each including a transistor switch and an internal resistor, The switching circuit opens and closes the transistor switch in accordance with a switching signal, and the internal resistance of each switching unit is connected in parallel with a corresponding voltage divider resistor when the transistor switch is ON, so that when a voltage is applied to the voltage divider, a bias voltage at the node is increased. A bias voltage generator for a liquid crystal display driver, characterized in that it is generated. 9. The apparatus of claim 8, wherein the internal resistance of each switching unit has a lower resistance value than the voltage divider resistor corresponding to each switching unit. 10. The liquid crystal display device of claim 8, further comprising a liquid crystal display driver, wherein the bias voltage enables the liquid crystal display driver to generate a plurality of liquid crystal display drive signals, wherein the liquid crystal display drive signal comprises a plurality of common signals and a plurality of common signals. And a segment signal. 9. The method of claim 8, wherein the plurality of continuously connected voltage divider resistors form a DC current path, the DC current path when the first end is connected to the voltage source and the second end has the same voltage as the voltage source. And the DC current path is responsive to the standby signal such that there is no voltage difference between the first end and the second end. 9. The apparatus of claim 8, wherein each transistor switching unit is closed when the switching signal is logic 1 and opens when the switching signal is logic 0. 9. The apparatus of claim 8, wherein each transistor switching unit is a long channel transfer gate. A signal generator for generating a switching signal, A voltage divider comprising a plurality of consecutively connected first and second resistor pairs and respective nodes at one end of the first and second resistor pairs, A switching circuit comprising a plurality of switches connected to be connected in parallel with a corresponding one of the plurality of switches and the second resistor, The switching circuit opens and closes the switch according to a switching signal, and when the switch is closed, the second resistor is invalidated, so that a bias voltage is generated at the node when a voltage is applied to the voltage divider. Device. 15. The apparatus of claim 14, wherein the first resistor of the first and second resistor pairs has a smaller resistance value than the corresponding second resistor of the first and second resistor pairs. 15. The liquid crystal display device of claim 14, further comprising a liquid crystal display driver, wherein the bias voltage enables the liquid crystal display driver to generate a plurality of liquid crystal display drive signals, wherein the liquid crystal display drive signal comprises a plurality of common signals and a plurality of common signals. And a segment signal. 15. The method of claim 14, wherein the plurality of consecutively connected alternate first and second resistors form a direct current current flow path, the direct current current path having a first end connected to a voltage source and a second end connected to a voltage source. And the DC current path is responsive to the standby signal so that there is no voltage difference between the first end and the second end when it has the same voltage. 15. The apparatus of claim 14, wherein each switch is closed when the switching signal is logic 1 and opens when the switching signal is logic 0. A signal generator for generating a switching signal, A voltage divider comprising a plurality of nodes between a plurality of continuously connected voltage divider resistors and an adjacent voltage divider resistor; A plurality of serially connected transistor switching units, each of which is connected in parallel with one of the plurality of voltage divider resistors corresponding to the switching unit, and each of the switching units comprises a switching circuit including a switch and an internal resistance, The switching circuit opens and closes the switch according to a switching signal, and the internal resistance of each switching unit is connected in parallel with a corresponding voltage divider resistor when the switch is closed, so that a bias voltage is generated at a node when voltage is applied to the voltage divider. A bias voltage generator for a liquid crystal display driver. A signal generator for generating a switching signal, A voltage divider comprising a plurality of consecutively connected adjacent variable resistors and a plurality of nodes positioned between adjacent variable resistors, The voltage at each node is a bias voltage, and when the voltage is applied to the voltage divider by adjusting the bias voltage according to a switching signal and raising and lowering the resistance value of the variable resistor to adjust the current through the voltage divider. A bias voltage generator for a liquid crystal display driver, wherein a bias voltage is generated at a node. In the method for generating a bias voltage for a liquid crystal display driver, (a) generating a switching signal; (b) applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, where the voltage divider comprises a plurality of first resistors connected in series, each node having a corresponding first pair of resistors adjacent to each other. Located between-and, (c) opening and closing a plurality of switching units connected in series in accordance with a switching signal, wherein each switching unit comprises a switch and a second resistor and each switching unit is connected in parallel with one of the corresponding first resistors. -Wow, (d) connecting each second resistor in parallel with a corresponding first resistor when the switching unit is closed. 22. The method of claim 21, wherein the first resistor has a greater resistance value than the second resistor. 22. The method of claim 21, wherein step (e) comprises closing each switching unit when the switching signal is logic 1 and opening each switching unit when the switching signal is logic 0. . In the method of generating a bias voltage for a liquid crystal display driver, (a) generating a switching signal; (b) applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, where the voltage divider comprises a plurality of voltage divider resistors connected in series, each node being connected between a pair of adjacent voltage divider resistors adjacent to each other. Is located at (c) opening and closing a plurality of transistor switching units connected in series in accordance with a switching signal, wherein each transistor switching unit comprises a transistor switch and an internal resistor, each transistor switching unit being in parallel with one of the corresponding voltage divider resistors. Connected- (d) connecting the corresponding voltage divider resistor and each internal resistance in parallel when the transistor switch is closed. 25. The method of claim 24, wherein the voltage divider resistor has a resistance value greater than the internal resistance. 25. The method of claim 24, wherein step (e) comprises closing each switching unit when the switching signal is logic 1 and opening each switching unit when the switching signal is logic 0. In the method for generating a bias voltage for a liquid crystal display driver, (a) generating a switching signal; (b) applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, wherein the voltage divider includes a plurality of pairs of first and second resistors connected in series and the first and second resistor pairs. Each node at each end of-and, (c) opening and closing a plurality of switches connected in series in accordance with a switching signal, wherein each switch is connected in parallel with one of the corresponding second resistors; (d) invalidating the corresponding second resistor when the switch is closed. 28. The method of claim 27, wherein the first resistor has a smaller resistance value than the second resistor. 28. The method of claim 27, wherein step (e) comprises closing each switch when the switching signal is logic 1 and opening each switch when the switching signal is logic 0. In the method for generating a bias voltage for a liquid crystal display driver, (a) generating a switching signal; (b) applying a voltage to the voltage divider to set a bias voltage to each of the plurality of nodes in the voltage divider, where the voltage divider comprises a plurality of variable resistors connected in series, each node being connected between a pair of adjacent variable resistors adjacent to each other. Is located at and (c) raising or lowering the resistance value of the variable resistor in accordance with a switching signal for generating a bias voltage for supplying a dynamic current flowing through the voltage divider.