KR19980061494A - Error location detection circuit and error location and size calculation device - Google Patents

Abstract

An error position detection circuit and an error position and size calculation apparatus using a pipeline tree by using a Reed-Solomon code and a Pony algorithm are disclosed. The first error location polynomial processing unit receives N / 2 (where N is an integer equal to or greater than 2) even-numbered error-locator polynomials, receives N / 2 coefficients for outputting the multiplication value, And has two multipliers. The second error location polynomial processing unit has N / 2 multipliers for receiving the coefficients of N / 2 odd-numbered error-locus polynomials and multiplying the stored odd-numbered primitive elements, respectively, to output multiplication values. The selector has N / 2 multiplexers for selectively outputting even-numbered multiplication values from the first error locator polynomial processing unit or odd-numbered multiplication values from the second error locator processing unit. The pipeline adder tree adds the odd-numbered multiplicand values and the even-numbered multiplicand values selected by the selector, respectively. In the pipeline adder tree, the number of adders can be reduced by half to reduce the chip area.

Description

Error location detection circuit and error location and size calculation device

The present invention relates to error location and magnitude computation by detection of a chien. More particularly, the present invention relates to detection of chien using reed-solomon (RS) codes using a pipeline tree, and error location detection circuit and error location and size calculator by pony algorithm.

RS code is a representative example of non-binary BCH code. Although it is possible to use Berlekamp's iterative algorithm to decode the RS code, the difference from the binary BCH code is that the error size at the error location must be calculated.

In the RS code, Chien's detection algorithm is substituted for each α ^-i , 0 ≤ ⁱ ≤ N-1 by the following error locator polynomial [1] to obtain all σ (α ⁱ ), 0 I < / = N < -1 >

[Formula 1]

The first thing to solve is to implement [Equation 1]. There are several ways to implement [Equation 1]. In other words, each term is sequentially computed and accumulated. Since this is performed for all i values, the computation period is long.

[Equation 1] is expressed by [Equation 2].

[Formula 2]

σ (x) = ((( (((σ N-1 x + σ N-2) x + σ N-3) x + σ N-4) x + ...... + α + σ 1) x + σ ₀

Is less than or equal to any error number ((ℓ-k) ⁾ of x = α ⁰ , α ^-1 , α ^-2 , ..., α ^{- (ℓ -1)} .

Where l is the number of encoded symbols.

Transmitted symbol (testis _{v 0, v 1, v 2} , ....... v k-1, parity _{P 0, P 1, P 2} , ....... P ℓ-k-1)

It is assumed that the transmitted symbols are constituted by k number of parity symbols of l-k-1 in the original information.

Chien detection is ^{σ (α 0), σ (} α -i), σ (α -2), σ (α -i) .... σ (α - (ℓ-1)) of the values has the value of 0 Quot; is detected.

If σ (α ^-i ) = 0 then i is an error position and can have up to N error locations.

1 is ^{σ (α 0), σ (} α -i), σ (α -2), ...., σ (α -i) .... σ - the ^{(α (ℓ-1))} 0 1 > for < i < = l-1. Referring to FIG. 1, the conventional error locator circuit includes a multiplier 11, a register 12, and an adder 13. The multiplier 11 multiplies each primitive element of the Galois Field by the additive value added by the adder 13 and provides the multiplication value to the register 12. [ The register 12 stores the multiplication value from the multiplier 11 and outputs it to the adder 13 and the outside. The adder 13 adds each term of the error locator polynomial of the input Galois field to the multiplication value stored in the register and provides the addition value to the multiplier 11.

σ _j (α ^-i) means the j-th, that is, x ⁱ coefficients of σ (α ^-i) when calculating σ (α ^-i) at x = α ^-i. FIG. 1 can implement Chien detection in N cycles when i is 1 to l in the case of performing parallel operation on a number of lines. The disadvantage of this method is that it requires a large number of multipliers and registers as many as the corresponding degree in relation to the degree of the error location polynomial when the value of ℓ is large. That is, in the case of any i = l, Nxl cycle is required.

FIG. 2 is a diagram illustrating a structure of an error locator circuit using a conventional pipeline adder tree in which the problem of FIG. 1 is eliminated.

The error location detection circuit using a conventional pipeline adder tree includes an error location polynomial processing unit 21 and a pipeline adder tree 22. [

An error locator polynomial processor 21 is the N error position polynomial coefficients having the N multipliers (210, 211, ...., 21N -1, 21N-1) (σ 0, σ 1, σ 2, ..., primitive elements are stored under the respective input ^{_{σ N-1) (x 0}} , x, x 2, ....., x N-2, x N-1) and multiplication by each multiplier To the pipeline adder tree (22).

The pipeline adder tree 22 adds the multiplication values from the error location polynomial processing unit 21 to generate an error location polynomial? (X). The error location polynomial σ (s) is given by [3].

[Formula 3]

_{^{σ (α -1) = σ 0}} + σ 1 α -1 + σ 2 (α -1) 2 + σ 3 (α -1) 3 + ........ + σ N-1 (α - ¹ ) ^N-1

_{^{σ (α -2) = σ 0}} + σ 1 α -2 + σ 2 (α -2) 2 + σ 3 (α -2) 3 + ........ + σ N-1 (α - ² ) ^N-1

_{^{σ (α -3) = σ 0}} + σ 1 α -3 + σ 2 (α -3) 2 + σ 3 (α -3) 3 + ........ + σ N-1 (α - ³ ) ^N-1

...

^{σ (α - (ℓ-1} )) = σ 0 + σ 1 α - (ℓ-1) + σ 2 (α - (ℓ-1)) 2 + σ 3 (α - (ℓ-1)) 3 + ........

+? _N-1 (? ^- (? ^{- 1)} ) ^N-1

As can be seen from Equation (3), in the error location detection circuit using the conventional pipeline adder tree, all operations are completed in the l cycle.

3 is a circuit diagram showing the structure of the pipeline adder tree shown in FIG. Pipelined adder tree 22 are input the N individual if the level of the log ₂ N as shown in Figure 3, because the presence of the level of the log ₂ N XOR gates.

4 is a diagram showing a configuration of an error location and size calculation circuit using a conventional Chien and Pony algorithm. The error position and magnitude computing circuit using the conventional Chien and Pony algorithms includes an even-numbered anti-error location polynomial operation circuit 41, an odd anti-error location polynomial operation circuit 42, an adder 43, an error size detection circuit 44, And a divider 45.

The even-numbered error-locator polynomial circuit 41 processes the inputted N / 2 even-numbered error-locator polynomial coefficients and the stored even-numbered non-primitive elements respectively so as to calculate the sum σ (x) = σ ₀ + σ ₂ x ² + ..... + σ _N-4 × ^N-4 + σ _N-2 × ^N-2 and outputs it to the adder 43. The even-numbered-term error-locating circuit 41 comprises N / 2 multipliers 4110, 4112, ..., 411N-4, 411N-2, Error position polynomial processing unit 411 for multiplying the stored even-numbered antinomial elements to generate multiplication values, and an adder 43 for adding the multiplication values from the even- And an even-numbered-term pipeline adder tree 412 for outputting the output.

The odd-numbered error-locator polynomial operation circuit 42 processes the coefficients of N / 2 odd-numbered error-locator polynomials and the stored odd-numbered primitive elements to calculate the sum σ (x) = σ ₁ x + σ ^₃ x ₃ + ..... a ^{_{+ σ N-3 x N-}} 3 + σ N-1 x N-1 and outputs it to the adder 43. The odd-numbered error-locator polynomial operation circuit 42 includes N / 2 multipliers 4211, 4213, .... 421N-3, 42N-1, Numbered error-prime polynomial processing unit 421 to generate multiplication values by multiplying the stored odd-numbered primitive elements by an odd-numbered error-prime polynomial processing unit 421 and adding the multiplied values to the adder 43 And an odd-numbered pipeline adder tree 422 for outputting the odd-numbered pipeline adder tree 422. [

The adder 43 adds the sum of the even term of the error locator polynomial from the even-numbered-term error polynomial arithmetic circuit 41 and the sum of the odd term of the error locator polynomial from the odd-term error locator polynomial arithmetic circuit 42, Generates a position polynomial, and provides the error locator polynomial to the divider 45. [

The error magnitude polynomial arithmetic circuit 44 computes the sum ω (x) of the error magnitude polynomials and provides them to the divider 45. The error magnitude polynomial operation circuit 44 includes N multipliers 4410, 4411, .... 441N-2, and 44N-1, and outputs the N error magnitude polynomial coefficients and the stored primitive enzymes An error magnitude polynomial processing unit 441 for multiplying and generating multiplication values and an error size pipeline adder tree 442 for adding the multiplication values from the error location polynomial processing unit 441 to the divider 45 ).

The divider 45 divides the sum ω (x) of error magnitude polynomials from the error magnitude polynomial processing unit 44 into a differential value of the error position polynomial, that is, an error position from the odd term error position polynomial operation circuit 42 Is divided by the sum of the odd term of the polynomial to generate the error magnitude -ω (x) / sigma '(x). In other words, the algorithm of the detection algorithm of the Chien-zhi position = the sum of the odd terms + the sum of the terms of the odd terms algorithm; Error size = -ω (x) /? '(X)

The error magnitude polynomial ω (x) = ω ₀ + ω ₁ x = ω ₂ x ² + ..... + ω _N-2 x ^N-2 + ω _N-1 x ^N-1

σ x = σ ₀ + σ ₁ x + σ ₂ x ² + σ ₃ x ³ + + σ _N-2 x ^N-2 + σ _N-1 x ^N-1 + σ _N x ^N and, σ '(x) = σ 1 + 2σ 2 x + 3σ 3 x 2 ..... + (N-2) σ N-2 x N-3 + (N-1) σ N-1 x N ^-2 + _N σ _N x ^N-1 , σ '(x) is equal to the sum of the odd term of σ (x).

As described above, in the conventional error location detecting circuit and error location and size calculating circuit, many adders are required in many pipeline adder trees in order to obtain error locator polynomials.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide an error position detection circuit for a chip that reduces the number of adders and reduce the area of a chip, and an error position and magnitude polynomial operation circuit using the same.

1 is a diagram showing a configuration of a conventional error location detecting circuit in Chien.

2 is a diagram showing a configuration of an error location detection circuit using a conventional pipeline adder tree.

3 is a circuit diagram showing the structure of the pipeline adder tree shown in FIG.

4 is a diagram showing a structure of an error location and size calculation circuit using a conventional pipeline adder tree.

FIG. 5 is a diagram illustrating a configuration of an error location detecting circuit of a CHANNEL using a pipeline adder tree according to an embodiment of the present invention. Referring to FIG.

6 is a circuit diagram showing the structure of the pipeline adder tree shown in FIG.

7 is a diagram showing a configuration of an error position and magnitude computing circuit according to an embodiment of the present invention.

Description of the Related Art [0002]

52, 712: selector 53, 713: pipeline adder tree

71: Error position detection circuit 72: Error size detection circuit

73: adder 74: divisor

510, 512, ..., 51N-2: the first error location polynomial processing unit

511, 513, ....., 51N-1: the second error location polynomial processing unit

521, 522, ..., 52 [N-1] / 2, 7121, 7122, ..., 712 [N-1] / 2:

7110, 7112, ...., 711N-2: Even-numbered error-position polynomial processing unit

7111, 7113, ...., 711N-1: odd term error position polynomial processing unit

In order to achieve the above object, the present invention provides a method for generating a multiplicative value by multiplying an N / 2 (where N is an integer of 2 or more) A first error locator polynomial processing unit having N / 2 multipliers; A second error locator polynomial processor having N / 2 multipliers for receiving the coefficients of the N / 2 even-numbered error-locator polynomials and multiplying the stored odd-numbered primitive elements, respectively, to produce multiplication values; A selector having N / 2 multiplexers for selectively outputting even-numbered multiplication values from the first error locator polynomial processing unit or odd-numbered multiplication values from the second error locator polynomial processing unit; And a pipeline adder tree for adding odd-numbered multiplicand values and even-numbered multiplicand values selected by the selector, respectively.

The present invention also deals with the input N / 2 (where N is an integer greater than or equal to 2) even-numbered and odd-numbered error-locus polynomial coefficients and stored even-numbered antinomial elements, respectively, An error location detection circuit for generating an association; An error size detection circuit for processing an input N number of error magnitude polynomial coefficients and stored primitive elements, respectively, to generate an error magnitude polynomial sum; An adder for generating an error locator polynomial by adding the even and odd anti-sum from the error location detection circuit; And a divider for dividing the generated error magnitude polynomial from the error magnitude detection circuit by an odd anti-sum from the odd term error position detection circuit to generate an error magnitude. Device.

In the present invention, the number of adders in the pipeline adder tree can be reduced by half to reduce the chip area.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of an error location detection circuit using a pipeline adder tree according to an embodiment of the present invention. The error location detecting circuit using the pipeline tree includes a first error locator polynomial processor 510, 512, ..., 51N-2, a second error locator polynomial processor 511, 513, ....., 51N- 1), a selector 52, and a pipeline adder tree 53.

The first error locator polynomial processing unit 510, 512, ..., 51N-2 receives the coefficients of N / 2 even-numbered error-locator polynomials respectively and multiplies each of the stored even- And N / 2 multipliers for outputting the value.

The second error location polynomial processing unit 511, 513, ..., 51N-1 receives the coefficients of N / 2 odd-numbered error-locus polynomials and multiplies the stored odd-numbered primitive elements, respectively, And outputs N / 2 multipliers. Each multiplier (510, 511, ...., 51N -2, 51N-1) is the result multiplied by the coefficient input receives the 0≤i≤N-1 σ _i (α ^{-i) j} own the calculated To calculate the agreement result. (α ^{-i) j,} is for calculating the term σ _j σ _j (α ^{-i) j} for x = α ^-i.

The selector 52 selects either the even-numbered multiplicand from the first error locator polynomial processor 510, 512, ...., 51N-2 or the second error locator polynomial processor 511, 513, ....., , 52 [N-1] / 2) for selectively outputting the odd-numbered multiplicative values from the multipliers 521, 51N-1.

The pipeline adder tree 53 adds odd-numbered multiplicand values and even-numbered multiplicand values selected by the selector 52, respectively. 6 is a circuit diagram showing the structure of the pipeline adder tree shown in FIG. Pipelined adder tree 52 is entered, that is, it is an odd number, wherein the multiplication value or an even number, wherein the multiplication teeth selected by the selector N individual if the level of the log ₂ N as shown in Figure 6 exists in the level of the log ₂ N by Instead of XOR gates It uses an XOR gate and performs an efficient pony algorithm.

Hereinafter, an error position and magnitude computing apparatus according to an embodiment of the present invention will be described in detail. 7 shows the configuration of an error position and magnitude computing circuit according to an embodiment of the present invention. The error location and magnitude computing device according to the present invention includes an error location detection circuit 71, an error size detection circuit 72, an adder 73, and a divider 74.

The error position detection circuit 71 processes the input N / 2 even-numbered and odd-numbered error-locus polynomial coefficients and the stored even-numbered non-primitive elements, respectively, to generate even-numbered and odd-numbered And provides it to the adder 73.

The error position detection circuit 71 receives the coefficients of the N / 2 even-numbered error-locator polynomials, receives the even-numbered anti-error elements having N / 2 multipliers for outputting the multiplied values, Number polynomial processing units 7110, 712, ..., 711N-2, and N / 2 odd-numbered error-locus-based coefficients, respectively, and outputs the multiplied values Numbered polynomial processing units 7111, 7113, ..., 711N-1 having N / 2 multipliers, and odd-numbered anti-error polynomial processing units 7110, 7112, ..., 711N-2 N / 2 multiplexers 7121, 7122,... 7123 for selectively outputting even-numbered multiplicand values or odd-numbered multiplicative values from the odd-numbered error polynomial processing units 7111, 7113, ....., 711N-1. ..., 712 [N-1] / 2), a selector 712 having an odd-numbered product And a pipeline adder tree 713 for adding the sum values and the even-numbered multiplication values, respectively.

Pipelined adder tree 713 is input, that is, it is an odd number, wherein the multiplication value or an even number, wherein the multiplication teeth selected by the selector is the level of the log ₂ N as shown in FIG. 6, if N individual the presence of a conventional log ₂ N By level Instead of XOR gates It uses an XOR gate and performs an efficient pony algorithm.

The error size detection circuit 72 processes the input N number of error magnitude polynomial coefficients and the stored primitive elements, respectively, to generate an error magnitude polynomial sum and provides it to the adder 73. [ The error size detection circuit 72 receives the coefficients of the N / 2 even-numbered error-locator polynomials, receives the even-numbered anti-error elements having N / 2 multipliers for outputting the multiplied values, N polynomial processing units 7210, 7212, ..., and 721N-2 for multiplying the odd anti-primitive elements received from the N / 2 odd-numbered error locator polynomial coefficients, respectively, / 2 odd-numbered error-magnitude polynomial processing units 7211, 7213, ....., 721N-1 having two multipliers, and even-numbered term error magnitude polynomial processing units 7210, 7212, ...., 721N-2 N / 2 multiplexers 7221, 7222, ..., 7222 for selectively outputting odd-numbered multiplicand values of odd-numbered error magnitude polynomial processing units 7211, 7213, ....., 721N- ..., 722 [N-1] / 2), a selector 722 having an odd-numbered And a pipelined adder tree 723 for respectively adding the count teeth and the even teeth, wherein multiplication.

The adder 73 adds an even-numbered sum and an odd-numbered sum from the error-position detecting circuit 71 to generate an error-locator polynomial.

The divider 74 divides the generated error magnitude polynomial from the error magnitude detection circuit 72 by an odd anti-sum from the error position detection circuit 71 to generate an error magnitude.

The error position and magnitude computing apparatus according to the present invention preliminarily stores one of the even and odd anti-sum of the error locator polynomial generated by the error position detection circuit 71 and calculates a sum of the terms calculated in the next cycle And additionally has a register 75 for finally finding an error location polynomial.

In the error position and magnitude computing apparatus according to the present invention, the calculation of the even and odd term in [Equation 2] is simultaneously performed in parallel (the cycle of computing one cycle and calculating σ (α ^-i ) is one cycle) The result of the even-numbered term is passed to the pipeline adder tree and the result of the odd term is passed to the pipeline adder tree in the next cycle. The reason for this is to reduce the number of adders in the pipeline adder tree by half and to perform an efficient pony algorithm.

As described above, according to the present invention, the number of adders in the pipeline adder tree can be reduced by half to reduce the chip area.

Although the present invention has been described in detail by way of the above embodiments, the present invention is not limited thereto, but can be modified or improved within the ordinary knowledge of those skilled in the art.

Claims (7)

(N / 2) multipliers for outputting a multiplication value by multiplying each of the even-numbered antinomial elements stored in the memory with N / 2 (where N is an integer of 2 or more) An error locator polynomial processing unit 510, 512, ...., 51N-1; A second error locator polynomial processor 511, 513, and N / 2 multipliers for multiplying N / 2 odd anti-error locator polynomial coefficients with the stored odd anti-primitive elements, respectively, ..., 51N-1); ..., 51N-1) from the first error location polynomial processing unit (510, 512, ..., 51N / 2) or from the second error location polynomial processing unit (511, 513, A selector 52 having N / 2 multiplexers 521, 522, ..., and 52 [N-1] / 2 for selectively outputting odd-numbered multiplicand values of the multiplexer 52; And And a pipeline adder tree (53) for adding odd-numbered multiplicand values and even-numbered multiplicand values selected by said selector (52), respectively. 3. The apparatus of claim 1, wherein the pipeline adder tree (53) comprises at least one exposive orgate (60) for alternately adding even-numbered multiplicand and odd-integer multiplicand values selected by the selecting means Wherein the error location detection circuit comprises: 3. The method of claim 2, wherein the exglueus gate (60) comprises an odd-numbered multiplier value or an even-numbered multiplier value selected by the selector if N (where N is an integer of 2 or more) ≪ / _RTI > and a log ₂ N level is present. And processing the even and odd anti-error polynomial coefficients and stored even-numbered non-primitive elements, respectively, of input N / 2 (where N is an integer equal to or greater than 2) An error position detection circuit (71) An error size detection circuit (72) for processing an input N error magnitude polynomial coefficients and stored primitive elements, respectively, to generate an error magnitude polynomial sum; An adder (73) for adding an addend sum and an odd addend from the error position detection circuit (71) to generate an error locator polynomial; And And a divider (74) for dividing the generated error magnitude polynomial from the error magnitude detection circuit (72) by an odd anti-sum from the error location detection circuit to generate an error magnitude And size computing device. 5. The apparatus according to claim 4, wherein the error position detection circuit (71) comprises N / 2 odd-numbered error-locator polynomials for receiving the coefficients of the odd-numbered error-locator polynomials and multiplying the odd- Numbered anti-error location polynomial processing units 7110, 7112, ..., 711N-2 having multipliers, multiplication of N / 2 odd anti-error location polynomial coefficients with respective stored odd anti-primitive elements, respectively Numbered polynomial processing units 7111, 7113, ....., 711N-1 having N / 2 multipliers for outputting multiplication values, the first error locator polynomial processing units 7110, 7112, ..., 711N-2) or the second error-locus polynomial processing unit 7111, 7113, ....., 711N-1 A selector 712 having N / 2 multiplexers 7121, 7122, ..., 712 [N-1] / 2 for selectively outputting odd-numbered multiplicand values of the odd- And a pipeline adder tree (713) for adding the multiplication values and the even-numbered multiplication values, respectively. 5. The apparatus of claim 4, wherein the error position detection circuit (72) comprises N / 2 < th > error correction circuits for inputting the coefficients of N / 2 even-numbered error-locus polynomials respectively and for multiplying the stored anti- A first error magnitude polynomial processing unit (7210, 7212, ..., 721N-2) having a multiplier, multiplies the odd anti-primitive elements received and stored in the coefficients of N / 2 odd- A second error magnitude polynomial processing unit 7211, 7213, ....., 721N-1 having N / 2 multipliers for outputting a multiplication value, a first error magnitude polynomial processing unit 7210, 7212, ..., , 721N-2, or odd-numbered multiplicative values from the second error magnitude polynomial processing unit 7211, 7213, ..., 721N-1, A selector 722 having multiplexers 7221, 7222, ..., 722 [N-1] / 2, And a pipeline adder tree (723) for adding the multiplication values and the even-numbered multiplication values, respectively. 5. The apparatus according to claim 4, characterized by further comprising a register (75) for preliminarily storing an item among the even and odd anti-sum of the error locator polynomial generated by the error position detection circuit (71) Error location and size computing device.