KR19980060614A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19980060614A KR19980060614A KR1019960079976A KR19960079976A KR19980060614A KR 19980060614 A KR19980060614 A KR 19980060614A KR 1019960079976 A KR1019960079976 A KR 1019960079976A KR 19960079976 A KR19960079976 A KR 19960079976A KR 19980060614 A KR19980060614 A KR 19980060614A
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 저장전극 상부에 RTN층과 Ta2O5막 및 TiN막을 순차적으로 적층되게 형성한 다음, 클로린 계통의 가스로 식각하여 표면적이 증가된 캐패시터를 형성함으로써 소자동작에 필요한 충분한 정전용량을 확보하여 반도체 소자의 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, by sequentially forming an RTN layer, a Ta 2 O 5 film, and a TiN film stacked on top of a storage electrode, and then etching the gas with a chlorine-based gas to form a capacitor having an increased surface area. The present invention relates to a technology capable of improving the reliability of semiconductor devices by securing sufficient capacitance required for device operation.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 Ta2O5막으로 이루어진 유전체막 상하부에 각각 TiN막과 질화막을 형성하여 클로린 계통의 가스를 이용하여 식각함으로써 소자동작에 필요한 충분한 정전용량을 확보하여 반도체 소자의 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a TiN film and a nitride film are formed on top and bottom of a dielectric film made of Ta 2 O 5 film to etch using a chlorine-based gas, thereby providing sufficient electrostatic power required for device operation. The present invention relates to a technology for securing a capacity and improving reliability of a semiconductor device.
일반적으로, 반도체 소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다. 특히, 단위셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서 면적을 줄이는 것이 디램소자의 고집적화에 중요한 요인이 된다.In general, with the trend toward higher integration of semiconductor devices, the cell size is reduced, making it difficult to form capacitors with sufficient capacitance. In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, reducing the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, is an important factor for high integration of the DRAM device.
그리하여, 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나 유전체막의 두께를 얇게 하거나 또는 캐패시터의 표면적을 증가시키는 등의 방법을 사용하였다.Therefore, in order to increase the capacitance of the capacitor, a method of using a material having a high dielectric constant as the dielectric film, reducing the thickness of the dielectric film, or increasing the surface area of the capacitor is used.
그러나, 이러한 방법들은 각각의 문제점을 가지고 있다. 즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2또는 SrTiO3등의 신뢰도 및 박막 특성이 확실하게 확인되지 않아 실제 소자에 적용하기에는 어렵다.However, these methods have their respective problems. That is, the reliability and thin film characteristics of a dielectric material having a high dielectric constant, such as Ta 2 O 5 , TiO 2, or SrTiO 3 , are not reliably confirmed, and thus are difficult to apply to an actual device.
또한, 초고집적 소자에서는 저장전극의 구조를 복합하게 함으로써 표면적을 확보하는 방법으로는 소자동작에 필요한 정전용량을 확보할 수 없으며, 유전체막 두께를 감소시키는 것은 소자 동작시 유전체막이 파괴되어 캐피시터의 신뢰도에 심각한 영향을 주는 문제점이 있다.In addition, in the highly integrated device, the capacitance of the device cannot be secured by the method of securing the surface area by composing the structure of the storage electrode, and reducing the thickness of the dielectric film causes the dielectric film to be destroyed during the device operation, thereby reducing the reliability of the capacitor. There is a problem that seriously affects.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 저장전극 상부에 질화막산화막과 Ta2O5막 및 TiN막을 순차적으로 적층되게 형성한 다음, 클로린 계통의 가스로 식각하여 표면적이 증가된 캐패시터를 형성함으로써 소자동작에 필요한 충분한 정전용량을 확보하여 반도체 소자의 신뢰성을 향상시키는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems to form a nitride oxide film, a Ta 2 O 5 film and a TiN film sequentially stacked on the storage electrode, and then etched with chlorine-based gas to form a capacitor with an increased surface area Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device which secures sufficient capacitance required for device operation to improve the reliability of the semiconductor device.
도 1는 본 발명에 따른 반도체 소자의 제조공정도이다.1 is a manufacturing process diagram of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10:저장전극 20:질화산화막10: storage electrode 20: nitride oxide film
30:Ta2O5막 40:TiN막30: Ta 2 O 5 film 40: TiN film
50:다결정 실리콘막50: polycrystalline silicon film
상기 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 제조방법은,In order to achieve the above object, a semiconductor device manufacturing method according to the present invention,
반도체 소자의 제조방법에 있어서,In the manufacturing method of a semiconductor device,
저장전극의 상부에 유전체막으로서 형성되는 질화산화막과, Ta2O5막 및 확산 방지막인 TiN막의 식각 공정을 염소계열 가스로 실시하는 것을 특정으로 한다.The etching process of the nitride oxide film formed as a dielectric film on the storage electrode and the TiN film, which is a Ta 2 O 5 film and a diffusion barrier film, is performed using a chlorine series gas.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1는 본 발명에 따른 반도체 소자의 제조공정 단면도이다.1 is a cross-sectional view of a manufacturing process of a semiconductor device according to the present invention.
먼저, 유전체막 하부에 저장전극(10)을 표면적이 증가된 준안정 다결정 실리콘막(metastable poly silicon 이하, MPS)으로 형성한 다음, 전표면을 급속 열처리 공정에 의한 질화공정(Rapid Thermal Nitridation 이하, RTN)으로 질화산화막(20)을 형성한다.First, the storage electrode 10 is formed below the dielectric film with a metastable polysilicon film (MPS) having an increased surface area, and then the entire surface is subjected to a rapid thermal nitriding process (Rapid Thermal Nitridation). The nitride oxide film 20 is formed of RTN.
다음, 상기 질화산화막(20) 상부에 유전체막으로 Ta2O5막(30)을 형성하고, 확산 방지막으로 TiN막(40)을 형성한 다음, 플레이트전극으로 다결정 실리콘막(50)을 순차적으로 형성한다.Next, a Ta 2 O 5 film 30 is formed as a dielectric film on the nitride oxide film 20, a TiN film 40 is formed as a diffusion barrier, and the polycrystalline silicon film 50 is sequentially formed as a plate electrode. Form.
그 다음, 상기 다결정 실리콘막(50)을 그 하부의 TiN막(40)과의 선택비가 높은 Cl2/O3혼합가스를 사용하여 식각하고, 상기 TiN막(40)과 Ta2O5막(30) 및 질화산화막(20)을 클로린 가스의 계열인 Cl2가스 또는 BCl3가스를 사용하여 순차적으로 식각하여 다결정 실리콘막(50)패턴과 TiN막(40) 패턴, Ta2O5막(30)패턴 및 질화산화막(20)패턴을 형성함으로써 소자동작에 필요로 하는 충분한 정전용량을 확보할 수 있는 반도체 소자의 제조공정을 완료한다(도 1 참조).Then, the polycrystalline silicon film 50 is etched using a Cl 2 / O 3 mixed gas having a high selectivity with the TiN film 40 below, and the TiN film 40 and the Ta 2 O 5 film ( 30) and the nitride oxide film 20 are sequentially etched using Cl 2 gas or BCl 3 gas, which is a chlorine gas series, to form a polycrystalline silicon film 50, a TiN film 40, and a Ta 2 O 5 film (30). By forming the pattern and the nitride oxide film 20 pattern, a semiconductor device manufacturing process capable of securing sufficient capacitance required for device operation is completed (see FIG. 1).
여기서, 상기 다결정 실리콘막(50)과 TiN 막(40), Ta2O5막(30) 및 질화산화막(20)의 식각 조건 범위는 1000w 이상의 소스전원, 10mT 이하의 저압에서 실시한다.Here, the etching conditions of the polycrystalline silicon film 50, the TiN film 40, the Ta 2 O 5 film 30, and the nitride oxide film 20 are performed at a source power of 1000 w or more and a low pressure of 10 mT or less.
상기한 바와 같이 본 발명에 따른 반도체 소자의 제조방법은 초고집적화에 따른 반도체 소자의 제조시 표면적을 최소화하면서 소자동작에 필요로 충분한 정전용량을 확보할 수 있으므로 반도체 소자의 신뢰성을 향상시키는 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention has the effect of improving the reliability of the semiconductor device since it is possible to secure sufficient capacitance necessary for device operation while minimizing the surface area during manufacturing of the semiconductor device due to ultra high integration. .
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960079976A KR19980060614A (en) | 1996-12-31 | 1996-12-31 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960079976A KR19980060614A (en) | 1996-12-31 | 1996-12-31 | Manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19980060614A true KR19980060614A (en) | 1998-10-07 |
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| KR1019960079976A KR19980060614A (en) | 1996-12-31 | 1996-12-31 | Manufacturing method of semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950001927A (en) * | 1993-06-30 | 1995-01-04 | 김광호 | Dry etching method of PZT thin film |
| KR960005829A (en) * | 1994-07-27 | 1996-02-23 | 쯔지 하루오 | Etching Method of Ferroelectric Film |
| EP0725430A2 (en) * | 1995-02-03 | 1996-08-07 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device having capacitor |
| KR970054070A (en) * | 1995-12-27 | 1997-07-31 | 김광호 | How to Form Capacitors in Semiconductor Devices |
-
1996
- 1996-12-31 KR KR1019960079976A patent/KR19980060614A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950001927A (en) * | 1993-06-30 | 1995-01-04 | 김광호 | Dry etching method of PZT thin film |
| KR960005829A (en) * | 1994-07-27 | 1996-02-23 | 쯔지 하루오 | Etching Method of Ferroelectric Film |
| EP0725430A2 (en) * | 1995-02-03 | 1996-08-07 | Matsushita Electronics Corporation | Method of manufacturing semiconductor device having capacitor |
| KR970054070A (en) * | 1995-12-27 | 1997-07-31 | 김광호 | How to Form Capacitors in Semiconductor Devices |
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