KR19980059213A - Digital Dead Time Generator of Inverter for Motor Control - Google Patents

Abstract

The present invention relates to a digital dead time generator of an inverter for controlling an electric motor, which is capable of accurately and easily generating a dead time necessary for preventing a short circuit of the switching element constituting the inverter drive unit by a simple configuration.

A digital dead time generator of an inverter for controlling a motor of the present invention includes a plurality of transistors and a motor control device for gating respective phase windings of an electric motor, wherein the gating signal for each phase winding is delayed by a predetermined period of an input clock. A delay circuit, an AND gate for ANDing the gating signal for each phase winding delayed by the delay circuit with the original gating signal, and a NOR for the gating signal for each phase winding delayed by the delay circuit with the original gating signal and the NOR. A NOR gate for calculating is provided.

Description

Digital Dead Time Generator of Inverter for Motor Control

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital dead time generator of an inverter for controlling a motor, and in particular, a digital of an inverter for controlling a motor that can accurately and easily generate a dead time necessary for preventing a short circuit of a switching element constituting the inverter driving unit by a simple configuration. It is about a dead time generator.

1 is a circuit configuration diagram of a general AC servomotor driver.

As shown in FIG. 1, the driving unit 1 of the conventional general AC servomotor is connected to each of the connection points U, V, and W of six switching transistors Tr1 to Tr6 connected in pairs. Each phase winding line of the electric motor 2 is connected, and the drive part which has such a structure is called an inverter drive part.

On the other hand, in order to prevent the short circuit of each switching transistor in driving the motor by such an inverter driving unit, a predetermined time delay between ending the energization of one phase winding line and energizing the other phase winding line (hereinafter such Delay time is called dead time).

Conventional dead time generating circuits include analog methods using resistors and capacitors and digital methods using counters.Because the dead time is changed by RC time constants, analog methods using resistors and capacitors are difficult to generate accurate dead time. The dead time generating circuit using the counter has a problem that the circuit configuration is complicated.

DISCLOSURE OF THE INVENTION The present invention has been made to solve the above-described problems, and the digital dead time of the inverter for controlling a motor can accurately and easily generate the dead time required to prevent a short circuit of the switching element constituting the inverter driving unit by a simple configuration. The purpose is to provide a generator.

1 is a circuit diagram of a typical AC servo motor driver;

2 is a schematic block diagram of a servo system of a robot controller to which the present invention is applied;

3 is a block diagram showing a detailed configuration of a dead time generating unit in FIG.

4 is a detailed circuit diagram of a delay circuit in FIG. 3;

5 is an output waveform diagram of the main part in FIG.

* Explanation of symbols for main parts of the drawings

1: servo drive, 2: electric motor,

10: main PC, 20: servo control unit,

30: dead time generator, 31, 34, 37: delay circuit,

32, 35, 38: AND gate, 33, 36, 39: NOR gate,

311-314: D flip-flop, 315: AND gate,

316: NOR gate,

317: J-K flip flop

The digital dead time generator of the motor control inverter of the present invention for achieving the above object is a motor control device having a plurality of transistors to gate each of the winding wires of the motor, and inputs a gating signal for each of the winding rights. A delay circuit for delaying by a predetermined period of a clock, an AND gate for ANDing the gating signal for each phase winding delayed by the delay circuit with the original gating signal, and a gating signal for each phase winding delayed by the delay circuit It characterized in that it has a NOR gate for performing a NOR operation with the original gating signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a schematic block diagram of a servo system of a robot controller to which the present invention is applied. As shown in FIG. 2, the servo system of the robot controller to which the present invention is applied includes a main PC (Personal) that performs functions such as performing various operations for position control of the robot and giving various commands and handling various errors. Servo controller 20, which is equipped with a position control algorithm, performs an absolute value and an incremental encoder interface and performs various data communication between the system synchronization and the main PC 10, A servo driver 40 which controls the rotational speed and current of the motor 50, detects various errors to protect the robot system, and supplies electric power to the motor 50 in response to a speed command from the servo controller 20, It consists of an encoder 60 that detects the rotational speed and position of the motor 50 and the motor 50 and provides the encoder feedback signal E / F to the servo controller 20. In the above configuration, the servo controller 20 also includes a dead time generator 30.

FIG. 3 is a block diagram illustrating a detailed configuration of the dead time generator in FIG. 2. In the case of driving a motor by supplying three-phase power to an inverter driver, a PWM signal including dead time is output by receiving a three-phase PWM gating signal. It is a circuit. More specifically, as shown in FIG. 3, the dead time generator 30 includes delay circuits 31; 34; 37 and end gates 32 for the respective windings U; V; and W; 35 and 38 and NOR gates 33 and 36 and 39 are provided, and a respective gating signal and a clock signal CLK are applied to each of the delay circuits 31 and 34 and 37.

And, each of the AND gates 32; 35; 38 and the NOR gates 33; 36; 39, respectively, may have its own original non-delayed gating signal and a gating signal delayed by the delay circuits 31; 34; 37. The logic is processed to provide the gate terminal of the corresponding switching transistor.

The dead time generated by the dead time generator 30 is necessary to prevent a short circuit of the power switching elements (Tr1-Tr6 in FIG. 1) during inverter gating, and the delay circuits 31; 34; 37 and the AND gate 32 35; 38) and the NOR gates 33; 36; 39 are combined to output a PWM signal containing dead time.

FIG. 4 is a detailed circuit diagram of the delay circuit in FIG. 3. As shown in Fig. 4, each of the delay circuits 31; 34; 37 has a plurality of cascaded connections (the number can be changed by the delayed time).

For example, two AND gates 315 logically multiplying the outputs of four D-flip-flops 311-314 and the respective outputs of the cascaded D-flip-flops 311-314 as positive and negative logic inputs. , 316 and one JK flip flop 317 whose outputs of the respective AND gates 315 and 316 are J and K inputs thereof.

Hereinafter, the operation of the digital dead time generator of the motor control inverter of the present invention having the above-described configuration will be described in detail.

First, in order to perform inverter gating, the servo controller 20 generates signals U, V, and W corresponding to three phases, and these three signals U, V, and ( W) corresponds to the U-phase gate signal, the V-phase gate signal, and the W-phase gate signal shown in FIG. 3, respectively.

The delay circuits 31; 34; 37 delay the gate signal of each phase by the length of the dead time in order to generate the dead time.

As a result, the delay circuit sections 31; 34; 37, which determine the length of the dead time, have a time t _d corresponding to a magnitude during a predetermined period of the delay circuit input clock CLK, for example, four periods. Will be delayed.

FIG. 5 is an output waveform diagram of the main part of FIG. 3, and these waveforms show one phase among three-phase gate signals U, V, and W output from the servo controller 20 as an example.

First, waveform b at point b is a reference clock, where Ts represents a sampling period and t _d represents a dead time delayed.

Waveform a at point a is a gating command signal for each phase.

In the waveform (a), the high level state is information for gating the upper switching elements (ie, Tr1, Tr3, Tr5 in Fig. 1) of the U phase, V phase, and W phase, and the low level states are U phase, V phase, and W. Information to gate the lower partial switching element (ie, Tr2, Tr4, Tr6 in FIG. 1) on the top.

Next, the waveform b at point c has a form in which the waveform a at point a is delayed by four periods t _d of the reference clock, that is, the waveform ㅁ at point b.

The waveform c at point d is a gating signal carrying the dead time thus obtained.

As a result, the high level state of the waveform (c) turns on the upper switching elements (Tr1, Tr3, Tr5 in Fig. 1) of the U phase, the V phase, and the W phase, and the low level states of the U phase, the V phase, and the W phase. The upper partial switching elements (Tr1, Tr3, Tr5 in FIG. 1) are turned off.

The waveform at point e is also a gating signal with dead time.

In this waveform (d), the high level state turns on the lower switching elements (Tr2, Tr4, Tr6 in Fig. 1) of the U phase, V phase, and W phase, and the low level states are below the U phase, V phase, and W phase. The partial switching elements (ie, Tr2, Tr4, Tr6 in FIG. 1) are turned off.

The digital dead time generator of the motor control inverter of the present invention is not limited to the above-described embodiments, and can be modified in various ways within the scope of the technical idea of the present invention.

According to the digital dead time generator of the motor control inverter of the present invention as described above, the dead time can be accurately and easily generated with only one delay circuit, an end gate, and a nor gate for each phase of the motor. There is.

Claims (1)

An electric motor control apparatus including a plurality of transistors to gate each phase winding line of an electric motor, comprising: a delay circuit for delaying a gating signal for each phase winding by a predetermined period of an input clock, and each phase winding delayed by the delay circuit; And an AND gate for ANDing the gating signal for the line with the original gating signal, and a NOR gate for NORing the gating signal for each phase winding delayed by the delay circuit with the original gating signal. Digital dead time generator of the control inverter.