KR19980058430A - TFT-LCD Gate Line Delay Compensation Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate line compensation device of a TFT-LCD capable of compensating a gate line delay by adjusting an output enable (OE) signal, and a control signal for preventing overlapping and delay of a gate output voltage. A control unit for generating a; A counting unit for counting and outputting a predetermined number of counts according to the output enable time of the gate line voltage; When the user sets the output enable time of the gate line voltage through the mode setting input terminal, an output enable setting for outputting the gate line voltage according to the set output enable time if the comparison is made with the count number input from the counting unit. Contains wealth.

Description

TFT-LCD Gate Line Delay Compensation Device

The present invention relates to a gate line delay compensation device of a TFT-LCD, and more particularly, to a gate line compensation device of a TFT-LCD capable of compensating a gate line delay by adjusting an output enable (OE) signal.

In general, TFTs control electric current flowing through a thin film semiconductor by applying an electric field perpendicular thereto, and are an active element for thin film integrated circuits as a kind of electric field effect transistor.

Such a TFT is one of the flat panel displays (FPDs) that are recently emerging as next-generation liquid crystal displays.

Referring to Figs. 1, 2, 3 and 4, the gate driving of the conventional TFT-LCD will be described.

The TFT-LCD shown in FIG. 1 has a plurality of memory cells M formed at the intersection of the gate lines of G1 to G600 and the data lines of D1 to D2400.

FIG. 2 is an equivalent circuit of the unit memory cell of FIG. 1, which stores and reads data.

Referring to FIG. 2, the unit memory cell M is composed of a transistor NMT, a liquid crystal C1, and a storage capacitor C2, and is driven by a power applied to the gate line G, thereby driving the data line D. The applied data is applied to the liquid crystal C1 so that the TFT displays an image. The liquid crystal C1 and the storage capacitor C2 supply the common power supply Vcom to shorten the charging speed of the liquid crystal C1 and the storage capacitor C2.

FIG. 3 illustrates characteristics of an ideal voltage applied to the gate line when sequentially driving the gate lines of G1 to G600 to drive the memory cells of the TFT-LCD shown in FIG.

FIG. 4 illustrates the voltage characteristics actually applied to the gate lines of G1 to G600 when driving the memory cells of the TFT-LCD of FIG. 1 as in FIG. 3. Due to the internal resistance of the gate line and the capacitor component, the voltage applied to the gate line substantially overlaps as shown in part (a) of FIG. 4, resulting in data malfunction. Accordingly, in order to prevent such overlapping portions, a control signal for supplying power to the gate lines is prevented from being overlapped by generating a control signal for preventing the voltage from being applied to the gate lines as long as the section (a).

However, in the case of controlling the application of power to the gate line by using the control unit in the conventional TFT-LCD as described above, the resistance and capacitor values of the gate line vary according to the material and process of forming the TFT, thereby preventing malfunction of data. There was a problem that could not be properly prevented.

Accordingly, the present invention has been made to solve such a problem, and by controlling the output enable time, regardless of the change in the resistance and capacitor value of the gate line, the gate voltage is properly prevented from overlapping, and also the delay of the gate line is prevented. It is an object of the present invention to provide a gate line delay compensation device of a TFT-LCD that can be prevented.

1 illustrates an arrangement of memory cells of a TFT-LCD.

2 is an equivalent circuit diagram of a unit memory cell of FIG. 1.

3 is a characteristic diagram of an ideal gate line voltage applied to memory cells of a TFT-LCD.

4 is a characteristic diagram of a substantial gate line voltage applied to memory cells of a conventional TFT-LCD.

Fig. 5 is a block diagram of a gate line delay compensation device of the TFT-LCD of the present invention.

6 and 7 are characteristic diagrams of gate line voltages of the TFT-LCD of the present invention;

* Explanation of symbols for the main parts of the drawings

10: control unit, 12: count unit, 12: output enable setting unit

The gate line delay compensation device of the TFT-LCD of the present invention for achieving the above object includes a control unit for generating a control signal for preventing the overlap and delay of the gate output voltage; A counting unit mounted to the control unit and counting and outputting a predetermined number of counts according to the output enable time of the gate line voltage; The controller is mounted on the control unit, and when the user sets the output enable time of the gate line voltage through the mode setting input terminal, the gate line voltage is output according to the set output enable time if it is compared with the count number input from the count unit. It characterized in that it comprises an output enable setting unit for.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 5, 6, 7 and 8.

Referring to FIG. 5, the gate line delay compensation device 10 of the TFT-LCD of the present invention controls the generation of a control signal for preventing distortion and delay of the gate voltage, and counts the clock signal CLK to gate line. A count unit 11 for counting and outputting a predetermined number of counts according to the output enable time of the voltage; and if the output enable time of the gate line voltage is set through the mode setting input terminal, If it compares with each other, it includes an output enable setting unit 12 for outputting the gate line voltage according to the set output enable time.

If 000 is set via the mode setting input terminals w4 to w6, the output enable setting unit 12 is 2.4 if the output enable setting unit 12 is equal to the number of counts input from the counting unit 11. It is output as the output enable signal Toe of ㎲.

The output enable signal Toe according to the output enable time setting mode of the output enable setting unit of the gate line delay preventing apparatus of the TFT-LCD of the present invention is exemplarily shown in Table 1 below.

TABLE 1

In Table 1, w4, w5 and w6 are the mode setting input terminals of the output enable setting unit 12 for the user to set the mode of the output enable time Toe.

6 illustrates output characteristics of the gate line voltage according to the output enable signal of the gate line delay compensation device of the TFT-LCD of the present invention.

Referring to FIG. 6, in the TFT-LCD gate line delay compensation device of the present invention, the first gate line G1 is output during the output enable time Toe set by the output enable setting unit 12 in the first horizontal period 1H. Is output after the Toe time has elapsed and the voltage of the second gate line G2 is passed after the Toe time has elapsed after the voltage of the first gate line G2 is output in the second horizontal period 2H. To output. As such, the voltage of the gate lines G1 to Gn is sequentially output without overlap due to distortion by preventing the output of the next gate line during the Toe time output from the output enable setting unit 12.

That is, the gate line voltage is not output in the section Toe in which the low signal is output from the output enable setting unit 12, thereby preventing the output voltage of the gate line from overlapping as shown in FIG. 4.

As described above, the present invention prevents the output voltage of the gate line from being delayed by selectively adjusting the Toe section through the output enable setting unit 12 regardless of the process variable.

7 is an output characteristic diagram when the gate line delay compensation device of the TFT-LCD of the present invention is applied to the common power supply Vcom and data Vsig, and not only the gate line voltage but also the common power supply Vcom and data. Vsig may also be controlled by the Toe time output from the output enable setting unit 12 to prevent overlapping with each other as described above.

In the embodiment of the present invention, by increasing the mode setting input terminals w4 to w6, a wider range of Toe time can be finely adjusted.

As described above, the gate line delay prevention apparatus of the TFT-LCD of the present invention controls the output enable time to properly prevent the output voltage of the gate from overlapping regardless of the change of the gate line resistance and capacitor value. This prevents data from malfunctioning and prevents delays in the gate lines, providing an excellent effect of shortening the output voltage time.

Claims (1)

A controller for generating a control signal for preventing overlapping and delay of the gate output voltage; A counting unit mounted on the control unit and counting and outputting a predetermined number of counts according to the output enable time of the gate line voltage; The controller is mounted on the control unit, and when the user sets the output enable time of the gate line voltage through the mode setting input terminal, the gate line voltage is output according to the set output enable time if it matches with the count number input from the count unit. And an output enable setting unit for outputting the gate line delay compensation apparatus of the TFT-LCD.