KR19980058291A - Block Interleaving / Deinterleaving Method - Google Patents

Block Interleaving / Deinterleaving Method Download PDF

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KR19980058291A
KR19980058291A KR1019960077614A KR19960077614A KR19980058291A KR 19980058291 A KR19980058291 A KR 19980058291A KR 1019960077614 A KR1019960077614 A KR 1019960077614A KR 19960077614 A KR19960077614 A KR 19960077614A KR 19980058291 A KR19980058291 A KR 19980058291A
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interleaving
deinterleaving
data
memory
deinterleaving method
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KR1019960077614A
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KR100218153B1 (en
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김동욱
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정장호
엘지정보통신 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory

Abstract

본 발명의 목적은 전송지연이 적고 하드웨어적으로 구현이 용이한 블럭 인터리빙/디인터리빙 방법을 제공하는 데 있다.An object of the present invention is to provide a block interleaving / deinterleaving method having a low transmission delay and easy to implement in hardware.

본 발명에 따른 블럭 인터리빙/디인터리빙 방법은 인터리빙시의 라이트 동작은 (1, 1)(1, 2)...(1, M), (2, 1)(2, 2)...(2, M),....,(N, 1)(N, 2)...(N, M)순서로, 인터리빙시의 리드동작은 (1, 1)(2, N)(3, N-1)...(M, N-(M-2)), (1, 2)(2, 1)(3, N)...(M, N-(M-3)), (1, 3)(2, 2)(3, 1)...(M, N-(M-4)), ... ,(1, N)(2, N-1)(3, N-2)...(M, (N-M+1)) 순서로 이루어지고, 디인터리빙시의 라이트 동작은 (1, 1)(1, 2)...(1, N), (2, 1)(2, 2)...(2, N), ... ,(M, 1)(M, 2)...(M, N) 순서로, 디인터리빙시의 리드동작은 (1, N-(M-2))(2, N-(M-3))(3, N-(M-4))...(M, 1), (1, M-(N-3))(2, N-(M-4))(3, N-(M-5))...(M, 2), (1, N-(M-4))(2, N-(M-5))(3, N-(M-6))...(M, 3),...,(1, N-M+1)(2, N-M+2)(3, N-M+2)...(M, N)순서로 이루어지고, 인터리빙 시(1, 1) (2, 1),...(N, 1)에 라이트 할 데이타는 라이트하지 아니하고 전송하는 것을 특징으로 한다.In the block interleaving / deinterleaving method according to the present invention, the write operation during interleaving is (1, 1) (1, 2) ... (1, M), (2, 1) (2, 2) ... ( 2, M), ..., (N, 1) (N, 2) ... (N, M), the interleaving read operation is (1, 1) (2, N) (3, N-1) ... (M, N- (M-2)), (1, 2) (2, 1) (3, N) ... (M, N- (M-3)), ( 1, 3) (2, 2) (3, 1) ... (M, N- (M-4)), ..., (1, N) (2, N-1) (3, N- 2) ... (M, (N-M + 1)), and the write operation during deinterleaving is (1, 1) (1, 2) ... (1, N), (2, 1) (2, 2) ... (2, N), ..., (M, 1) (M, 2) ... (M, N) In order, the read operation during deinterleaving is (1 , N- (M-2)) (2, N- (M-3)) (3, N- (M-4)) ... (M, 1), (1, M- (N-3) (2, N- (M-4)) (3, N- (M-5)) ... (M, 2), (1, N- (M-4)) (2, N- (M -5)) (3, N- (M-6)) ... (M, 3), ..., (1, N-M + 1) (2, N-M + 2) (3, N -M + 2) ... (M, N) in order, and when interleaving (1, 1) (2, 1), ... (N, 1), the data to be written is transmitted without writing. It features.

Description

블럭 인터리빙/디인터리빙 방법Block Interleaving / Deinterleaving Method

본 발명은 전송시스템에 관한 것이며, 보다 상세히는 디지탈신호의 전송과정에서 발생하는 연집에러(Burst Error)를 방지하기 위한 메모리를 사용하는 블럭 인터리빙/디인터리빙 방법에 관한 것이다.The present invention relates to a transmission system, and more particularly, to a block interleaving / deinterleaving method using a memory for preventing burst errors occurring in a digital signal transmission process.

일반적으로 전송시스템에서는 디지탈 데이타가 전송하는 도중에 발생하는 연집에러를 방지하기 위하여 데이타를 구성하는 비트를 일정한 법칙에 따라 혼합하여 전송한 후 다시 이를 원상태로 배열하는 인터리빙/디인터리빙 방법을 채용하고 있으며, 인터리빙/디인터리빙 방법으로는 송신측에서 전송할 데이타를 메모리에 라이트하고 라이트한 순서와 달리하여 메모리로부터 전송데이타를 리드하여 전송하고 수신측에서 송신측에서 메모리에 라이트하고 리드하는 순서와 역으로 메모리에 라이트하고 리드하여 원래의 데이타 배열을 회복하는 블럭(Block) 인터리빙/디인터리빙 방법 방법과 시프트 레지스터를 사용하여 송신측에서 각 전송데이타를 구성하는 비트의 전송 지연을 발생시켜 송신하고 수신측에서는 송신측과 반대로 전송데이타를 구성하는 비트의 전송 지연을 발생시켜 원래의 데이타 배열을 회복하는 방법이 있다.In general, a transmission system employs an interleaving / deinterleaving method in which bits constituting data are mixed and transmitted according to a certain law in order to prevent continuous errors occurring during the transmission of digital data, and then arranged again. In the interleaving / deinterleaving method, the sender writes and transfers data to the memory in a different order from the sender's memory. The block interleaving / deinterleaving method of writing, reading, and restoring the original data array, and using the shift register, generate and transmit the transmission delay of the bits constituting each transmission data at the transmitting side, and at the receiving side, Conversely, you can configure the transmission data. Generating a transmission delay of a bit to a method for restoring the original data arrangement.

본 명세서에서의 메모리의 구조는 가로는 M, 세로는 N개의 어드레스를 갖는 것으로 하고, 데이타가 저장되는 위치는 가로 어드레스 및 세로 어드레스의 조합(M, N)으로 표현한다.In the present specification, the memory has a horizontal width and a vertical length having N addresses, and a location where data is stored is expressed by a combination of the horizontal address and the vertical address (M, N).

도1은 종래의 블럭 인터리빙/디인터리빙 방법을 도시한 도면으로서, 도1A는 인터리빙 또는 디인터리빙할 때의 메모리에 데이타를 라이트하는 순서를 도시한 도면이고, 도1B는 인터리빙 또는 디인터리빙할 때의 메모리로부터 데이타를 리드하는 순서를 도시한 도면이다.FIG. 1 is a diagram illustrating a conventional block interleaving / deinterleaving method, and FIG. 1A is a diagram illustrating a procedure of writing data to a memory when interleaving or deinterleaving, and FIG. 1B is a diagram illustrating interleaving or deinterleaving. It is a figure which shows the procedure of reading data from a memory.

도1A를 보면, 종래의 인터리빙 또는 디인터리빙 방법에서는 (1, 1)(1, 2)...(1, M), (2, 1)(2, 2)...(2, M),....,(N, 1)(N, 2)...(N, M)순서로 라이트하고, (1, 1)(2, 1)...(N, 1), (1, 2)(2, 2)...(N, 2), ... ,(1, M)(2, M)...(N, M)의 순서로 리드(Read)한다.1A, in the conventional interleaving or deinterleaving method, (1, 1) (1, 2) ... (1, M), (2, 1) (2, 2) ... (2, M) , ...., (N, 1) (N, 2) ... (N, M) in order, (1, 1) (2, 1) ... (N, 1), (1 (2, 2) ... (N, 2), ..., (1, M) (2, M) ... (N, M) Read in order.

종래의 인터리빙/디인터리빙 방법에 따르면, 메모리에서 라이트 동작과 리드 동작이 동시에 일어나는 경우 5, 9, 13, 10, 14, 15의 데이타는 라이트 동작이 일어나기 전에 리드되기 때문에 이전에 라이트된 데이터들이 전송되어 디인터리빙할 때 데이타를 원래의 순서대로 배열할 수 없으므로 메모리의 라이트 동작과 리드 동작이 별도로 이루어지도록 한다. 따라서, 전송지연이 크다는 문제점이 있었다. 또한 메모리의 행의 수만큼 계수기가 소요되어 하드웨어적으로 구현하기 어렵다는 문제점이 있었다.According to the conventional interleaving / deinterleaving method, when a write operation and a read operation occur simultaneously in the memory, data of 5, 9, 13, 10, 14, and 15 are read before the write operation occurs, and thus the previously written data are transmitted. When data is deinterleaved, data cannot be arranged in the original order so that the memory write and read operations are performed separately. Therefore, there is a problem that the transmission delay is large. In addition, there is a problem that it is difficult to implement in hardware because the counter is required as many as the number of rows of the memory.

본 발명의 목적은 전송지연이 적고 하드웨어적으로 구현이 용이한 블럭 인터리빙/디인터리빙 방법을 제공하는 데 있다.An object of the present invention is to provide a block interleaving / deinterleaving method having a low transmission delay and easy to implement in hardware.

도1은 종래의 블럭 인터리빙/디인터리빙 방법을 도시한 도면으로서1 is a diagram illustrating a conventional block interleaving / deinterleaving method.

도1A는 인터리빙 또는 디인터리빙할 때의 메모리에 데이타를 라이트하는 순서를 도시한 도면Fig. 1A is a diagram showing a procedure of writing data to a memory when interleaving or deinterleaving.

도1B는 인터리빙 또는 디인터리빙할 때의 메모리로부터 데이타를 리드하는 순서를 도시한 도면Fig. 1B is a diagram showing a procedure of reading data from a memory when interleaving or deinterleaving.

도2는 본 발명의 실시예에 따른 블럭 인터리빙/디인터리빙 방법을 도시한 도면으로서2 illustrates a block interleaving / deinterleaving method according to an embodiment of the present invention.

도2A는 인터리빙 또는 디인터리빙할 때의 메모리에 데이타를 라이트하는 순서를 도시한 도면Fig. 2A is a diagram showing a procedure of writing data to a memory when interleaving or deinterleaving.

도2B는 인터리빙할 때의 메모리로부터 데이타를 리드하는 순서를 도시한 도면Fig. 2B is a diagram showing a procedure of reading data from a memory when interleaving.

도2C는 디인터리빙할 때의 메모리에 데이타를 라이트하는 순서를 도시한 도면Fig. 2C is a diagram showing a procedure of writing data to a memory when deinterleaving.

본 발명에 따른 블럭 인터리빙/디인터리빙 방법은 인터리빙시의 라이트 동작은 (1, 1)(1, 2)...(1, M), (2, 1)(2, 2)...(2, M),....,(N, 1)(N, 2)...(N, M)순서로, 인터리빙시의 리드동작은 (1, 1)(2, N)(3, N-1)...(M, N-(M-2)), (1, 2)(2, 1)(3, N)...(M, N-(M-3)), (1, 3)(2, 2)(3, 1)...(M, N-(M-4)), ... ,(1, N)(2, N-1)(3, N-2)...(M, (N-M+1)) 순서로 이루어지고, 인터리빙시의 라이트 동작은 (1, 1)(1, 2)...(1, N), (2, 1)(2, 2)...(2, N), ... ,(M, 1)(M, 2)...(M, N) 순서로, 디인터리빙시의 리드동작은 (1, N-(M-2))(2, N-(M-3))(3, N-(M-4))...(M, 1), (1, M-(N-3))(2, N-(M-4))(3, N-(M-5))...(M, 2), (1, N-(M-4))(2, N-(M-5))(3, N-(M-6))...(M, 3),...,(1, N-M+1)(2, N-M+2)(3, N-M+2)...(M, N)순서로 이루어지고, 인터리빙 시(1, 1) (2, 1),...(N, 1)에 라이트 할 데이타는 라이트하지 아니하고 전송하는 것을 특징으로 한다.In the block interleaving / deinterleaving method according to the present invention, the write operation during interleaving is (1, 1) (1, 2) ... (1, M), (2, 1) (2, 2) ... ( 2, M), ..., (N, 1) (N, 2) ... (N, M), the interleaving read operation is (1, 1) (2, N) (3, N-1) ... (M, N- (M-2)), (1, 2) (2, 1) (3, N) ... (M, N- (M-3)), ( 1, 3) (2, 2) (3, 1) ... (M, N- (M-4)), ..., (1, N) (2, N-1) (3, N- 2) ... (M, (N-M + 1)) in order, and interleaving write operations are (1, 1) (1, 2) ... (1, N), (2, 1 ) (2, 2) ... (2, N), ..., (M, 1) (M, 2) ... (M, N) In order, the read operation during deinterleaving is (1, N- (M-2)) (2, N- (M-3)) (3, N- (M-4)) ... (M, 1), (1, M- (N-3)) (2, N- (M-4)) (3, N- (M-5)) ... (M, 2), (1, N- (M-4)) (2, N- (M- 5)) (3, N- (M-6)) ... (M, 3), ..., (1, N-M + 1) (2, N-M + 2) (3, N- M + 2) ... (M, N) sequence, and the data to be written in (1, 1) (2, 1), ... (N, 1) is transmitted without being written. It is done.

인터리빙 시 (1, 1) (2, 1),...,(N, 1)에 라이트 할 데이타는 라이트하지 아니하고 바로 전송하는 것은 이 부분의 데이타는 동시에 라이트되고 리드동작이 이루어지는 부분이므로 라이트하지 아니하고 바로 전송되도록 한다.When interleaving, do not write the data to be written to (1, 1) (2, 1), ..., (N, 1) and send it immediately because the data of this part is written simultaneously and the read operation is performed. To be sent immediately.

본 발명에 따른 블럭 인터리빙/디인터리빙 방법을 실시하기 위하여 송신측과 수신측의 메모리는 데이타의 라이트동작과 리드동작을 동시에 할 수 있는 이중포트 램을 사용하고 이중포트 램의 가로어드레스와 세로어드레스를 카운트하기 위하여 각각 가로 어드레스카운터와 세로어드레스 카운터가 필요하다.In order to implement the block interleaving / deinterleaving method according to the present invention, the memory of the transmitting side and the receiving side uses a dual port RAM capable of simultaneously writing and reading data, and the horizontal and vertical addresses of the dual port RAM are used. To count, you need a horizontal address counter and a vertical address counter, respectively.

도2는 본 발명의 실시예에 따른 블럭 인터리빙/디인터리빙 방법을 도시한 도면으로서, 도2A는 인터리빙 또는 디인터리빙할 때의 메모리에 데이타를 라이트하는 순서를 도시한 도면이고, 도2B는 인터리빙할 때의 메모리로부터 데이타를 리드하는 순서를 도시한 도면이고, 도2C는 디인터리빙할 때의 메모리에 데이타를 라이트하는 순서를 도시한 도면이다.FIG. 2 is a diagram illustrating a block interleaving / deinterleaving method according to an embodiment of the present invention, and FIG. 2A is a diagram illustrating a procedure of writing data to a memory when interleaving or deinterleaving. FIG. FIG. 2C is a diagram showing a procedure of reading data from a memory at the time, and FIG. 2C is a diagram showing a procedure of writing data to a memory at the time of deinterleaving.

상술한 바와 같이, 본 발명에서는 블럭 인터리빙/디인터리빙할 때 메모리에서 데이타의 라이트 동작과 리드동작이 동시에 이루어질 수 있도록 함으로써 전송지연을 줄일 수 있으며, 또한 각각 1개씩의 가로어드레스카운터 및 세로어드레스카운터를 사용함으로써, 하드웨어적으로 용이하게 구현할 수 있다.As described above, in the present invention, when the block interleaving / deinterleaving, the write and read operations of the data can be simultaneously performed in the memory, the transmission delay can be reduced, and one horizontal address counter and one vertical address counter are respectively provided. By using it, it can implement easily in hardware.

본 발명에 따른 블럭 인터리빙/디인터리빙 방법에서 동시에 메모리에 라이트되고 리드되는 데이타는 라이트하지 아니하고 바로 전송되도록 함으로써, 전송지연 효과를 높일 수 있다.In the block interleaving / deinterleaving method according to the present invention, data that is simultaneously written and read into the memory is transmitted without being written, thereby increasing the transmission delay effect.

Claims (1)

인터리빙시의 라이트 동작은 (1, 1)(1, 2)...(1, M), (2, 1)(2, 2)...(2, M),....,(N, 1)(N, 2)...(N, M)순서로, 인터리빙시의 리드동작은 (1, 1)(2, N)(3, N-1)...(M, N-(M-2)), (1, 2)(2, 1)(3, N)...(M, N-(M-3)), (1, 3)(2, 2)(3, 1)...(M, N-(M-4)), ... ,(1, N)(2, N-1)(3, N-2)...(M, (N-M+1)) 순서로 이루어지고, 디인터리빙시의 라이트 동작은 (1, 1)(1, 2)...(1, N), (2, 1)(2, 2)...(2, N), ... ,(M, 1)(M, 2)...(M, N) 순서로, 디인터리빙시의 리드동작은 (1, N-(M-2))(2, N-(M-3))(3, N-(M-4))...(M, 1), (1, M-(N-3))(2, N-(M-4))(3, N-(M-5))...(M, 2), (1, N-(M-4))(2, N-(M-5))(3, N-(M-6))...(M, 3),...,(1, N-M+1)(2, N-M+2)(3, N-M+2)...(M, N)순서로 이루어지고, 인터리빙 시(1, 1) (2, 1),...(N, 1)에 라이트 할 데이타는 라이트하지 아니하고 전송하는 것을 특징으로 하는 블럭 인터리빙/디인터리빙 방법.The write operation during interleaving is (1, 1) (1, 2) ... (1, M), (2, 1) (2, 2) ... (2, M), ... In order of N, 1) (N, 2) ... (N, M), the interleaving read operation is (1, 1) (2, N) (3, N-1) ... (M, N -(M-2)), (1, 2) (2, 1) (3, N) ... (M, N- (M-3)), (1, 3) (2, 2) (3 , 1) ... (M, N- (M-4)), ..., (1, N) (2, N-1) (3, N-2) ... (M, (N- M + 1)), and the write operation during deinterleaving is (1, 1) (1, 2) ... (1, N), (2, 1) (2, 2) ... ( 2, N), ..., (M, 1) (M, 2) ... (M, N), the read operation during deinterleaving is (1, N- (M-2)) (2 , N- (M-3)) (3, N- (M-4)) ... (M, 1), (1, M- (N-3)) (2, N- (M-4) ) (3, N- (M-5)) ... (M, 2), (1, N- (M-4)) (2, N- (M-5)) (3, N- (M -6)) ... (M, 3), ..., (1, N-M + 1) (2, N-M + 2) (3, N-M + 2) ... (M, N) a block interleaving / de-interleaving method comprising the steps of: (1, 1) (2, 1), ... (N, 1) to transmit data without writing.
KR1019960077614A 1996-12-30 1996-12-30 Block interleave/deinterleave method of data communication KR100218153B1 (en)

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