KR19980056122A - Memory Cell Arrays in Semiconductor Memory Devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell array of a semiconductor memory device, wherein redundancy for replacing a defective memory cell when the memory cells are disposed adjacent to the memory cells and when some of the memory cells are defective are defective. And a plurality of dummy memory cells disposed between the normal memory cells and the redundancy memory cells to prevent a bridge from occurring between the normal memory cells and the redundancy memory cells. Bridges between normal memory cells and redundant memory cells are prevented from occurring, which prevents semiconductor memory devices that are found to be good in test but are actually defective.

Description

Memory cell array of semiconductor memory device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell array of a semiconductor memory device, and more particularly to a memory cell array of a semiconductor memory device for preventing a memory cell test from becoming a good product even when a bridge between memory cells occurs.

In the highly integrated memory, since the size of the semiconductor chip is increased and the size of the memory cell is reduced, a bridge is generated between the memory cell and the memory cell, causing the memory cell to be defective. Therefore, in order to increase the production yield of semiconductor chips, normal memory cells and redundancy memory cells are arranged in the memory cell array. The quality and repairability of the semiconductor chip are determined by testing the quantity and defect of the normal memory cell and the redundant memory cell of the memory cell array, respectively, to determine whether to use the semiconductor chip. Testing the normal memory cell during the test of the semiconductor chip determines the quantity and defect of the normal memory cell, and if a defective memory cell is found, replaces it with a redundant memory cell. In this case, if the redundant memory cell is not tested, the defective redundancy is tested. Since there is a risk of repairing the memory cell, a separate redundancy memory cell test removes the bad memory cell, and then replaces the defective normal memory cell with a good quality redundancy memory cell. However, in the highly integrated memory cell array, since the memory cell array is small in size, bridges between the memory cells and the memory cells frequently occur. When a bridge occurs between a normal memory cell and a normal memory cell, a bad memory cell is detected by a normal memory cell test, and when a bridge occurs between a redundancy memory cell and a redundant memory cell, a bad redundancy memory cell is detected by a redundancy memory cell test. However, when the bridge between the normal memory cell and the redundancy cell is not detected by each cell test, the semiconductor chip should be treated as defective when the defective normal cell is repaired with the redundant cells detected as good. In this case, if the number of semiconductor chips is very large, there is no problem even if it is treated as defective, but in the high density memory, the number of semiconductor chips is extremely small, which causes a fatal decrease in yield in such a case.

1 is a layout view of a memory cell array of a conventional semiconductor memory device. Redundancy memory cell blocks 13 and 15 are disposed at left and right ends of the memory cell array 10, and a normal memory cell block 11 is disposed between the redundancy memory cell blocks 13 and 15.

FIG. 2 is a diagram illustrating a case where a bridge occurs in the memory cell array 10 shown in FIG. 1. In FIG. 2, a bridge 25 is formed between the bit line 23 of the normal memory cell block 11 and the bit line 21 of the redundancy memory cell 15. As such, even when a bridge 25 is formed between the bit line 23 of the normal memory cell block 11 and the bit line 21 of the redundancy memory cell block 15, the memory cell array 10 may perform the test when the bridge 25 is formed. The semiconductor memory device having the memory cell array 10 turns out to be good. However, when actually used, the semiconductor memory device including the memory cell array 10 is defective.

As described above, an object of the present invention is to provide a semiconductor memory device for preventing a test from being proved good even though a bridge occurs between memory cells.

1 is a layout view of a memory cell array of a conventional semiconductor memory device.

FIG. 2 is a diagram illustrating a case where a bridge occurs in the memory cell array illustrated in FIG. 1.

3 is a layout view of a memory cell array of a semiconductor memory device according to the present invention;

FIG. 4 is a diagram illustrating a case in which a failure does not occur even when a bridge occurs in the memory cell array illustrated in FIG. 3.

The present invention to achieve the above object,

Redundant memory cells and redundancy memory cells disposed adjacent to the normal memory cells to replace the defective memory cell when some of the normal memory cells are defective and between the normal memory cells and the redundant memory cells A memory cell array of a semiconductor memory device having a plurality of dummy memory cells arranged to prevent a bridge from occurring between the normal memory cells and the redundancy memory cells is provided.

According to the present invention, a bridge is prevented from occurring between a normal memory cell and a redundant memory cell of a memory cell array of the semiconductor memory device, thereby preventing a semiconductor memory device that is proved to be good in a test but is actually defective.

Hereinafter, the present invention will be described in detail through examples.

3 is a layout view of a memory cell array of a semiconductor memory device according to the present invention. The structure of the memory cell array 30 shown in FIG. 1 is disposed near the normal memory cell block 31 and the normal memory cell block 31 so that some of the memory cells of the normal memory cell block 31 are disposed. Redundancy memory cell blocks 33 and 35 and redundancy memory cell blocks 31 and redundancy memory cell blocks 33 and 35 in which redundancy memory cells are disposed to replace the defective memory cell in the case of failure The dummy memory cell blocks 37 and 39 are disposed between the normal memory cell block 31 and the redundancy memory cell blocks 33 and 35.

FIG. 4 is a diagram illustrating a case in which a failure does not occur even when a bridge occurs in the memory cell array 30 illustrated in FIG. 3. As shown in FIG. 4, a bridge may never be generated between the normal memory cell block 31 and the redundancy memory cell blocks 33 and 35. Instead, between the bit line 45 of the normal memory cell block 31 and the bit line 43 of the dummy memory cell block 39 or the bit line 43 of the dummy memory cell block 39 and the redundancy memory cell. Even if a bridge 47 occurs between the bit lines 41 of the block 35, this has no effect on actual use. This is because the dummy memory cell blocks 37 and 39 are not used at all.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, a bridge is prevented from occurring between a normal memory cell and a redundancy memory cell of the memory cell array of the semiconductor memory device, thereby preventing a semiconductor memory device that proves to be good in a test but is actually defective. have.

Claims (1)

Normal memory cells; Redundancy memory cells disposed adjacent to the normal memory cells to replace the defective memory cell when some of the normal memory cells are defective; And And a plurality of dummy memory cells disposed between the normal memory cells and the redundancy memory cells to prevent a bridge from occurring between the normal memory cells and the redundancy memory cells. .