KR19980055723A - Decoder Circuit in Flash Memory - Google Patents

Abstract

The present invention provides a decoder circuit in a flash memory, and uses a global row decoder in a flash memory device capable of writing sector by sector, and a local row decoder which inputs the output of the global row decoder when dividing a sector in a column direction. By increasing the number of sectors, the access time can be reduced by minimizing the load caused by the row address signal, and the circuit of the local row decoder used is simple to minimize the size of the chip as well as the pumping voltage Vpp and By reducing the load on -Vpp, stable operation can be realized.

Description

Decoder Circuit in Flash Memory

The present invention provides a flash memory device that can use a global row decoder in a flash memory device capable of writing sector by sector, and increase the number of sectors in the local row decoder that inputs the output of the global row decoder when the sector is divided in the column direction. Relates to a row decoder circuit.

In general, flash memory devices have electrical programming and erasing functions. In a sector-programmable flash memory device, write cycles are typically guaranteed at least 100,000 times. At this time, the number of stresses applied to the gate of the unit cell is the number of unit cells connected to one word line, and the number of stresses received at the drain of the unit cell is the number of unit cells connected to one bit line. 1 is a circuit diagram of a row decoder conventionally used.

First, in the read mode, the first voltage supply signal SnVppx is switched to the Vdd voltage level, and the second voltage supply signal SnVeex and the XRST are switched to the ground voltage level. At this time, the P-MOS transistor hp1 is turned on so that all the node points A have the Vdd voltage level, and the Vdd voltage level applied to the node point A turns on the N-MOS transistor thn to turn the ground voltage on the sector word line SnWL. Have a level.

On the other hand, only one XnCOM selected by the NAND gate I for inputting the row address signals XBPRED and XCPRED and the sector signal S has the ground voltage level, and at this time, only one XAPRED is selected by the Vdd voltage level. The NMOS transistor hn of the row decoder to be turned on is turned on, and the node point A of the selected row decoder has a ground voltage level. Therefore, the ground voltage level applied to the node point A turns on the P-MOS transistor hp3 to give the sector word line SnWL a Vdd voltage level.

Next, in the program mode, the first voltage supply signal SnVppx of the selected sector is switched to the Vpp voltage level, all the second voltage supply signals SnVeex are switched to the ground voltage level, and XRST is the first voltage. Until the supply signal SnVppx becomes the Vpp voltage level, the ground voltage level is maintained, and when the Vpp voltage level is reached, the XRST of the selected sector is switched to become the Vpp voltage level. The first voltage supply signal SnVppx of the unselected sector maintains the Vdd voltage level, and the XRST of the unselected sector maintains the ground voltage level, so that the word line SnWL of the unselected sector has the ground voltage level. .

On the other hand, one XnCOM selected by the NAND gate I which inputs the row address signals XBPRED and XCPRED and the sector signal S has a ground voltage level, and at this time, only one XAPRED is selected by being the Vdd voltage level. The NMOS transistor hn of the row decoder to be turned on is turned on, and the node point A of the selected row decoder has a ground voltage level. Therefore, the ground voltage level applied to the node point A turns on the P-MOS transistor hp3 to give the sector word line SnWL a Vpp voltage level.

Finally, in the erase mode, the first voltage supply signal SnVppx of the selected sector is switched to the ground voltage level, the second voltage supply signal SnVeex is switched to the -Vpp voltage level, and the XRST is set to the ground voltage level. Switching. The first voltage supply signal SnVppx of the unselected sector is switched to the Vdd voltage level, the second voltage supply signal SnVeex is switched to the ground voltage level, and the XRST is switched to the ground voltage level.

As a result, the node point A of the non-selected sector becomes the Vdd voltage level, and thus the sector word line SnWL has a ground voltage level.

Meanwhile, in the row decoder of the selected sector, the NMOS transistor thn is turned on so that all word lines SnWL have a voltage level of -Vpp.

As the row decoder as described above divides the sector in the column direction, the number of row decoders increases so that the number of XnCOMs of the row decoder increases so that the predecoder output load and the address buffer output load increase proportionally. Access Time) is delayed, and the size of the chip also increases.

Accordingly, the present invention uses a global row decoder in a flash memory device capable of writing sector-by-sector, and increases the number of sectors in the row address signal by increasing the number of sectors in the local row decoder that inputs the output of the global row decoder when the sector is divided in the column direction. It is an object of the present invention to provide a low decoder circuit in a flash memory device capable of increasing the access time while reducing the size of the chip by minimizing the load caused by the Low Address Path.

The present invention for achieving the above object consists of a global row decoder for selecting a plurality of sector word lines, and a local row decoder for selecting each of the sector word lines selected by the global row decoder.

1 is a circuit diagram showing a typical row decoder.

2 is a circuit diagram illustrating a global row decoder in accordance with the present invention.

3 is a circuit diagram illustrating a local row decoder in accordance with the present invention.

Explanation of symbols on the main parts of the drawings

T1: first transistor T2: second transistor

T3: third transistor T4: fourth transistor

T5: fifth transistor hp1 to hp3: P-MOS transistor

hn and thn: N-MOS transistor

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a global row decoder according to the present invention, in which an output signal of the first decoding means I11 is determined by row address signals XAPRED, XBPRED and XCPRED. The output signal of the first decoding means I11 is input to the second decoding means I12 together with the erase signal E to select the global word line GWL. The first and second decoding means I11 and I12 consist of NAND gates. That is, in the read mode and the program mode, only one of the multiple global word lines GWL is selected as the Vdd voltage level, and in the erase mode E, the erase signal E becomes the ground voltage level so that all global row decoders have global words. The output signal of the line GWL has a voltage level of Vdd.

FIG. 3 is a global word line GWL, which is an output signal of the global row decoder of FIG. 2, and is input only to a sector word line SnWL of a column sector selected by a combination of column sector addresses SnCOM. Is a circuit diagram of a local row decoder configured to transmit an output voltage and to have a ground voltage level in a sector word line SnWL of an unselected column sector.

The operation of the local row decoder will be described by mode as follows.

First, in the read mode, the first voltage supply signals SnVppx of all the column sectors are switched to the Vdd voltage level, and the second voltage supply signal SnVeex is switched to the ground voltage level. The column sector address SnCOM selected in the column sector is switched to the ground voltage level, and in the non-selected column sector, the column sector address SnCOM is switched to be the Vdd voltage level. As a result, the local row decoder turns on the second transistor T2 by the unselected global word line GWL so that the node B becomes the Vdd voltage level, and the voltage applied to the node point B turns the fifth transistor T5 on. The sector word line SnWL is brought to the ground voltage level.

On the other hand, the selected global word line GWL becomes the Vdd voltage level to turn on the first transistor T1, so that the node point B becomes the voltage of the column sector address SnCOM by the column sector. Therefore, since the column sector address SnCOM of the non-selected column sectors is at the Vdd voltage level, the fifth transistor T5 is turned on so that the sector word line SnWL becomes the ground voltage level, and only the column sector address SnCOM of the selected column sector is turned on. Since the ground voltage level is reached, the fourth transistor T4 is turned on so that the sector word line SnWL has the Vdd voltage level. Therefore, only one selected sector word line SnWL among all sector word lines SnWL has a Vdd voltage level, and the other sector word lines SnWL have a ground voltage level.

Next, in the program mode, the first voltage supply signal SnVppx of the selected sector is switched to the Vpp voltage level, the first voltage supply signal SnVppx of the unselected sectors is switched to the Vdd voltage level, and all the second voltage supply signals are (SnVeex) is switched to ground voltage level. In addition, the column sector address SnCOM of the selected column sector is switched to the ground voltage level, and the unselected column sector address SnCOM is switched to the Vdd voltage level. Therefore, the non-selected global word line GWL turns on the second transistor T2 so that the node point B becomes the Vdd voltage level, and the Vdd voltage level applied to the node point B turns the fifth transistor T5 into the corresponding sector. The word line SnWL becomes a ground voltage level.

On the other hand, the selected global word line GWL turns on the first transistor T1, so that the node point B becomes the column sector address SnCOM voltage by the column sector. At this time, in the non-selected column sector, the third and fifth transistors T3 and T5 are turned on so as to have a ground voltage level in the sector word line SnWL, and in the selected column sector, the fourth transistor T4 is turned on in the sector word. The line SnWL is set at the Vpp voltage level.

Therefore, only one sector word line SnWL selected from all sector word lines SnWL becomes the Vpp voltage level, and the other sector word lines SnWL become the ground voltage level.

When the first voltage supply signal SnVppx and the second voltage supply signal SnVeex are shared by a plurality of local row decoders due to a chip size problem, in the program mode, the column sector address (SnCOM) of the selected column sector is changed. The voltage is as mentioned above, and the column sector address SnCOM in the unselected column sector having the common first voltage supply signal SnVppx and the second voltage supply signal SnVeex has the same Vpp voltage level. Becomes

Finally, the first voltage supply signal SnVppx of the sector selected in the erase mode is switched to the ground voltage level, and the second voltage supply signal SnVeex is switched to the -Vpp voltage level. The first voltage supply signal SnVppx of the unselected sectors is switched to the Vdd voltage level, and the second voltage supply signal SnVeex is switched to the ground voltage level. Since the global word line GWL, which is the output of the global row decoder, has the mode Vdd voltage level, the first transistor T1 is turned on by the global word line GWL, and the node point B is the column sector address SnCOM voltage due to the column sector. Becomes At this time, since the first voltage supply signal SnVppx and the column sector address SnCOM of the non-selected sectors are at the Vdd voltage level, the node point B is at the Vdd voltage level, thereby turning on the fifth transistor T5. The lines SnWL all have a ground voltage level.

Meanwhile, since the first voltage supply signal SnVppx of the selected sector is the ground voltage level, the second voltage supply signal SnVeex is the -Vpp voltage level, and the column sector address SnCOM is the ground voltage level, so that all of the sectors selected. By turning on the fifth transistor T5 of the local row decoder, all sector word lines SnWL of the selected sector are at the -Vpp voltage level.

As described above, according to the present invention, a flash memory device capable of writing by sector uses a global row decoder, and when a sector is divided in a column direction, the local row decoder which inputs the output of the global row decoder as the number of sectors is increased by the number of sectors. By minimizing the load caused by the address signal, the access time can be reduced, and the circuit of the local row decoder used is simple to reduce the size of the chip, as well as the load on the pumping voltages Vpp and -Vpp. It is excellent effect that can realize stable operation by reducing.

Claims (10)

In the decoder circuit in the flash memory, A global row for inputting a row address signal and having a first decoding means selected according to the row address signal and a second decoding means for inputting an output signal and an erase signal of the first decoding means to output a global wordline signal. With a decoder, And a local row decoder for selecting each of the word lines selected by said global row decoder. The method of claim 1, And said first and second decoding means comprise NAND gates. The method of claim 1, And said erasing signal is at ground voltage level only in the erasing mode. The method of claim 1, The local row decoder may include first and second transistors configured to input selected or unselected global wordline signals and operate according to the selected or unselected global wordline signals; It is composed of third to fifth transistors that operate in accordance with a first voltage supply signal or a column sector address signal transmitted by the operation of the first and second transistors, thereby supplying a first voltage by operation of the third to fifth transistors. Outputting a signal or a second voltage supply signal to a sector word line. The method of claim 4, wherein The selected global wordline turns on the first transistor in read and program modes to deliver column sector address signals of selected or unselected sectors, and the unselected global wordline turns on the second and fifth transistors and And turning off the fourth transistor to bring the sector word line to the ground voltage level. The method of claim 5, The column sector address signal of the selected sector is at ground voltage level and the fifth transistor is turned off and the fourth transistor is turned on to transfer the first voltage supply signal to the selected sector word line, and the column sector address signal of the unselected sector is The decoder circuit of claim 1, wherein the second voltage supply signal is transmitted to the sector word line by turning on the fifth transistor. The method of claim 4, wherein The selected global word line is at the Vdd voltage level in the erase mode and turns on the first transistor and turns off the second transistor to transfer column sector address signals of selected or unselected sectors. Circuit. The method of claim 7, wherein In the selected sector, the first voltage supply signal is switched to the ground voltage level in the erase mode, the second voltage supply signal is at the -Vpp voltage level, and the unselected sector is at the Vdd voltage level in the erase mode. And the second voltage supply signal is switched to the ground voltage level. The method according to claim 7 or 8, And the column sector address signal of the selected or unselected sector is at ground voltage level, and the fourth transistor is turned off and the fifth transistor is turned on to transfer the second voltage supply signal to all sector word lines of the selected sector. Row decoder circuit in memory. The method according to any one of claims 4 to 8, And the second to fourth transistors are PMOS transistors, and the first and fifth transistors are NMOS transistors.