JPH04205792A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To facilitate the layout of a VPP switch even when a device is highly integrated by connecting the output of the VPP switch to the word line of a memory cell row which is not connected to the same source line and switching the source line in terms of an 'L' level and a floating state. CONSTITUTION:The word lines WL9, WL11, WL10 and WL12 of the memory cell row which is not connected to the same source line are connected to the output of the same VPP. In the case of selecting the word line WL1, a transistor(Tr) 20 is turned on and a Tr19 is turned off according to a predecoding signal, and 'L' is inputted in the VPP switch 37. At such a time, a VPPWL 41 becomes VCC in the case of readout, and it becomes VPP in the case of write, then the word lines WL9 and WL11 become VCC or VPP. In such a state, a source line decoding signal EVEN 46 is made 'L', an ODD 47 is made 'H'. Then, the Tr 44 is turned off and the Tr 45 is turned on so as to set the source line 42 floating and the line 43 at 'L' level. Thus, the readout and the write of the WL9 are executed. Therefore, the VPP switch is reduced and the layout is facilitated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to non-volatile semiconductor memory devices, particularly EFROM.
, regarding flash EEFROM.

[Conventional technology]

FIG. 2 is a circuit diagram showing part of a conventional memory array and part of a row decoder circuit. In the figure, (1) to (8
) are memory cells of EPROM or FRAS) IEEPROM, (9) to (12) are word lines, (13)
(14) is a bit line, (15) is a common source line within one array, (+6) (+8) is a P-channel transistor, (17) (19) to (26) are N-channel transistors, (27) ~(34) is a 4-tree word line (
(35) is a NAND gate, (36) is a predecoder output that decodes a block composed of four word lines, (37) is a transistor (16) to ( +8)
Vpp switch consisting of (38) to (40) are V
I) It shows that it has the same circuit configuration as the rl switch (37). (41) is a word line power supply line which becomes Vpp during writing and Vcc during reading.

Also, (28) (30) (32) (:I4
) is a positive logic signal, (27) (29) (31)
(:+3) are (28) (30) (32) respectively
(34) is a negative logic signal.

Next, the operation will be explained.

In this conventional decoding method, a block consisting of four word lines is selected by a NAND gate (35), and one block from the four word lines is selected by transistors (19) to (26).
Select the book's word line. First, the predecode signal (3
6) The output of the NAND gate (35) becomes "L" after reaching "H". When selecting the word line WL+ (9), the positive predecode signal (28) becomes "H". ,
The negative predecode signal (27) becomes "L". As a result, the transistor (20) is turned on, and the transistor (1) is turned on.
9) is turned off, so N is applied to the Vpp switch (37).
The output "L"' of the AND gate (35) is input manually. V
When the PP switch is set to "L" or manually operated, its output rises to the level of the power supply line VPPWL (41) -F.
When “°H”° is input manually, the output is set to “L” level. Therefore, in the case of writing, the power line VPPWL (
41) Since it becomes LLVpp, the output of the VpI) switch (37), that is, the word line WLI (9), becomes Vpp.
Rehelebe becomes. In addition, in the case of reading, the power supply line VPPWL
(41) becomes Vcc, so the word line WLI
(9) becomes the Vcc level. At the same time, the positive predecode signals (30), (32), and (34) are "L", and the negative predecode signals (29, (31), and (33) are "L".
Since it is H-pass, transistors (22) (24
) (26) turns off and transistor (2]) (
23) (25) turns on. Therefore, Vl)I)
Switches (38) (:19) (40) are set to “H”.
” is manually operated, VpI) switch (38) (
39) The output of (40), that is, the word line (10) (
11) (12) is °゛L゛L゛ level. At this time, since at least one input of the N to ND gate of the other block is at "L", its output becomes "H".

Therefore, even if the transistor corresponding to the transistor (20) in another block is turned on and the transistor corresponding to the transistor (19) is turned off, the voltage applied to the Vl)I) switch is "H" level. Therefore, the word line becomes L°" level. By the above operation, only one word line is selected and the other word lines are made selected.

[Problem to be solved by the invention]

Since the conventional nonvolatile semiconductor memory device is configured as described above, the memory cell size of the flash EEPROM can be made extremely small because the memory cell is configured with only one transistor. However, 3
A Vl)p switch circuit consisting of two transistors is required for each word line.
There was a problem in that the layout of the pp switch was extremely difficult.

This invention was made to solve the above problems, and even if the memory cell size becomes smaller, the Vll
l) The object is to obtain a nonvolatile semiconductor memory device that enables switch layout.

[Means to solve the problem]

The nonvolatile semiconductor memory device according to the present invention connects the output of the Vpp switch to word lines of a plurality of memory cell rows that are not connected to the same source line, and connects the source line to °゛L°L.
The system is equipped with means for switching between the 3 and 3 route routing states.

[Effect]

The nonvolatile semiconductor memory device according to the present invention includes means for connecting the output of the Vpp switch to a plurality of memory cell rows that are not connected to the same source line, and switching the source line between the "°L" level and a floating state. Therefore, even if the memory can be highly integrated and the size of the memory cell can be reduced, the layout of the Vpp switch can be easily performed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing part of a memory array and part of a row decoder circuit. In the figure, the same reference numerals as those in the conventional device are the same, and the explanation thereof will be omitted.

In the figure, (42) (4:l) are mutually independent source lines, (44) (45) are source lines (42)
(43), an N-channel transistor controlling (43);
6) (47) is a signal that codes the source lines (42) and (43), and the word lines of two memory cell rows that are not connected to the same source line (WLI and WL3, WL2 and W
Connect L4) to the output of the same-VIII) switch.

In this embodiment, a case will be described in which the output of one Vpp switch is connected to two word lines.

Next, the operation will be explained. Here, a case will be described in which a memory cell connected to word line WLI is selected. V
l) The process up to the input of "L" to the p switch (37) is the same as the conventional one.

In the case of reading, since VPPWL (4) becomes Vcc, the output of the VpI) switch (37), that is, the word lines WLI (9) and Wl,3 (11), becomes Vcc.
become the level. Also, source line decode signal A (4B)
to L" level, source line decode signal B (47) to "
By setting the level to H, the transistor (44) is turned off and the transistor (45) is turned on. As a result, the source line (42) is floating, and the source line (4:]) is "
It becomes L” level. When reading, it is B old (13),
A potential of about 1.5 V is applied to both BL2 (+4), and a sense amplifier (not shown) connected to the bit line senses whether or not current flows in the memory cell. When current flows through the memory cell, the threshold voltage is in a low state (erased state), and when no current flows, the threshold voltage is in a high state (written state). When the memory cell (1) is in the erased state, the word line WLI (9) is at the Vc, c level and the source line (43) is at the L'' level as explained above, so the memory cell (1) is in the erased state. Since it is turned on and current flows, reading can be performed.When the memory cell (1) is in the write state, the word line WLI (9)
Although the source line (43) is at the above level, no current flows through the memory cell (1) because the threshold voltage of the memory cell (1) is high. At this time, even if the memory cells (5) and (6) connected to the word line WL3 (11), which simultaneously attains the Vcc level, are in the erased state, no current flows through the bit line BLI (13) for the following reason. When memory cells (5) and (6) are in erased state, word line WL3
(11) is at the Vcc level, the memory cells (5) and (6) are turned on, and the level of the floating source line (42) becomes 1.5V. However, since there is no bus through which current flows, the bit line BLI (
No current flows through 13).

In case of writing, power line VPPWL (41) is Vl
)p, the output of the Vpl) switch (37), that is, the word lines WLI (9) and Wl3 (11), becomes the Vl)p level. Also, as in the case of reading, when the decode signal (47) is set to "H", the transistor (44) is turned off, the transistor (45) is turned on, (42) is floating, and (43) is low. When writing to memory cell (1), word line WLI (9) 2Vpp, source line S
1, 2 (4:]) “L” level, bit line 81, +
(+3) is given a potential of about 6V. At this time, a current flows from the drain to the source of the memory cell (1), and hot electrons generated near the source are injected into the floating gate. Since electrons are accumulated in the floating gate, the threshold voltage of the memory cell (1) becomes high. Furthermore, the bit line BL2 (+4) on which writing is not performed is floating. Under the above potential conditions, word line WL3 (11) is also Vllll+
Level (5) (42) (6)
(14) Current flows through the path shown in (2). However, compared to the current flowing in memory cell (1),
Since the latter current is sufficiently small, memory cells (5) (6)
Since the number of hot electrons generated in (2) is negligible, there is no fluctuation in the threshold voltage.

When selecting a memory cell connected to word line WL3 (11), source line decode signal A (4B) is set to “
Ho” level, source line decode signal B (47) is “
This is done by setting the word line WL2 to Lo” level.The subsequent operation is the same as that for the word line WLI.
, Wl4 is selected.

〔Effect of the invention〕

As described above, according to the present invention, one
Since only one Vpp switch is required, the memory can be highly integrated, and even if the memory cell size is reduced, the layout of the Vpp switch can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing part of a memory array and part of a row decoder circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing part of a conventional memory array and part of a row decoder circuit. It is a diagram. In the figure, (1) to (8) are memory cells, (9) to (
12) is a word line, (+3) (14> is a hit line,
(15) is a source line, (16) to (22) are transistors, (27) to (30) (36) are predecoder outputs, (35) are NAND gates, (37) (38)
C shows the Vpp switch. In addition, in the figures, the same reference numerals indicate the same or identical parts.

Claims (1)

[Claims] The output of the Vpp switch arranged in the row direction is connected to word lines of a plurality of memory cell rows that are not connected to the same source line, and means is provided for switching the source line to an "L" level and a floating state. A nonvolatile semiconductor memory device characterized by: