KR19980045921A - 원소 티타늄이 없는 라이너 및 금속간 연결을 위한 제조 공정 - Google Patents

원소 티타늄이 없는 라이너 및 금속간 연결을 위한 제조 공정 Download PDF

Info

Publication number
KR19980045921A
KR19980045921A KR1019960064166A KR19960064166A KR19980045921A KR 19980045921 A KR19980045921 A KR 19980045921A KR 1019960064166 A KR1019960064166 A KR 1019960064166A KR 19960064166 A KR19960064166 A KR 19960064166A KR 19980045921 A KR19980045921 A KR 19980045921A
Authority
KR
South Korea
Prior art keywords
cavity
liner
metal
aluminum
vias
Prior art date
Application number
KR1019960064166A
Other languages
English (en)
Korean (ko)
Inventor
기리쉬 에이. 딕시트
Original Assignee
윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윌리엄 이. 힐러, 텍사스 인스트루먼츠 인코포레이티드 filed Critical 윌리엄 이. 힐러
Publication of KR19980045921A publication Critical patent/KR19980045921A/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019960064166A 1995-12-12 1996-12-11 원소 티타늄이 없는 라이너 및 금속간 연결을 위한 제조 공정 KR19980045921A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US844495P 1995-12-12 1995-12-12
US60/008,444 1995-12-12

Publications (1)

Publication Number Publication Date
KR19980045921A true KR19980045921A (ko) 1998-09-15

Family

ID=21731636

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960064166A KR19980045921A (ko) 1995-12-12 1996-12-11 원소 티타늄이 없는 라이너 및 금속간 연결을 위한 제조 공정

Country Status (2)

Country Link
JP (1) JPH09275141A (ja)
KR (1) KR19980045921A (ja)

Also Published As

Publication number Publication date
JPH09275141A (ja) 1997-10-21

Similar Documents

Publication Publication Date Title
US6949461B2 (en) Method for depositing a metal layer on a semiconductor interconnect structure
US6949450B2 (en) Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber
US6217721B1 (en) Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer
US6566242B1 (en) Dual damascene copper interconnect to a damascene tungsten wiring level
US6426289B1 (en) Method of fabricating a barrier layer associated with a conductor layer in damascene structures
US7799693B2 (en) Method for manufacturing a semiconductor device
US6207222B1 (en) Dual damascene metallization
US6846741B2 (en) Sacrificial metal spacer damascene process
EP1570517B1 (en) A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
US7145241B2 (en) Semiconductor device having a multilayer interconnection structure and fabrication process thereof
KR100440418B1 (ko) 저압,저온의반도체갭충전처리방법
US6002176A (en) Differential copper deposition on integrated circuit surfaces
US5849367A (en) Elemental titanium-free liner and fabrication process for inter-metal connections
US6713407B1 (en) Method of forming a metal nitride layer over exposed copper
US7830019B2 (en) Via bottom contact and method of manufacturing same
US6258716B1 (en) CVD titanium silicide for contact hole plugs
WO2002046489A1 (en) Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber
KR19980045921A (ko) 원소 티타늄이 없는 라이너 및 금속간 연결을 위한 제조 공정
KR100424835B1 (ko) 장벽을갖지않는반도체구조및이러한구조에서의금속간접속형성방법
KR20030059456A (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application